AUTO-TUNED MINIMUM-DEVIATION DIGITAL CONTROLLER FOR LLC RESONANT CONVERTERS

Transcription

1 AUTO-TUNED MINIMUM-DEVIATION DIGITAL CONTROLLER FOR LLC RESONANT CONVERTERS by SeyedehMayam SeyedAmouzandeh A thesis submitted in confomity with the equiements fo the degee of Maste of Applied Science Gaduate Depatment of Electical and Compute Engineeing Univesity of Toonto Copyight by SeyedehMayam SeyedAmouzandeh 2015

2 AUTO-TUNED MINIMUM-DEVIATION DIGITAL CONTROLLER FOR LLC RESONANT CONVERTERS Abstact SeyedehMayam SeyedAmouzandeh Maste of Applied Science Gaduate Depatment of Electical and Compute Engineeing Univesity of Toonto 2015 This thesis pesents a pactical auto-tuned digital contolle fo LLC esonant dc-dc convetes that esults in vitually minimal possible output voltage deviation duing tansients. Duing tansients the contolle applies a two-step fequency change algoithm such that the minimum deviation and seamless tansition to the new steady state is achieved. The fast voltage egulation is obtained though the output voltage measuements only and faily simple calculations of the fequency-changing sequence, eliminating fast cuent sensos and complex calculations usually existing in othe fast contolles fo LLC convetes. Based on the initial voltage deviation the fist fequency step of the contolle is detemined and adjusted though an auto-tuning pocess. Smooth tansition to the new steady state is achieved though the estimation of the new switching fequency fom the ipple amplitude. Expeimental esults obtained with a 350 W, 400 V to 12 V, isolated LLC convete confim ecovey with pactically smallest possible deviation and bump-less tansitions to the new steady state. ii

3 Acknowledgments Fistly, I would like to expess my sincee gatitude to my adviso Pof. Podić fo the continuous suppot and guidance in all the time of eseach and witing of this thesis and also thoughout the two yeas of my gaduate study. His encouaging wods thoughout my eseach motivated and kept me going which was invaluable to my thesis. I could not have imagined having a bette adviso and mento. Besides my adviso, I would like to thank all my fiends and pees in the Laboatoy fo Powe Management and Integated Switch-Mode Powe supplies. I am gateful to D. Behzad Mahdavikhah fo his patience, motivation, and immense knowledge. Without his pecious suppot it would not be possible to conduct this eseach. To all the est of my colleagues and fiends, D. S.M. Ahsanuzzan, Nenad Vukadinović, Mahmoud Shousa, Tim McRae, Am Amin, Path Jain and Shadi Dashmiz fo poviding me suppot to ovecome some of the obstacles and fo all the fun we have had in the last two yeas. I would like to acknowledge the suppot of Texas Instuments and Bent McDonald fo sponsoing this exciting and challenging poject. Last but not the least, I would like to thank my paents who have povided me with unconditional love and suppot thoughout my life. They have always been an inspiation to me, I know I can neve be thankful enough to them. Special thanks to my sistes Zaha and Nages fo suppoting me spiitually thoughout my life. Also, my niece, Atisa and nephew, Asam who kept me laughing and smiling though the had times. iii

4 Table of Contents Acknowledgments... iii Table of Contents... iv List of Tables... vi List of Figues...vii Chapte Intoduction Backgound and Objective Pevious At and Reseach Motivation LLC Dynamic Pefomance Synchonous Rectification Contolle Thesis Oveview... 6 Chapte Review of LLC Resonant Convete Intoduction Resonant Mode Convete Topologies Seies esonant convete (SRC) Paallel esonant convete Seies paallel esonant convete LLC Resonant Convete Pinciples of Opeation Chapte Auto-Tuned Minimum-Deviation Digital Contolle fo LLC Resonant Convetes Intoduction Pinciple of Opeation Pactical Implementation iv

5 3.4. Simulation Results Chapte Digital Synchonous Rectification Contolle Intoduction LLC Resonant Opeation LLC Resonant Convete with Diode Rectifie LLC Resonant Convete with Synchonous Rectifie Pinciple of opeation and Pactical Implementation Chapte Expeimental Results Chapte Conclusions and Futue Wok Futue wok Refeences A Optimal Tajectoy Analysis fo Load Tansients A.1 LLC esonant steady state tajectoy in 2D A.2 LLC Load Tansient Tajectoies in State-Plane A.2.1 Light to Heavy Load Tansient A.2.2 Heavy Light to Load Tansient B Implementation of Functional Blocks B.1 VCO Block B.2 Voltage Deviation, H2L and L2H Detection B.3 Ripple measuement and PID Re-Initialization C Appoximation fo the Chage (Equation (3.13)) v

6 List of Tables Table 1: Mode I Table 2: Mode II Table 3: Mode III Table 4: mode IV Table 5: Mode V Table 6: Mode VI vi

7 List of Figues Figue 1-1: Distibute Powe System (DPS)... 2 Figue 1-2: half-bidge LLC esonant convete... 2 Figue 1-3: LLC esonant convete with synchonous ectifie on the seconday... 5 Figue 1-4: Pimay side cuent sensing fo SR diving Figue 2-1: Cicuit diagam of a half bidge Seies Resonant Convete (SRC)... 8 Figue 2-2: DC voltage gain chaacteistic of seies esonant convete (SRC)... 8 Figue 2-3: Cicuit diagam of a half bidge Paallel Resonant Convete (PRC) Figue 2-4: DC chaacteistic of Paallel Resonant Convete (PRC) Figue 2-5: Half bidge SPRC, LCC esonant convete Figue 2-6: DC chaacteistic of LCC esonant convete Figue 2-7: Half-bidge LLC esonant convet Figue 2-8: DC chaacteistic of LLC esonant convete Figue 2-9: LLC esonant convete wavefoms at the esonant fequency Figue 2-10: LLC esonant convete equivalent cicuits opeating below esonance Figue 2-11: LLC esonant convete wavefoms opeating below the esonant fequency Figue 2-12: LLC esonant convete wavefoms opeating above the esonant fequency Figue 3-1: LLC esonant convete with PID and tansient suppession contolle Figue 3-2: Key wavefoms of LLC esonant convete duing tansient. Wavefoms fom top to bottom: output voltage; load cuent; switching signals; tank and magnetizing inducto cuent; and switching fequency vii

8 Figue 3-3: Magnetizing and tank cuent, output capacito voltage, and output capacito cuent wavefoms fom simulation Figue 3-4: Compaison between function Y of equation (3-17) and its appoximated piecewise linea intepolation Figue 3-5: LLC esonant convete block diagam with detailed contolle blocks Figue 3-6: Contolle flowchat Figue 3-7: Auto-tuning flowchat of facto K Figue 3-8: Simulation esults fo a light to heavy load tansient with a well-tuned PID compensato Figue 3-9: Simulation esults fo a light to heavy load tansient with the intoduced contolle. 30 Figue 4-1: LLC esonant convete with SR on the seconday side and digital contolle Figue 4-2: Simulation esults of LLC opeating below esonance; G1 and G2 ae main switches diving signal; ig1 and ig2 ae main switches cuents; ilm and il ae magnetizing and tank inducto cuents espectively; idsr1 and idsr2 ae ectifie body diode cuents Figue 4-4: Simulation esults of LLC opeating above esonance; G1 and G2 ae main switches diving signal; IG1 and IG2 ae main switches cuents; ILm and IL ae magnetizing and tank inducto cuents espectively; IDSR1 and IDSR2 ae ectifie body diode cuents Figue 4-5: LLC esonant convete equivalent cicuits opeating above esonance Figue 4-6: Simulation esults of LLC esonant convete with SR while SR synchonously tuns on with the main switch. a) Opeating above esonance. b) Opeating below esonance; G1 and G2 ae main switches diving signal; idsr and GDSR1 ae the SR cuent and diving signals Figue 4-7: a) SR tun off contolle flowchat; b) SR tun on contolle flowchat Figue 4-8: Timing diagam, ISR is the SR cuent, VdsSR is the SR switch dain to souce voltage, GSR is the SR gating signal viii

9 Figue 5-1: Expeimental setup Figue 5-2: Dynamic esponse of LLC esonant convete fo light to heavy load tansient. vout is the output voltage measuement signal (200mV/div). iload is the load step cuent (10A/div); vsw_node is the switching node voltage Figue 5-3: Dynamic esponse of LLC esonant convete fo heavy to light load tansient. vout is the output voltage measuement signal (200mV/div); iload is the load step cuent (10A/div); vsw_node is the switching node voltage Figue 5-4: Tansient esponse of a 3 to 15A load step a) with PID e-initialization, b) without PID e-initialization. vout is the output voltage measuement signal (100mV/div). iload is the load step cuent (5A/div); vsw_node is the switching signal Figue 5-5: Dynamic esponse of LLC esonant convete fo light to heavy load tansient a) with intoduced contolle and Cout=1645 µf, b) with conventional contolle and Cout=2585 µf. vout is the output voltage measuement signal (200mV/div). iload is the load step cuent (10A/div); vsw_node is the gating signal; Time scale is 50us/div Figue 5-6: Auto-tune of facto K fo light to heavy load tansients. vout is the output voltage measuement signal (200mV/div). iload is the load step cuent (10A/div); G1 is the gating signal and facto K is shown in 5 bits; Time scale is 100 ms/div Figue 5-7: Zoomed in vesion of Figue 5-6 at updating times Figue 5-8: Expeimental esults, a) SR diving signals in synchonous with the pimay side switches; b) SR diving signals with modified on time. SRDET1 is the QSR1 body diode conduction detection signal; GSR1 is the QSR1 gating signal; vdssr1 is the QSR1 dain to souce voltage 20 V/div.; vx pimay side witching node voltage. Time is 2 us/div Figue A-1: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode I.. 52 Figue A-2: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode II 53 Figue A-3: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode III54 ix

10 Figue A-4: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode IV55 Figue A-5: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode V 56 Figue A-6: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode VI57 Figue A-7: State tajectoy duing load step up Figue A-8: LLC esonant convete wavefoms duing load step up Figue A-9: State tajectoy duing load step down Figue A-10: LLC esonant convete wavefoms duing load step down Figue B-1: Functional blocks used in the intoduced contolle Figue B-2: Conventional VCO implementation Figue B-3: Expeimental esult using conventional VCO Figue B-4: Univesal VCO implementation Figue B-5: expeimental esult using the univesal VCO Figue B-6: Diving signal compaison using conventional and univesal VCO Figue B-7: Voltage Dop, H2L and L2H Detection Figue B-8: Ripple measuement and PID Re-Initialization x

11 1 Chapte 1 1. Intoduction The objective of this thesis is to design a contolle fo LLC esonant convetes with a fast tansient esponse. In this chapte a liteatue eview on the LLC esonant convete is pesented, and its advantages and applications ae investigated. The contol challenges and the impotance of the pope synchonous ectification ae also addessed Backgound and Objective With inceasing demand fo fast dynamic loads such as telecoms, seves, desktops, laptops and notebooks, Distibute Powe System (DPS), has been widely used fo its ability to impove the system oveall efficiency [10]. As shown in Figue 1-1 in a DSP, powe is usually pocessed by thee stages, the fist two stages fom a font-end convete which is connected to the utility line. In the last stage point-of-load convetes ae placed close to each fast dynamic load [10]. As shown in Figue 1-1, font-end convete is consist of two convesion convetes. Fist stage usually convets ac input to a 400 V dc while poviding powe facto coection (PFC). Second stage is the font-end dc-dc convete, convets 400V dc into a 12V dc. High efficiency and high powe density ae desied fo font-end convetes to educe the convete cost while having an acceptable pefomance. Theefoe, these convetes need to opeate at high fequency to have a high powe density while maintain high efficiency. In these applications LLC esonant convetes ae being widely used as font-end convetes because of thei ability to achieve highe powe density and efficiency than the had switching solutions. LLC esonant convetes ae also able to opeate ove a wide input voltage ange. A half-bidge LLC esonant convete is shown in Figue 1-2.

12 2 12V DC Bus Point of Load convete Load 1 Point of Load convete Load 2 AC PFC 400 V dc DC/DC 12 V dc Font End Convete Point of Load convete Load 3 Point of Load convete Load n Figue 1-1: Distibute Powe System (DPS) G 1 L T n:1:1 D SR2 V g G 2 C Lm D SR1 Cout Rload + V out - Figue 1-2: half-bidge LLC esonant convete LLC esonant convete is contolled with pulse fequency modulation technique. Howeve, since dynamic chaacteistic of LLC convetes changes with opeation conditions [1], [2], i.e. fo vaious input/output voltages and loads, thei contol is moe challenging than that of hadswitching PWM convetes. Fo PWM convetes the natual fequency of the system, L.C. output filte is much lowe than the switching fequency. Fo that eason in the modeling

13 3 pocess components of switching fequency can be neglected. Howeve, LLC esonant convetes usually opeate at a switching fequency that is close to the natual fequency of the esonant tank, in ode to obtain bette powe pocessing efficiency [1]. Theefoe, it is much moe complex to descibe the esonant tank small-signal model [1]-[3] Pevious At and Reseach Motivation As explained ealie, impoving the dynamic pefomance of the LLC esonant convete duing tansients is challenging due to opeating condition dependent chaacteistics of the convete. Theefoe, the main objective of this thesis is to design a simple and eliable contolle fo LLC esonant convete which impove the tansient esponse using digital contolle. In ode to impove the oveall efficiency of the convete, the seconday side can be eplaced with a synchonous ectifie. The contolle to dive the seconday side switches to eliminate the body diode conduction of the switches and avoid any ciculating cuent is also studied. In the following sections a liteatue eview on dynamic pefomances and contol of the LLC esonant convetes is pesented. Also a eview of the pevious at on contol of synchonous ectifie is given LLC Dynamic Pefomance LLC esonant convetes demand tight output voltage egulation while maintaining good dynamic pefomance duing tansients. Theefoe advanced contol algoithm ae needed to povide mentioned equiements. LLC esonant convete chaacteistics changes as the convete opeating point change, theefoe commonly used analog contolles which ae often designed to opeate in only one mode, have vey limited dynamic pefomances. Digital contolles allow moe complex algoithm and can be implemented fo impove efficiency and dynamic pefomances [12]. Digital contolles ae also moe flexible, eliable, cost effective and less sensitive to noise and component vaiations. To impove dynamic pefomance of LLC convete contolles, a numbe of methods has been poposed in the past.

14 4 In [4], the authos implement and compae a digital PID and fuzzy logic contolle (FLC) on a half-bidge DC/DC LLC esonant convete. Howeve, since this contolle does not equie accuate mathematical model of the system it has not demonstated bette small signal pefomance than standad egulatos. In [5], a sliding-mode contol scheme fo LLC esonant convete is pesented. The poposed contolle opeates at two fixed switching fequencies. The poposed contol method impoves the dynamic pefomance of the convete, but shows sensitivity to convete paametes and the discontinuous high speed switching action esults in the chatteing poblem. Authos in [6], poposed a simplified optimal tajectoy contol (SOTC) fo the LLC esonant convete. Duing the steady state, a linea compensato is used, and duing load tansients, the SOTC contols the system. The SOTC changes the pulse-width of the gate diving signals based on complex calculation to get in to the new state in the optimal i.e. fastest possible time. This method equie costly, fast, and accuate load cuent measuement along with input voltage measuement. The othe disadvantage of this contolle is its sensitivity to convete paametes Synchonous Rectification Contolle To educe the conduction losses on the seconday side of the LLC esonant convete, the synchonous ectifies (SR) as shown in Figue 1-3 should be employed. Howeve the diving signals fo the SR switches need to be caefully timed, since they ae not in phase with the pimay side signals. Inaccuate timing of SR diving signals deceases the oveall efficiency. In the case of shote diving signals the body diodes of SR switches conduct, inceasing the conduction losses. In the case of longe diving signals the ciculating cuent fom the load to the souce would educe the efficiency damatically. In [19], a method to geneate the SR deiving signals based on the SR cuent sensing by tansfomes is intoduced. This method suffes fom additional losses due to high seconday cuent and enegy losses of the tansfome windings.

15 5 G 1 L I P T n:1:1 V g G 2 C L m Cout Rload + V out - Figue 1-3: LLC esonant convete with synchonous ectifie on the seconday Authos in [20] ae also using a tansfome to sense the SR cuent, howeve they sense the pimay side cuent since it is smalle compaed to the seconday side cuent. Theefoe the losses associated to the tansfome windings ae lowe. Howeve, as it shown in Figue 1-4, Ip is popotional to the seconday side cuent. That means the magnetizing inductance of the tansfome needs to be extenal. As a consequent the integation of leakage, magnetizing inductos and tansfome in a single element is lost. G 1 L I P T n:1:1 V g G 2 C L m Sensing Tansfome Cout Rload + V out - Signal pocessing and SR diving Figue 1-4: Pimay side cuent sensing fo SR diving. In [28], [29] the SR body diode conduction detection cicuit is used to detect the fowad voltage dop on SR switches. In this method the SR diving signal is tuned until the cicuit cannot detect the body diode conduction anymoe. The main dawback of this method is a limit

16 6 on the maximum pulse width of the SR diving signal, which cannot be lage than that of the main switch. Howeve duing opeation above esonance the seconday switches need to emain in on-state longe than the pimay side signals. In [24] a digital auto tuned pocess fo the tun-off instant of the SR is poposed. Although the auto tuned tun off algoithm is pecise, the tun-on time instant is in synchonous with the pimay side switches. As it will be discussed in Chapte 4, fo a ealistic convete, the optimal SR tun on time instant is not fully synchonized with the pimay side switches and depends on the opeating conditions Thesis Oveview This thesis is oganized into six chaptes. In Chapte 1, the motivation to design a digital contolle fo LLC esonant convete is established. Pevious wok elated to impoving the dynamic pefomance and synchonous ectification ae also pesented. Chapte 2 povides a bief eview of basic esonant convete topologies and thei DC chaacteistics. The LLC esonant convete is pesented in moe detail. In Chapte 3, fist the design pocess of digital tansient contolle to achieve minimum voltage deviation is pesented. Next, simulation esults with PSIM softwae ae pesented that the esults also show the compaisons between the intoduced nonlinea contolle and a conventional linea contolle. In Chapte 4, fist the effect of impope tun on time is addessed and shown though simulation. Then, the digital synchonous ectifie contolle algoithm is pesented. Chapte 5 descibes the expeimental setup and pesents esults to validating the wok done in this thesis. Fist the expeimental esults show dynamic pefomance of the digitally contolled LLC esonant convete. Then the dynamic esponse of a conventional linea contolle is povided fo compaison. Finally, Chapte 6 summaizes the wok done in this thesis. Possible impovements and futue wok ae also discussed.

17 7 Chapte 2 2. Review of LLC Resonant Convete In this chapte seveal esonant convete topologies ae studied and the advantages and disadvantages of each topology ae pesented. Aftewads, the LLC esonant convete pinciple of opeation, the diffeent modes, and desied egions of opeation ae discussed Intoduction Resonant convetes can be designed to achieve low switching losses theefoe they ae able to opeate at high switching fequency. Theefoe these topologies ae having high efficiency, high powe density, i.e. low oveall volume, and low pofile. To find a topology that could have the optimal pefomance at nomal opeation condition, thee most popula esonant convete topologies have been investigated hee. Seies esonant convete (SRC), paallel esonant convete (PRC) and seies paallel esonant convete (SPRC) ae studied fo font-end applications Resonant Mode Convete Topologies Seies esonant convete (SRC) Figue 2-1 shows the cicuit diagam of a half bidge seies esonant convete (SRC) [13]. The dc input to output voltage gain chaacteistic of SRC is shown in Figue 2-2. Hee fn, the nomalized switching fequency is defined as f of the system. f s 0 1, and f0 is the esonant fequency LC 2

18 8 G 1 L T n:1:1 D SR2 V g G 2 C D SR1 Cout Rload + V out - Figue 2-1: Cicuit diagam of a half bidge Seies Resonant Convete (SRC) Figue 2-2: DC voltage gain chaacteistic of seies esonant convete (SRC) In this topology as it is shown in Figue 2-1 the esonant inducto L and the esonant capacito C ae in seies. They fom a esonant tank netwok which is in seies with the load. It can be seen that the esonant tank and the load make a voltage divide. Theefoe as it is shown in Figue 2-2 the dc gain fo this topology is always less than one. By changing the switching fequency the impedance of the esonant tank changes. The minimum impedance happens at the esonant fequency, thus the dc gain of the SRC is one when the switching fequency is equal to the esonant fequency.

19 9 It is known that the pat of the dc chaacteistic with the positive slope is the zeo-voltage switching (ZVS) egion, and the pat that has negative slope is the zeo-cuent switching (ZCS) egion [13]. Theefoe SRC can achieve ZVS on the ight side of the esonant fequency and ZCS on the left side. ZVS eliminates the switching losses in powe switches o powe MOSFET, theefoe the pefeed soft-switching mechanism of MOSFET devices is ZVS. It can be seen in Figue 2-2 that with load vaiation in ode to egulate the output voltage, the switching fequency vaies ove a wide ange of fequencies, especially at light load (smalle Q). This is the main disadvantage fo the SRC. Since it is known that the opeation aound the esonant fequency has the geatest efficiency, it is desied that convete opeate close to the esonant fequency [13]. Fo a wide input voltage ange, as the input voltage inceases, in ode to maintain the egulated voltage and emain in ZVS egion, the convete has to opeate of a highe switching fequency. As fequency inceases, the impedance of the esonant tank inceases, thus moe enegy ciculates in the esonant tank, which inceases the conduction losses. Consideing all above points, SRC is not the most suitable candidate fo font end applications. Although this convete can achieve ZVS and theefoe is able to educe switching losses, it is not an optimal topology fo wide input voltage ange and vaiable load applications [13] Paallel esonant convete Figue 2-3 shows a cicuit diagam of a half bidge paallel esonant convete (PRC) [13]. The nomalized dc chaacteistic of PRC is shown in Figue 2-4 in which fn is the nomalized switching fequency ( f s f 0 1 ), and f0 is the esonant fequency. LC 2 The esonant tank in PRC consists of a esonant inducto L and a esonant capacito C in seies. It is called paallel esonant convete, because the esonant capacito is in paallel with the load. Simila to SRC, the PRC can also achieve ZVS on the ight hand side of the dc gain chaacteistic and ZCS on the left hand side. The majo diffeence between these two topologies is, unlike SRC, PRC does not need to change the fequency ove a wide ange to egulate the output voltage. Theefoe, the light load egulation poblem doesn't exist in PRC.

20 10 Although the PRC does not have poblems in egulating the output voltage unde no-load condition it has a disadvantage, that the pimay side cuent is almost independent of the load condition. Since the load is in paallel with the esonant capacito, even at no load condition, the input still sees a small impedance of the esonant tank. This cause a high ciculating enegy even at no load and light load condition, negatively affecting the efficiency. G 1 L T n:1:1 D SR2 V g G 2 C + D SR1 L f Cout Rload V out - Figue 2-3: Cicuit diagam of a half bidge Paallel Resonant Convete (PRC) Figue 2-4: DC chaacteistic of Paallel Resonant Convete (PRC)

21 11 Simila to SRC, PRC ciculating cuent inceases as input voltage inceases so it is not a pope topology fo the applications with wide ange of input voltage Seies paallel esonant convete Seies paallel esonant convetes (SPRC) consist of thee esonant components. They can be divided into two majo categoies, LCC and LLC. LCC esonant convetes have two esonant capacito and one inducto, and LLC esonant convetes have one esonant capacito and two inductos. Each categoy has seveal configuations, depending on the esonant components placement. Figue 2-5 shows the cicuit diagam fo one configuation of a half bidge LCC esonant convete this topology consists of a esonant inducto L, esonant seies capacito Cs, and esonant paallel capacito Cp. The nomalized dc chaacteistic of the LCC esonant convete is shown in Figue 2-6. It can be seen that, depending on value of quality facto Q, moe than one esonant fequency exists, whee Q is given with: Q L 8 C (2-1) 2 2 nrload LCC esonant convete, combines advantages of PRC and SRC. The ciculating enegy is limited, since the load is in seies with L and Cs, theefoe the pefomance of the LCC esonant convete is bette than that of the PRC. Moeove, the paallel capacito Cp helps the LCC convete to egulate the output voltage at no load condition. Simila to SRC and PRC, to achieve ZVS the LCC needs to opeate on the ight side of the esonant chaacteistic. At highe input voltages, the convete is opeating at highe fequencies fa away fom esonant fequency. Simila to PRC and SRC with wide input ange, the conduction loss and switching loss will incease at high input voltage. Although the LCC esonant convete has smalle ciculating enegy compaed to PRC and is not so sensitive to load changes as SRC, it is still not the optimal topology fo the wide input voltage ange applications.

22 12 G 1 L T n:1:1 D SR2 V g G 2 C s Cp D SR1 L f Cout Rload + V out - Figue 2-5: Half bidge SPRC, LCC esonant convete Figue 2-6: DC chaacteistic of LCC esonant convete 2.3. LLC Resonant Convete Pinciples of Opeation Figue 2-7 shows a half-bidge LLC esonant convet, in this topology the magnetizing inductance of the tansfome is utilized as a esonant component. The LLC convete topology

23 13 consists of esonant inducto L, esonant capacito C, and magnetizing inducto Lm. Thee ae two esonant fequencies fo this convete, L and C detemine the highe esonant fequency, f0. The lowe esonant fequency, fp is detemined by C and the seies inductance of Lm and L. The two esonant fequencies ae: f 0 1 (2-2) LC 2 f p 1 2 ( L L ) C m (2-3) The quality facto Q and the atio L n between L m and L ae: L C Q (2-4) 2 nrl L n L L m (2-5) The nomalized dc input-to-output voltage gain chaacteistic of the LLC esonant convete fo diffeent Q is shown in Figue 2-8, in which fn, the nomalized switching fequency is defined as fs f 0. It can be seen fom Figue 2-8 that the voltage gain is equal to one fo all load conditions at the esonant fequency. As shown in Figue 2-8 the dc input-to-output voltage gain chaacteistic of the LLC esonant convete can be divided into thee egions, accoding to diffeent modes of opeation. Fist egion is when the convete switching fequency is highe than the esonant fequency f0. In this egion the gain is always less than one, and the slope of the dc chaacteistic is negative. So, the zeo-voltage switching (ZVS) fo pimay switches can be achieved. In the second egion, the switching fequency is between two esonant fequencies. The gain in this egion is moe than one and simila to the fist egion the ZVS fo pimay switches can be achieved. In the thid egion the zeo-cuent switching (ZCS) fo the pimay switches is achievable since the slope of

24 14 the dc chaacteistic is positive in this egion. Fo MOSFETs, the ZVS opeation is pefeed so the desied opeating egions ae 1 and 2. Since ZVS is not achievable in egion 3, the convete should be pevented fom enteing this egion. Figue 2-9 shows the LLC esonant fequency wavefoms while the convete woks at esonant fequency. It can be seen fom Figue 2-9, that the opeation of the LLC convete can be divided in six time intevals. The convete s equivalent cicuits ae shown in Figue G 1 L T n:1:1 D SR2 V g G 2 C Lm D SR1 Cout Rload + V out - Figue 2-7: Half-bidge LLC esonant convet Figue 2-8: DC chaacteistic of LLC esonant convete

25 15 G1 t G2 t i L i Lm t i D1 t i D2 t t 0 t 1 t 2 t 3 t 4 Figue 2-9: LLC esonant convete wavefoms at the esonant fequency Q 1 D 1 C 1 L T n:1:1 D SR2 Q 1 D 1 C 1 L T n:1:1 D SR2 V g V g Q 2 D 2 C 2 C Lm D SR1 Cout Rload + Vout - Q 2 D 2 C 2 C Lm D SR1 Cout Rload + Vout - a) b) Q 1 D 1 C 1 L T n:1:1 D SR2 Q 1 D 1 C 1 L T n:1:1 D SR2 V g V g Q 2 D 2 C 2 Lm Cout Rload C D SR1 + Q 2 Vout - c) d) D 2 C 2 C Lm D SR1 Cout Rload + Vout - Figue 2-10: LLC esonant convete equivalent cicuits opeating below esonance. Between time t0 and t1, is non-ovelapping time. Figue 2-10-a shows the equivalent cicuit duing this time inteval. Both switches on the pimay side ae in off state and zeo cuent goes though the seconday side. Duing this time inteval magnetizing cuent on the pimay will dischages C1 and chages C2.

26 16 Figue 2-10-b shows the time inteval between t1 and t2. The body diode of the pimay switch Q1 is conducting. On the seconday side, the diode DSR2 is conducting. Switch Q1 can be tuned off at any time duing this inteval and ZVS can be achieved. As it shown in Figue 2-10-c, duing time inteval between t2 and t3, switch Q1 and diode DSR1 ae conducting. Powe tansfe fom the pimay side to the output load takes place duing this time inteval. Also the constant output voltage (Vout) is eflected on the pimay, geneating the linealy inceasing magnetizing cuent ilm. Once the esonant tank cuent eaches the magnetizing cuent so the cuent though DSR1 is zeo this inteval ends with ZCS. The next half switching cycle is simila to the fist half cycle. While opeating at esonant fequency, LLC esonant convete pimay side switches tun off time instance is the same time that the esonant tank cuent needs to each the magnetizing cuent, labeled as t3. All pevious analysis is fo the convete opeation at esonant fequency. In the following the diffeences of the cicuit behavio when the convete opeates above and below esonance ae studied. The LLC esonant wavefoms fo opeation below the esonant fequency ae shown in Figue 2-11, and 2-12 espectively. Fo the case when convete opeates below esonance, fundamental sine wave has a shote peiod than that of the switching fequency. The seconday side cuent eaches zeo at t3, befoe the pimay switch tuns off. Afte this time, the esonant capacito foms a esonant cicuit with the tank inducto in seies with the magnetizing inducto and the cuent going though the pimay is that of the magnetizing cuent. Fo the case that convete opeates above esonance, the esonance peiod is longe than that of the switching peiod. At the end of a switching half peiod the tank cuent is highe than the magnetizing cuent. This cuent diffeence depends on the load condition and the distance of the switching fequency fom the esonant fequency. Duing the dead time inteval, the tank cuent falls apidly to the value of the magnetizing cuent.

27 17 G1 t G2 t i L i Lm t i D1 t i D2 t t 0 t 1 t 2 t 3 t 4 Figue 2-11: LLC esonant convete wavefoms opeating below the esonant fequency. G1 t G2 t i L i Lm t i D1 t i D2 t t 0 t 1 t 2 t 3 t 4 Figue 2-12: LLC esonant convete wavefoms opeating above the esonant fequency.

28 18 Chapte 3 3. Auto-Tuned Minimum-Deviation Digital Contolle fo LLC Resonant Convetes In this chapte, a simple digital contolle fo the LLC esonant convete is intoduced. Duing the steady state, a linea compensato (PID) contols the switching fequency (fs), to eliminate the steady-state eo. Duing tansients the contolle applies a two-step fequency change algoithm, such that minimum deviation fom the desied output voltage and a seamless tansition to the new steady state is achieved. The intoduced solution is implemented with an expeimental pototype. Obtained expeimental esults show significant impovement compaed to a conventional analog contolle Intoduction The LLC isolated esonant convetes ae widely used in dc-dc applications whee thee is a need to step down high input voltage to a much lowe level. As mentioned befoe, the most common example include font-end dc-dc stages educing a high voltage obtained fom a PFC ectifie to a bus voltage level, fo consume electonics, computes, and telecom applications. The LLC convetes ae widely adopted because of thei high efficiency, high powe density, and low electomagnetic intefeence (EMI) emissions [1-3]. If popely contolled, LLC convetes can achieve naow switching fequency ange, zeo voltage switching (ZVS) of pimay side switches, and zeo cuent switching (ZCS) of seconday switches (o ectifie diodes) [4-6]. By eliminating the need fo magnetics on the seconday side, these convetes also minimize stess on ectifie diodes [1],[2]. Howeve, since dynamic chaacteistic of LLC convetes change with opeation conditions [3], thei contol is moe challenging than that of conventional had-switching solutions. Conventional methods such as state space aveaging

29 19 have failed to model LLC esonant convetes accuately because of the lagely vaying chaacteistic with opeating condition [3]. Commonly, simulation based methods [2] have been utilized to design linea PID compensato based contolles with faily low-bandwidth, which povide stability ove the full ange of opeating conditions [2]. The main dawback of this design is a equiement fo a lage output filte capacitos and, in some cases, inceased cuent and voltage stess of the components [1]. To impove dynamic pefomance of LLC convete contolles, a numbe of methods [4-6] have been poposed in the past. Among the most effective ae poximity time-optimal contolles, namely the simplified optimal tajectoy contolle [6] and the sliding mode contolle [5]. These contolles achieve vitually the fastest possible esponse and, theefoe, a small output voltage deviation fo step changes, allowing fo a dastic eduction of the output capacito. Howeve, the optimal contolles have not been widely adopted, mostly due to elatively high complexity of implementation and, in some cases, sensitivity to convete paamete vaiations [6]. These digital contolles equie costly sensos fo fast and accuate cuent measuement and complex calculation of fequency-changing patten duing tansients. It this thesis a digital contolle is intoduced that, pactically esults in the smallest possible output voltage deviation without a need fo costly cuent sensos o complex calculations. The new contolle, whose simplified diagam is shown in Figue 3-1, opeates in two modes. In steady-state it woks as a conventional fequency-egulated voltage mode contolle. Once a tansient is detected, the key element of the new contolle, the tansient suppession block, is activated. Based on the output voltage measuements only, this block makes two successive fequency step changes to get to the new steady state. In the fist step the effect of the load change on the output capacito cuent is evesed in the fastest possible manne. The fequency coesponding to the new steady state is set in the second step. The fist fequency step is calculated fom the initial voltage deviation caused by a load tansient and adjusted though an auto-tuning pocess. The new steady state fequency esulting in a bump-less tansition fom the tansient mode is calculated fom the ipple measuements. The tansient suppession method, which will be descibed in the following section, is insensitive to convete paamete vaiations and equies simple hadwae fo implementation.

30 20 G 1 T n:1:1 v g G 2 v x L Lm Cout +12 V + Rload v out C - H 1 v out(t) Digital Contolle G 1 (t),g 2 (t) VCO f ss [n] f t [n] Steady State Mode PID Compensato tansient suppession Tansient Mode e v [n] _ + V ef H 1 v out (t) H 1 v out [n] ADC Figue 3-1: LLC esonant convete with PID and tansient suppession contolle Pinciple of Opeation The opeation of the tansient suppession logic, which is the key novelty of the contolle, is inspied by the minimum deviation method fo had switching convetes pesented in [13], [14]. Simila to the pevious solutions, the goal of obtaining the minimum output voltage deviation is achieved though evesing the output capacito chaging/dischaging pocess until the capacito voltage deviation, i.e. its deivative, changes the sign and the peak/valley point is detected. At that exteme point the inducto cuent of the system is also bought to its new steady state and the steady-state PID compensato is epogammed and eactivated. Fo the LLC convete, which key wavefoms duing tansient ae shown in Figue 3-2, the implementation of the minimum deviation method is moe challenging than fo the had switching solutions. This is because the elation between the inducto and capacito chaging/dischaging cuent is moe complex. Anothe poblem is that, unlike in had switching

31 21 voltage mode solutions, whee fo constant input voltage the duty atio in steady states befoe and afte tansient does not change much, the steady-state contol vaiable fo the LLC contolle vaies significantly. As it can be seen fom Figue 3-2, the switching fequencies pio to the load tansient and in the new state afte the tansient has been suppessed ae not the same. Achieving seamless tansition fom tansient to the new steady state mode is thus moe challenging since the contol vaiable value fom the pio steady state cannot be diectly used. The opeation of the intoduced minimum-deviation LLC contolle can be explained by looking at the diagam of Figue 3-1 and wavefoms of Figue 3-2. The tansient suppession block changes the switching fequency of the system afte detecting the tansient based on the initial voltage deviation vout. This initial value is used to detemine the size of the fist fequency step ft in the ecovey pocess. v out Tansient detection delay Δv out V ipple,ss v ipple,t I Load Valley point Dead time G 1 G 2 i L i Lm f s f ss f PID f t f ss_new Figue 3-2: Key wavefoms of LLC esonant convete duing tansient. Wavefoms fom top to bottom: output voltage; load cuent; switching signals; tank and magnetizing inducto cuent; and switching fequency

32 22 The value ΔT, changing in pulse width, is calculated stating fom the analysis pesented in [6]. The complete deivation is given in Appendix A. Thee, it is shown that the pulse width change fo light-to-heavy load tansients and the new pulse width fo heavy-to-light load tansients of a LLC convete esulting in a one-step ecovey of the inducto cuent ae: L m TLH,max IL and (3-1) nvg T HL ILL Ts,max (1 ), (3-2) I 4 HL whee Ts is the switching peiod befoe the tansient, IL is the load step, while, ILL and IHL ae load cuent values at light load and heavy load, espectively. (3-2) can be modified to: T HL Ts I L,max (1 1/ (1 )). (3-3) 4 I LL Also the output cuent is elated to the voltage, T s vout, t IL, (3-4) Cout whee Δvout,t is the initial voltage deviation caused by the tansient and Cout is the output capacito value. Fom Figue 3-3 load cuent can be calculated based on voltage ipple (Δvipple) and the value of the output capacito which can be calculated fom the capacito chage, Q. Δvipple in Figue 3-3 is the output voltage diffeence between two exteme points, point a and point b. Points a and b can be detemined fom solving the deivative of the output voltage equal to zeo. The output voltage is: Solving vout knowing vout vc ESRic

33 23 v vout can be witten as: 1 i dt C c c. I L vout ( cos t t ) ESRI L( sint 1) V0 C As it mentioned ealie to find the voltage ipple the points that deivative of output voltage is equal to zeo needs to be calculated. The output voltage deivative is: dv dt out I L ( sint 1) ESR. I L. cost (3-8) C 2 2 To simplify the equations E is defined as: E C. ESR. (3-9) dv out Solving 0, points a and b ae detemined. dt a E E cos 1 ( 2 ) ( E 1), (3-10) b E E cos 1 ( 2 ) ( E 1) (3-11) Knowing points a and b, Δvipple can be witten as: E 1. E E 1. E E 1 IT L s 1 1 vipple [ cos ( ) cos ( ) C ( E 1) ( E 1) ( E 1) (3-12) E E.(1 ) E E 1 E E.(1 ) E E E. ] 2 2 ( E 1)

34 24 Since in the expeimental setup the ESR is negligible compae to the capacito size, to find the appoximate elation between voltage ipple and capacito chage fom the above equation, ESR is assumed to be zeo. The complete deivations ae given in appendix C. Though gaphical analysis of the wavefoms an appoximate elation between the lost chage and the new load cuent value can be found as: T s Q I 9.5 L (3-13) so, Ts v ipple L 9.5C I. (3-14) out Replacing (3-4) and (3-14) in (3-1) and (3-3), the pulse width vaiation fo light to heavy and the new pulse width fo heavy to light load tansient based on voltage deviation afte tansient and voltage ipple ae calculated: LC T v Kf v (3-15) m out LH out, t s out, t TsnVg T HL T V 4 9.5V s out, t (1 1/ (1 )) ipple (3-16) Which K is a constant that depends on convete paametes, and will be detemined though an auto tuning pocess. It can be seen fom (3-15) that, in ode to calculate ΔTHL (change of switching peiod) afte finding the value of K, only a simple multiplication needs to be pefomed. As it is shown in Figue 3-4 the tem x Y=1 1/ (1 ) (3-17) 9.5

35 25 i Lm i L v out a Δv ipple b i Cout -I L Q Time (s) Figue 3-3: Magnetizing and tank cuent, output capacito voltage, and output capacito cuent wavefoms fom simulation in equation (3-16), whee x is Δvout,t/Δvipple, can be appoximated by sampling the cuve and intepolating linealy between the points. At the exteme point, afte a tansient, PID compensato is enabled and takes ove the task of the output voltage egulation. Since the switching fequency in the new steady state, and theefoe the output of the PID, will be significantly diffeent fom those befoe the tansient, einitialization of the PID is necessay. As it will be shown in Chapte 5, without e-initialization the PID would estat fom a wong output value and cause sub-tansients negatively affecting stability of the system. To e-initialize the PID it has been ecognized hee that the ipple value at the exteme point, i.e. at the peak o valley is equal to that of the new steady state, as illustated in Figue 3-2. This fact is utilized hee. At the exteme point the output voltage ipple vipple is measued and fom the self-populating look up tables (LUT) the new initial value fo the PID is detemined. The LUT then is self-populated based on the output voltage ipple once voltage eaches the steady state vipple,ss. Additional details on the opeation of this block ae given in the following subsection.

36 26 Figue 3-4: Compaison between function Y of equation (3-17) and its appoximated piecewise linea intepolation.

37 Pactical Implementation The hadwae implementation of the contolle is shown in Figue 3-5 and the contol algoithm is descibed with the flowchat of Figue 3-6. As shown in Figue 3-5, in ode to poduce the gating signals, the contolle uses a voltage-contolled oscillato (VCO), which depending on the opeating conditions, eceives the contol vaiable, fs[n], eithe fom the PID compensato o the tansient suppession block. Duing nomal opeation, the PID contolle is enabled and the analog-to-digital convete (ADC) samples the output voltage once pe switching cycle. Afte a tansient is detected by the tansient detection block, the ADC stats ovesampling. Based on the polaity of the voltage deviation the contolle detemines whethe the tansient is heavy to light o light to heavy and selects the fequency sequence calculation potocol accodingly. G 1 T n:1:1 L v g G 2 Lm Cout Rload +12 V + v out C - H 1 v out(t) Digital Contolle G 1 (t),g 2 (t) VCO f s[n] f ss[n] f t[n] PID contolle Initial Value e v[n] _ + H 1 v out (t) H 1v out[n] ADC TR f snew[n] VP V ef f s[n-1] TR Tansient Suppession LUT Update SS Ripple TR L/H Vd Tansient Detection Voltage Deviation Measuement f t[n] + + Δf[n] L/H K Δf HL LUT Vd TR Ripple TR SS f s[n] SS VP Ripple Steady State Detection Valley Point Detection Ripple Measuement Figue 3-5: LLC esonant convete block diagam with detailed contolle blocks.

38 28 In the case of a light to heavy tansient, ΔTLH is detemined fom (3-15) and the value K is detemined though an auto-tuning pocess. The contolle flowchat fo tuning K is shown in Figue 3-7. The change of switching peiod ΔTLH is calculated and the new switching peiod is applied in the fist switching cycle. If in the next switching cycle tansient suppession block is still active, it means the voltage has not eached its exteme point and the counte is incease by one. This means the initial value of ΔTLH was not sufficient fo the system to get to the new state within one cycle. Theefoe the value of K needs to be updated fo the next occuence of the tansient that does not need to be of the same value. initiate Enable PID Contolle No tansient Yes Disable PID Contolle Stat Ove Sampling Heavy to light Valley Point Yes Measue Ripple No Δf Update No Steady State Yes Stat Ove Sampling No Find Δf L2H yes Find Δf H2L f s (t)= Δf + f s (t-1) Reinitialize PID Fom LUT Enable PID contolle Stop Ovesampling Measue Ripple Get f s Stop Ove Sampling Update LUT Figue 3-6: Contolle flowchat

39 29 Stat Tansient Yes Cnt=Cnt+1 No No Valley point Yes Cnt >= 2 No Yes Keep K Incease K Figue 3-7: Auto-tuning flowchat of facto K In the case of a heavy to light load tansient, the value of ΔTHL is detemined utilizing a LUT. Tansient suppession logic emains active until the voltage eaches its valley point. At this point the ADC stops ove sampling and the PID is estated with the new initial fequency. As mentioned befoe, the PID uses the initial value fom a lookup table upon stating. At the time in which system gets to steady state opeation, and emains in steady state fo at least 10 cycles, the value of output voltage is used to update the LUT enties Simulation Results The simulation esult of Figue 3-8 and Figue 3-9 show the tansient esponse of the system with a well-tuned PID compensato and the intoduced contolle espectively. The simulation esults show that the system eaches the new steady state with the intoduced contolle in few switching cycles and, also that the voltage deviation is impoved compaed to the PID contolle.

40 Vout G1 0 iload Time (s) Figue 3-8: Simulation esults fo a light to heavy load tansient with a well-tuned PID compensato Vout G1 iload Time (s) Figue 3-9: Simulation esults fo a light to heavy load tansient with the intoduced contolle.

41 31 Chapte 4 4. Digital Synchonous Rectification Contolle In this chapte a obust, hadwae efficient, mixed-signal in addition to the peviously pesented contol loop is intoduced. It govens the switching actions of the seconday-side synchonous ectifie (SR) switches of LLC esonant convetes. The new SR timing contolle method minimizes switching and conduction losses of the SR switches though online optimization of thei on-off timing, using an auto-tuning pocess that takes into account the effect of paasitic elements, mainly leakage inductances. In this contolle, body diode conduction detection cicuits acoss the SR switches, and infomation about switching fequency available fom digital contolle ae utilized by a digitally implemented auto-tuning algoithm to detemine optimal switching times and achieve zeo cuent switching. In compaison with the existing SR contolles, the intoduced solution has a moe pecise diving scheme. Moeove, the contolle equies simple hadwae implementation Intoduction Fo impoving efficiency of LLC the diode ectifie can be eplaced with a synchonous ectifie (SR). Howeve, a majo difficulty in LLC convetes is detemination of the SR gate diving scheme, which needs to be adjusted fo diffeent opeating conditions. Figue 4-1 shows an LLC esonant convete with SR on the seconday side. In pevious publications [19-26], a numbe of SR diving schemes has been poposed. The analog solutions ae mostly based on the SR cuent sensing, to geneate SR diving signal by use of cuent tansfomes, which educes the efficiency due to exta tansfome winding esistance. Digital solutions utilizing computational powe, athe than diect sensing, have also been poposed [24], [26]. Among the most effective digital solutions is [24], in which the SR is tuned on synchonously with the main switches and the tun off pocess is auto tuned. Howeve, as

42 32 demonstated in [27], fo a ealistic convete, the optimal SR tun on time instant vaies with espect the main switch tun on time, depending on the opeating conditions. The auto-tuned tun off time adjustment intoduced in [24] is pecise, impoving obustness and educing susceptibility to the noise associated with the body diode conduction detection cicuits. Howeve, the poposed tun-off pocess is time consuming. C 1 G 1 T n:1:1 G SR2 L V g G 2 Lm Cout Rload C G SR1 SR body diode conduction detection cicuit G 1 (t),g 2 (t) G SR1 (t),g SR2 (t) VCO SR contolle fss[n] Digital Contolle Compensato ev[n] _ + V ef H 1 V out (t) H1Vout[n] ADC Figue 4-1: LLC esonant convete with SR on the seconday side and digital contolle To minimize losses associated with seconday side switches, a new hadwae-efficient contol method fo diving the SR switches is intoduced have the contolle shown in Figue 4-1 is independent of the convete s opeating condition. The new SR contolle utilizes the eadily available switching fequency infomation fom the digital contol loop and body diodes detection cicuits. A simple digitally implemented algoithm adjusts both tun-on and tun-off timing instants, though an auto-tuning pocess LLC Resonant Opeation To show the impotance of vaiable tun-on time of the SR switches with espect to tun on timing of the pimay switches, LLC wavefoms in the pesence of paasticics ae analyzed in

43 33 the following subsection. The desied SR gate diving signals fo the LLC esonant convete ae eviewed fo two modes of opeation, fo opeation below and above the esonance, while taking into account the tansfome leakage inductance and paasitic capacitance. The analysis pesented in [27] and simulation esults of the following figues show that in ode to achieve ZCS duing opeation below esonance, the SR must be tuned on befoe tuning on the pimay side switch. On the othe side, when opeating above the esonance [27] the SR switch should be tuned on afte the pimay side switch commutation. In ode to achieve ZCS fo the seconday side, the SR gating signals should be applied fo the same time duation that the SR body diodes ae conducting. Theefoe, in ode to find out the desied SR signals, an LLC esonant convete with a diode ectifie is simulated. Aftewads, the diode ectifie is eplaced by a synchonous ectifie and the effect of diving the SR synchonously with the pimay side is examined LLC Resonant Convete with Diode Rectifie Figue 4-2 shows the simulation esults fo the LLC convete while opeating below esonance and the coesponding equivalent cicuits ae shown in Figue 4-3. A half cycle, i.e. peiod fom t0 to t4, can be divided into fou subintevals. In the subinteval t0 to t1, as shown in Figue 4-3-a, the output capacito of the switch Q1 is being dischaged while the output capacitance of the switch Q2 is chaging. At the end of this subinteval the cuent though Q1 is still negative, so the next subinteval (t1 to t2) stats as shown in Figue 4-3-b and the body diode of Q1 stats conducting along with SR diode, DSR1. In ode to achieve ZVS fo the pimay side switches, the switch Q1 needs to be tuned on duing this subinteval. Figue 4-3-c shows the t2 to t3 subinteval in which Q1 and DSR1 ae on. This subinteval ends when the magnetizing inducto cuent (ilm) eaches the seies inducto cuent (il), and the SR cuent eaches zeo. Duing the fouth subinteval, t2 to t3 as shown in Figue 4-3-d both diodes on the seconday sides ae off and the magnetizing inducto makes a esonant cicuit with the esonance capacitance and inducto, C and L. This subinteval ends when the main switch tuns off. The second half cycle is simila to fist half cycle.

44 34 Figue 4-2: Simulation esults of LLC opeating below esonance; G 1 and G 2 ae main switches diving signal; i G1 and i G2 ae main switches cuents; i Lm and i L ae magnetizing and tank inducto cuents espectively; i DSR1 and i DSR2 ae ectifie body diode cuents. Q1 D1 C1 T n:1:1 DSR2 Ll1 Q1 D1 C1 T n:1:1 DSR2 Ll1 L L vg vg Q2 D2 C2 C Lm DSR1 Ll2 Cout Rload + vout - Q2 D2 C2 C Lm DSR1 Ll2 Cout Rload + vout - a) t 0 -t 1 b) t 1 -t 2 Q1 D1 C1 T n:1:1 DSR2 Ll1 Q1 D1 C1 T n:1:1 DSR2 Ll1 L L vg vg Q2 D2 C2 Lm + Q2 D2 C2 Lm + C DSR1 Ll2 Cout Rload vout - C DSR1 Ll2 Cout Rload vout - c) t 2 -t 3 d) t 3 -t 4 Figue 4-3: LLC esonant convete equivalent cicuits opeating below esonance. Similaly, Figue 4-4 shows the simulation esults fo the LLC convete while opeating above the esonant fequency. A half cycle can be divided into fou modes of opeation. The equivalent cicuits ae shown in Figue 4-5.

45 35 Figue 4-4: Simulation esults of LLC opeating above esonance; G 1 and G 2 ae main switches diving signal; I G1 and I G2 ae main switches cuents; I Lm and I L ae magnetizing and tank inducto cuents espectively; I DSR1 and I DSR2 ae ectifie body diode cuents. Q1 D1 C1 L T n:1:1 DSR2 Ll1 Q1 D1 C1 L T n:1:1 DSR2 Ll1 vg vg D2 C2 Q2 a) t 0 -t 1 C Lm DSR1 Ll2 Cout Rload + vout - D2 C2 Q2 b) t 1 -t 2 C Lm DSR1 Ll2 Cout Rload + vout - Q1 D1 C1 L T n:1:1 DSR2 Ll1 Q1 D1 C1 L T n:1:1 DSR2 Ll1 vg Vg Q2 c) t 2 -t 3 D2 C2 C Lm DSR1 Ll2 Cout Rload + Vout - Q2 d) t 3 -t 4 D2 C2 C Lm DSR1 Ll2 Cout Rload + Vout - Figue 4-5: LLC esonant convete equivalent cicuits opeating above esonance. As shown in the Figue 4-2, and Figue 4-4, the seconday side cuent stats gowing slightly befoe the tun-on of the main switches while convete is opeating below the esonant

46 36 fequency (fs<f0), and slightly afte that when convete is opeating above the esonant fequency (fs>f0). SR tun-on duation also depends on the convete s opeating condition. Theefoe, if the diode ectifie is eplaced with a SR, the SR tun-on and tun-off time instants have to be executed pecisely in ode to avoid ciculating enegy o body diode conduction loss LLC Resonant Convete with Synchonous Rectifie To examine the effect of inappopiate SR tun on, the simulation esults of a LLC esonant convete with a SR on the seconday side ae pesented hee. Figue 4-6-a shows simulation esults fo opeation below esonance and the tun on of the SR happens synchonously with the main switch. Duing the ΔTBR as shown in Figue 4-6-a, the body diode conducts while the SR switch tuns on afte this time. This delay in tun on inceases the conduction losses while it can be avoided by pope SR switching scheme. Figue 4-6: Simulation esults of LLC esonant convete with SR while SR synchonously tuns on with the main switch. a) Opeating above esonance. b) Opeating below esonance; G 1 and G 2 ae main switches diving signal; i DSR and G DSR1 ae the SR cuent and diving signals. Figue 4-6-b shows the same simulation esult while opeating above esonance. Again the SR tun on is in synch with the main switch. Simulation esults show a evese cuent though the SR in ΔTAR time. This evese cuent will cause ciculating enegy and decease the efficiency Pinciple of opeation and Pactical Implementation Hee a pactical and fast SR contol scheme that optimizes switching sequence timing is descibed. It takes into account all the timing equiements discussed in the pevious section. Fom the pevious discussion it can be seen that it is highly desiable to tun on the SR switch

47 37 ight befoe the diode would be stating its conduction and to tun it off ight afte the diode would stop conducting. Figue 4-7 shows the contolle flowchat that explains how these two goals ae achieved, i.e. descibes the intoduced SR diving/contol scheme. At the moment the body diode conduction is sensed by the detection cicuit as shown in Figue 4-1, the SR tuns on and that time instant, with espect to the switching cycle, is captued in a egiste. In the next cycle, if the switching fequency emains the same, the contolle takes into account the egisteed value, and SR tuns on ΔTon time ealie than in the pevious cycle. Theefoe, except fo the fist cycle in each opeating point, all othe cycles stat without body diode conduction. This pocess is activated each time a change of fequency is detected and, if the fequency emains the same, the algoithm is estated evey 20 cycles, to pevent possible eos. A simila algoithm is used to find the SR tun-off time instant. Instantly tun off time is detemined based on the maximum allowable switching fequency (minimum time peiod Tm). When the SR tuns off the body diode stats conducting. The exta time that SR needs to emain in the on state is the time duation which the body diode conducts o the duation of the active pulse at the output of the body diode detection cicuit. This emaining time (ΔToff) is measued (by a counte and egiste) and added to the initial value of the tun on pulse width (Tm/2). In this way the tun off time instant is detemined as Toff=Tm/2+ΔToff. This algoithm estats evey time the switching fequency changes, so it guaantees fo all opeating fequency egions. The implementation of the fast two step SR contolle is shown in Figue 4-8. At t0 body diode conduction cicuit detects conduction. SR switch tuns on and the value of VCO_counte is egisteed with a Counte_ON vaiable at t1. At t2 the on time peiod eaches the maximum allowable time peiod and GSR tuns off. At this point the body diode stats conducting and Counte_off stats measuing the time until body diode stops conducting at t3. Duing the next cycle, when the VCO_Counte eaches Counte_ON-1 at t4, the GSR tuns on. At t5, GSR tuns off which is the time that VCO_counte eaches Counte_off+Tm/2. It should be noted that this method can potentially be extended fo othe dc-dc convetes with synchonous ectifie such as synchonous buck convete.

48 38 Figue 4-7: a) SR tun off contolle flowchat; b) SR tun on contolle flowchat Figue 4-8: Timing diagam, I SR is the SR cuent, V dssr is the SR switch dain to souce voltage, G SR is the SR gating signal.

49 39 Chapte 5 5. Expeimental Results To veify the pefomance of the intoduced contolle, a commecial development boad [17] with a half-bidge 340 W, 400 V to 12 V, LLC esonant convete is used and tested with the setup shown in Figue 5-1. The existing contolle is eplaced with a custom-made FPGA system. The contolle is based on the diagam of Figue 3-3, Figue 3-5, and Figue 4-1 and its pefomance is veified both though simulation and expeiment. To avoid any possible damage to the system, the PID compensato has been tuned though simulation. Figue 5-1: Expeimental setup

50 40 The intoduced contolle was tested and the expeimental esults wee compaed with a welltuned digital PID contolle to show the dynamic pefomance impovement. A light to heavy and heavy to light load tansients in both cases ae shown in Figue 5-2 and Figue 5-3, espectively. The esults show bump-less tansition between diffeent modes, confiming pope opeation of the auto-tuning algoithm and, significant impovement compaed to a well-tuned PID contolle. Figue 5-2 shows the tansient esponse fo a light to heavy load tansient fo a load step-up fom 3 A to 15 A. With tansient suppession contolle, the switching fequency is deceased to 64 khz fom 88 khz fo one cycle and goes to 83 khz when PID is e-activated. Figue 5-3 shows the tansient esponse fo a heavy to light load tansient fo a load step-down fom 15 A to3 A. When the tansient suppession contolle is employed, the fequency is inceased to 120 khz fom 83 khz. The esults show that the tansient suppession block is woking popely and changes the fequency afte the tansient until the voltage eaches the valley/peak. Then PID contols the system. Figue 5-2: Dynamic esponse of LLC esonant convete fo light to heavy load tansient. v out is the output voltage measuement signal (200mV/div). i Load is the load step cuent (10A/div); v sw_node is the switching node voltage.

51 41 Figue 5-3: Dynamic esponse of LLC esonant convete fo heavy to light load tansient. v out is the output voltage measuement signal (200mV/div); i Load is the load step cuent (10A/div); v sw_node is the switching node voltage. It can be seen fom the figues that, in both cases, the tansient ecovey pocess takes two switching cycles afte tansient and esults in the minimum voltage deviation. Fist half switching cycle is the tansient detection delay and the next half cycle is used to calculate value of the peiod. With the calculated peiod, i.e. fequency, the states vaiables each new states in one cycle, at this point PID contolle estats opeation with an initial value based on new load cuent. In ode to show the impotance of the PID e-initialization the system is contolled with the intoduced contolle while the PID e-initialization block was disabled. The expeiment esults then compaed with the expeimental esults fom the fully functional contolle. Figue 5-4-a, and b show the tansient esponse of the system fo a 3 A to 15 A load step with and without PID e-initialization espectively. The expeimental esults show that without PID e-initializing system goes though anothe tansient and with e-initializing system has faste esponse, as discussed peviously.

52 42 Figue 5-4: Tansient esponse of a 3 to 15A load step a) with PID e-initialization, b) without PID einitialization. v out is the output voltage measuement signal (100mV/div). i Load is the load step cuent (5A/div); v sw_node is the switching signal. To find the minimum allowable output capacito, the tansient esponse of the intoduced contolle is compaed to the tansient esponse of a conventionally designed PID contolle as a efeence. In the conventional system the output capacito is 2585 µf while the output capacito in the system with the intoduced contolle is 1645 µf. The conventional PID contolle bandwidth is about 1/10 th of the switching fequency at the optimal load. Figue 5-5-a shows the tansient esponse of the intoduced contolle fo a light to heavy load tansient fo a load step-up fom 3 A to 21 A while Figue 5-5-b shows the esults of the same expeiment with the conventional contolle. The esults confim supeio pefomance of the intoduced contolle, nea minimum possible output voltage deviation. The esults also show that the intoduced contolle can achieve 40% smalle output voltage deviation compaed to the conventional contolle while utilizing 60% of the output capacito size. This allows fo moe capacito eduction. The intoduced contolle can potentially allow fo utilization of 40% output capacito size to achieve simila output voltage deviation.

53 43 Figue 5-5: Dynamic esponse of LLC esonant convete fo light to heavy load tansient a) with intoduced contolle and C out=1645 µf, b) with conventional contolle and C out=2585 µf. v out is the output voltage measuement signal (200mV/div). i Load is the load step cuent (10A/div); v sw_node is the gating signal; Time scale is 50us/div. Figue 5-6 shows a epetitive load tansient demonstating the auto-tuning pocess of facto K, descibed by Equation (3-7). K is applied to find the pope fequency afte a light to heavy load tansient. Afte each light to heavy load tansient if the state vaiables of the system ae not at thei new states within one switching cycle afte detecting the tansient, K is inceased one step. The steps can be optimized based on the total numbe of tansients until K eaches its final value. In this setup total numbe of eight tansients takes until K gets to its final value. The zoomed in vesion of Figue 5-6 at the updating points of K ae shown in Figue 5-7. It can be seen fom the figues that K is inceased each time that the numbe of cycles duing the tansient suppession block activation is moe than two.

54 44 Figue 5-6: Auto-tune of facto K fo light to heavy load tansients. v out is the output voltage measuement signal (200mV/div). i Load is the load step cuent (10A/div); G 1 is the gating signal and facto K is shown in 5 bits; Time scale is 100 ms/div. Figue 5-7: Zoomed in vesion of Figue 5-6 at updating times

55 45 To veify the analysis pesented in section 4.2 the SR switches ae deived in synchonous with the pimay side switches and the esults ae compaed with the modified SR deiving scheme. Figue 5-8-a shows the expeimental esult while the SR tuns on synchonously with the pimay switch. As it can be seen fom the expeimental esult body diode stat conducting fo some time in the beginning of the cycle. Figue 5-8-b is the same esults with modified on time. The esults show that with a pope on and off time the body diode conduction could be avoided. Figue 5-8: Expeimental esults, a) SR diving signals in synchonous with the pimay side switches; b) SR diving signals with modified on time. SR DET1 is the Q SR1 body diode conduction detection signal; G SR1 is the Q SR1 gating signal; v DSSR1 is the Q SR1 dain to souce voltage 20 V/div.; v x pimay side witching node voltage. Time is 2 us/div. These tansient esults show that the intoduced contolle is a suitable contol technique fo LLC esonant convetes. It achieves minimal output voltage deviation duing light-to-heavy and heavy-to-light load tansients. The esults show that the intoduced contolle can achieve bette output voltage deviation than the conventional contolle, allowing fo output capacito volume eduction.

56 46 Chapte 6 6. Conclusions and Futue Wok To impove the dynamic pefomance of the LLC esonant convete a pactical auto-tuning digital contolle that esults in vitually smallest possible output voltage deviation duing tansients is pesented. Also an addition contolle fo egulating opeation of the SR is intoduced. The contolle achieves fast tansient esponse and seamless tansition between steady-state and tansient modes of opeation by collecting infomation about the output voltage only. This eliminates the need fo costly cuent sensos and complex calculations existing in othe fast tansient esponse solutions. The two fequency steps ae detemined though measuements of the initial voltage deviation afte the tansient and the output voltage ipple at the consecutive exteme output voltage deviation point. The values of those steps ae dynamically adjusted though self-tuning pocesses. The effectiveness of the contolle is demonstated with expeimental pototypes showing smooth tansitions between the contolle states and confiming pactically minimum output voltage deviation allowing fo a dastic eduction of the output capacitance value. Expeimental esults show up to 60% eduction in the output capacitance. The fast auto-tuned digital contolle block fo optimization of the synchonous ectifies conduction times eliminates the body diode conduction and avoids the evese SR cuent. Moeove, the contolle pevents evese cuent build up. Theefoe, it limits the ciculating enegy and impoves the efficiency. The diving scheme consists of two fast auto tuned pocess fo tun-on and tun-off, which can tune the SR diving signal in one cycle. The advantages of this method ove othe existing methods ae its pecise diving signals and fast auto tuning,

57 47 which esult in lowe powe losses. The method could potentially be used in othe dc-dc synchonous ectifie such as synchonous buck convete Futue wok The intoduced contolle in this thesis impoves the dynamic pefomance of the system as well as the oveall efficiency. Howeve, thee ae still some woks can be done. 1. One of the impotant featue of LLC esonant convete is its ability to opeate ove a wide input voltage ange. The effect of intoduced contolle to impove input voltage vaiation can also be analyzed. The tajectoy analysis in this case would be moe challenging due to vaiation of input and output voltages along with inducto cuent and capacito voltage. 2. An input voltage feedfowad also can be used to detemine moe accuate ΔTLH afte a light to heavy load tansient. Facto K of Equation (3-7) can be modified as: C (6-1) m out K L Tsn 3. The heavy to light load tansients algoithm also can be implemented as an auto-tuned pocess so the contolle could be genealized and extended to othe convetes. Based on the state tajectoy analysis, the optimal fequency o duty atio change needs to be fomulized fo diffeent convetes.

58 48 Refeences [1] Bo, Yang, and F.C. Lee, "LLC esonant convete fo font end DC/DC convesion," in Seventeenth Annual IEEE Applied Powe Electonics Confeence and Exposition, APEC 2002, vol.2: pp [2] B.Yang and F.C. Lee, Small-signal analysis fo LLC esonant convete, in Poc. Cente Powe Electon. Syst. Semin., 2003, pp [3] R. D. Middlebook and S. Cuk, A geneal unified appoach to modeling switchingconvete powe stages, in Poc. IEEE Powe Electon. Spec. Conf., 1976, pp [4] Mattavelli, P.; Rossetto, L.; Spiazzi, G.; Tenti, P., "Geneal-pupose fuzzy contolle fo DC/DC convetes," Applied Powe Electonics Confeence and Exposition, APEC '95. Confeence Poceedings 1995., Tenth Annual, vol., no.0, pp.723,730 vol.2, 5-9 Ma [5] Hao Ma; Qinwei Liu; Jin Guo, "A sliding-mode contol scheme fo llc esonant DC/DC convete with fast tansient esponse," IECON th Annual Confeence on IEEE Industial Electonics Society, vol., no., pp.162,167, Oct [6] Weiyi Feng; Lee, F.C.; Mattavelli, P., "Simplified Optimal Tajectoy Contol (SOTC) fo LLC Resonant Convetes," Powe Electonics, IEEE Tansactions on, vol.28, no.5, pp.2415,2426, May [7] Chao Fei, Weiyi Feng, Fed C. Lee, Qiang Li., "State-tajectoy Contol of LLC Convete Implemented by Micocontolle, In Poc. IEEE APEC 2014, Mach [8] Buccella, C.; Cecati, C.; Latafat, H.; Razi, K., "Compaative tansient esponse analysis of LLC esonant convete contolled by adaptive PID and fuzzy logic contolles," IECON th Annual Confeence on IEEE Industial Electonics Society, vol., no., pp.4729,4734, Oct [9] Kuokawa, F.; Muata, K., "A new fast digital P-I-D contol LLC esonant convete," Electical Machines and Systems (ICEMS), 2011 Intenational Confeence on, vol., no., pp.1,5, Aug [10] W. A. Tabisz, M. M. Jovanovic, and F. C. Lee, "Pesent and futue of distibuted powe systems," in Applied Powe Electonics Confeence and Exposition, APEC '92. Confeence Poceedings 1992., Seventh Annual, 1992, pp [11] R. W. Eickson and D. Maksimovic, Fundamentals of Powe Electonics. New Yok: Spinge-Velag, 2001.

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61 51 Appendices A Optimal Tajectoy Analysis fo Load Tansients In this pat, the tajectoy analysis fo LLC esonant convete in 2D state-plane is pesented. LLC esonant convete is a multi-element esonant convete [6]. In ode to analyze the tajectoy in 2D state-plane fist the convete needs to be analyzed and simplified based on diffeent modes of opeation, so the esonant elements can be educed to two elements [6]. Aftewads, the steady-state and dynamic tajectoies ae illustated in ode to calculate the optimal tajectoy loci fo state vaiable to tack afte tansient. A.1 LLC esonant steady state tajectoy in 2D The LLC esonant convete can be divided to six modes of opeation based on the state of the pimay switches and seconday diodes [6]. In the fist thee modes Q1 is conducting and in the est Q2 is conducting. To simplify the analysis the output voltage is assumed to be constant. In mode I, II, IV, and V the magnetizing inducto Lm, is clamped with the output voltage eflection fom the seconday side. Theefoe the magnetizing inducto can be eliminated fom the state vaiable equations [6]. In mode III and VI the magnetizing cuent paticipates in the esonance and make a esonant cicuit in seies with the tank inducto L and tank capacito C, so the magnetizing cuent is same as inducto cuent. Theefoe in these cases the magnetizing inducto can be eliminated fom the state vaiable equations as well. Although the LLC esonant convete is a multi-element esonant convete, it can be epesented with two esonant element. The following figues show the LLC esonant convete in each mode of opeation, and thei equivalent cicuit and tajectoy in the coesponding mode. In the tables below each figue ae the state vaiable diffeential equations deivatives and the tajectoy equation.

62 52 Mode I V g G 1 L T n:1:1 D SR2 V g L Lm nv out il (1-nVoutN, 0) G 2 C Lm D SR1 Cout Rload + Vout - C VC Figue A-1: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode I Table 1: Mode I State Vaiables di L dt 1 dvc ( Vg nvout vc ) L dt 1 i C L Chaacteistic impedance Resonant fequency Z L 0 0 C 1 LC Diffeentiate equations Nomalized equations i L V ( V nv ) I.cos[ (t t )].sin[ (t t )] C 0 g out L Z0 v ( V nv ) I. Z.sin[ (t t )] [V (V nv )].cos[ (t t )] C g out L C 0 g out 0 0 i I.cos[ (t t )] [ V (1 nv )].sin[ (t t )] L N L 0N 0 0 C 0N outn 0 0 v (1 nv ) I.sin[ (t t )] [V (1 nv )].cos[ (t t )] CN outn L0N 0 0 C 0N outn 0 0 State space tajectoy equation [ v (1 nv )] i ( I ) [V (1 nv )] C N outn L N L 0N C 0N outn

63 53 Mode II G 1 L T n:1:1 D SR2 L (1+nVoutN, 0) V g V g Lm nv out il G 2 C Lm D SR1 Cout Rload + Vout - C VC Figue A-2: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode II Table 2: Mode II State Vaiables di L dt 1 dvc ( Vg nvout vc ) L dt 1 i C L Chaacteistic impedance Z0 L C Resonant fequency 0 1 LC Diffeentiate equations Nomalized equations State space tajectoy equation i L V ( V nv ) I.cos[ (t t )].sin[ (t t )] C 0 g out L Z0 v ( V nv ) I. Z.sin[ (t t )] [V (V nv )].cos[ (t t )] C g out L C 0 g out 0 0 i I.cos[ (t t )] V (1 nv ).sin[ (t t )] L N L 0N 0 0 C 0N outn 0 0 v (1 nv ) I.sin[ (t t )] [V (1 nv )].cos[ (t t )] CN outn L0N 0 0 C 0N outn 0 0 [ v (1 nv )] i ( I ) [V (1 nv )] C N outn L N L 0N C 0N outn

64 54 Mode III L V g G 1 L T n:1:1 D SR2 V g Lm il (1, 0) G 2 C Lm D SR1 Cout Rload + Vout - C VC Figue A-3: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode III Table 3: Mode III State Vaiables dil 1 dt L L m ( V v ) g C dv C dt 1 i C L Chaacteistic impedance Z1 L C L m Resonant fequency 1 1 ( L L ) C m Diffeentiate equations Nomalized equations State space tajectoy equation i L V V I.cos[ (t t )].sin[ (t t )] C 0 g L Z1 v V I. Z.sin[ (t t )] ( V V ).cos[ (t t )] C g L C 0 g 1 0 il N IL 0N.cos[ 1(t t 0)] ( VC 0 1).sin[ 1(t t 0)] N Z Z Z Z v I 1.sin[ (t t )] ( 1).cos[ (t t )] L 0N CN 1 0 VC 0N 1 0 Z0 Z1 i I ( v 1) ( ) ( ) (V 1) C N 2 LN 2 L0 N 2 2 C0 N Z0 Z1 Z0 Z1

65 55 Mode IV G 1 L T n:1:1 D SR2 L (nvoutn, 0) V g Lm nv out il G 2 Lm + C D SR1 Cout Rload Vout - C VC Figue A-4: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode IV Table 4: mode IV State Vaiables di L dt 1 dvc ( vc nv out ) L dt 1 i C L Chaacteistic impedance Z0 L C Resonant fequency 0 1 LC Diffeentiate equations i L V nv I.cos[ (t t )].sin[ (t t )] C 0 out L Z0 v nv I. Z.sin[ (t t )] (V nv ).cos[ (t t )] C out L C 0 out 0 0 Nomalized equations v nv I.sin[ (t t )] (V nv ).cos[ (t t )] CN outn L0N 0 0 C 0N outn 0 0 i I.cos[ (t t )] ( V nv ).sin[ (t t )] L N L 0N 0 0 C 0N outn 0 0 State space tajectoy equation ( v nv ) i ( I ) (V nv ) C N outn L N L 0N C 0N outn

66 56 Mode V G 1 L T n:1:1 D SR2 L (-nvoutn, 0) V g Lm nv out il G 2 C Lm D SR1 Cout Rload + Vout - C VC Figue A-5: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode V Table 5: Mode V State Vaiables di L dt 1 dvc ( nvout vc ) L dt 1 i C L Chaacteistic impedance Z0 L C Resonant fequency 0 1 LC Diffeentiate equations i L V nv I.cos[ (t t )].sin[ (t t )] C 0 out L Z0 v nv I. Z.sin[ (t t )] (V nv ).cos[ (t t )] C out L C 0 out 0 0 Nomalized equations i I.cos[ (t t )] ( V nv ).sin[ (t t )] L N L 0N 0 0 C 0N outn 0 0 v nv I.sin[ (t t )] (V nv ).cos[ (t t )] CN outn L0N 0 0 C 0N outn 0 0 State space tajectoy equation ( v nv ) i ( I ) (V nv ) C N outn L N L 0N C 0N outn

67 57 Mode VI V g G 1 L T n:1:1 D SR2 L Lm il (0, 0) G 2 C Lm D SR1 Cout Rload + Vout - C VC Figue A-6: LLC esonant convete equivalent cicuit and its state space tajectoy in Mode VI Table 6: Mode VI State Vaiables dil 1. v dt L L m C dv C dt 1 i C L Chaacteistic impedance Z1 L C L m Resonant fequency 1 1 ( L L ) C m Diffeentiate equations i L V I.cos[ (t t )].sin[ (t t )] C 0 L Z1 v I. Z.sin[ (t t )] V.cos[ (t t )] C L C Nomalized equations State space tajectoy equation il N IL 0N.cos[ 1(t t 0)] VC 0.sin[ 1(t t 0)] N Z0 Z1 Z0 Z1 IL 0N vc.sin[ 1(t t 0)] 0.cos[ 1(t t 0)] N VC N Z Z v 0 1 i 2 LN 2 L0 N 2 2 C ( ) ( ) V N C0 N Z0 Z1 Z0 Z1 I

68 58 A.2 LLC Load Tansient Tajectoies in State-Plane In this pat the state-plane analysis duing load tansient is illustated using the state tajectoies studied in the pevious section. In ode to ecove fom the tansient in the minimum possible time and avoid oveshoot, the incement and decement time peiod of the switching fequency is calculated using the gaphic state-plane analysis [6]. A.2.1 Light to Heavy Load Tansient The LLC esonant convete usually opeates close to the esonant fequency to achieve the highest efficiency, theefoe the tajectoies ae cicles and the adius depends on the load cuent. Fo a light load, ILL to heavy load IHL tansient the state vaiables move fom one cicle with a smalle adius to a cicle with a bigge adius. In ode to avoid unbalance cuent in the magnetizing inducto this tansition needs to take place in two steps. As shown in Figue A-7 and Figue A-8 the state vaiables ae located on the inne cicle in the beginning at t1 they move to the middle cicle moving on the ellipse of mode III. Fom t2 to t3 state vaiables ae on the middle cicle and at t3 they move to the oute cicle though the ellipse of mode VI. At time t4 all state vaiables (il, VC and ilm) ae settled [6]. Heavy Load V C t 4 t 3 t 0 t 1 t 2 Light Load i L Figue A-7: State tajectoy duing load step up

69 59 I Load t G1 t G2 t I L ILm t t 0 t 1 t 2 t 3 t 4 Figue A-8: LLC esonant convete wavefoms duing load step up Now that we know the desied path on the tajectoy, the objective is to calculate the time incement (t2-t1) on the pulse width. Fom [30] the RMS esonant inducto cuent, IRMS nea the esonant fequency is : I RMS 1 V n R T 1 n V T i. 4 4 ( ) (6-2) 4 2 nr L 4 2 L n out L 2 out 2 Load L m m The adius of the tajectoy cicles pesented in the pevious pat ae the nomalized peak cuent. Theefoe (A-2) shows the elation between the IRMS and the adius of the tajectoy cicle. 2I RMS V / Z (6-3) g 0 Initially the convete is opeating in mode I and mode IV, so the magnetizing inducto is clamped with the eflection of the output voltage fom the seconday side. Theefoe the magnetizing inducto cuent ilm can be calculated based on the output voltage [6]. At t1 the conveto entes mode III and ilm and esonant inducto il ae in seies in this mode. So the value of the il can be witten as:

70 60 nv T i t il t (6-4) out L ( 1) m( 1). Lm 4 The nomalized fom is: nvout T 1 il ( 1) ( 1).. N t ilmn t (6-5) L 4 V / Z m g 0 While convete is opeating in the esonance the state tajectoy is a cicle centeed at (0.5, 0) and the value of the vcn is as follows: 2 2 iload 1 vc ( 1) ( 1) N t il N t (6-6) 2 n V / Z g 0 Load cuent at t1 is the light load, ILL so: v CN ILL 1 ( t1) (6-7) 2 n V / Z g 0 Similaly vc at t4 can be calculated: v CN IHL 1 ( t4) (6-8) 2 n V / Z g 0 The nomalized value of vc at t2 can be estimated by: v v ( t ) (1 v ( t )) ( I I ) / 2 1 (6-9) CN 1 CN 4 LL HL CN ( t2) n Vg / Z0 Since the magnetizing inducto is lage, fom t1 to t2, il and ilm is consideed to be constant. nvout T Vg T I il ( t1) ilm( t1).. L 4 L 8 m m The esonant capacito is chaging duing this time (t1 to t2) so the time diffeence can be pesented as:

71 61 C.( v ( t ) v ( t )).V L.( I I ) / n C N 2 C N 1 g m HL LL TINC t2 t1 (6-11) I Vg A.2.2 Heavy Light to Load Tansient Fo heavy to light load tansient the pulse width needs to get smalle, theefoe the time decement needs to be calculated. Initially convete is opeating in mode I and IV at t1 convete goes though mode V to middle cicle. At t3 convete entes mode II until t4. At this point state vaiables each thei final values [6]. V C Heavy Load t 1 t 2 t 0 t 4 t 3 Light Load i L Figue A-9: State tajectoy duing load step down The nomalized esonant capacito voltage at t0 and t4 ae: V CN IHL 1 ( t0) (6-12) 2 n V / Z g 0 V CN ILL 1 ( t4) (6-13) 2 n V / Z g 0

72 62 I Load t G1 G2 t t I L ILm t t 0 t 1 t 2 t3 t 4 Figue A-10: LLC esonant convete wavefoms duing load step down All the modes duing heavy to light load tansient ae cicles so the magnetizing inducto Lm is always clamped by the output voltage nvout. Since the cicles of modes V and II ae much lage, the line fom t1 to t2 and t3 to t4 assumed to be staight. Theefoe vcn(t1)= vcn(t2) and vcn(t3)= vcn(t4). The equations fo inducto cuent and capacito voltage ae as follow: vcn ( t2) vcn ( t3) ilmn ( t2) 0.5 v ( t ) v ( t ) 0.5 i ( t ) CN 0 CN 1 LmN 0 (6-14) IHL. ILL 1 vcn ( t2) (0.5 vcn ( t0)).(0.5 vcn ( t3)) (6-15) 2 n V Z g 0 nvout T 1 iln ( t0) ilmn ( t0).. (6-16) L 4 V Z m g 0 i t i t v ( t ) 0.5 nv T 1 I CN 2 out LL LmN ( 2) LmN ( 0) vcn ( t0) Lm 4 Vg Z0 I HL (6-17) Using above equations the time duation fom t0 to t2 can be obtained:

73 63 L.( i ( t ) i ( t )).V Z I T m LmN 2 LmN 0 g 0 LL 2 0 (1 ). (6-18) nvout IHL 4 T t t The deceases pulse width can be estimated by: T I LL T TDEC T (1 ). (6-19) 2 I 4 HL

74 64 B Implementation of Functional Blocks In this chapte the detailed implementation of some of the impotant blocks in the contolle is explained. Figue B-1 shows the functional blocks used in the contolle. B.1 VCO Block Figue B-1: Functional blocks used in the intoduced contolle Figue B-2 shows a conventional VCO block that updates the fequency afte each cycle. Since the intoduced contolle changes the switching fequency afte tansient, in some cases the conventional VCO is unable to popely dive the switches. Figue B-3 shows the expeimental esults with a conventional VCO in which the diving signal is faulty. In ode to avoid this poblem a univesal VCO is designed as it is shown in Figue B-4.

75 65 T D Q T eg 12-Bit Counte Cnt Dead time Digital Compaato G1 R T T eg /2 Digital Compaato T eg /2 + Dead time Digital Compaato G2 T eg Digital Compaato Figue B-2: Conventional VCO implementation Figue B-3: Expeimental esult using conventional VCO Univesal VCO uses a counte that eset evey half cycle. Duing nomal opeation in which PID is contolling the system VCO changes the fequency only afte end of each cycle. Although it enables the nonlinea contolle to change the fequency at the time that tansient happens to make the system faste. Figue B-5shows the expeimental esult with the univesal VCO. The compaison between the diving signals of conventional and univesal VCO is shown in Figue B-6.

76 66 Figue B-4: Univesal VCO implementation Figue B-5: expeimental esult using the univesal VCO Figue B-6: Diving signal compaison using conventional and univesal VCO B.2 Voltage Deviation, H2L and L2H Detection In ode to find the voltage deviation afte tansient, the defeence between value of output voltage at tansient and half cycle afte tansient is measued as shown in Figue B-7. Based on the sign of the voltage dop the type of tansient (H2L o L2H) is detected.

77 67 Figue B-7: Voltage Dop, H2L and L2H Detection B.3 Ripple measuement and PID Re-Initialization Duing ove sampling, once at steady state fo 20 cycles and once afte tansient, the defeence between maximum and minimum of the output voltage in each cycle is measued as shown in Figue B-8. The output of ipple measuement block duing tansient is used to detemine the initial value of the PID at valley point. Its output duing steady state is used to update the fequency in PID look up table (LUT). V[n] Reset Vmin [n] MUX Vmin_Reg Reg. Vmin [n] Clk Dig. Comp. ADC V[n] Vmax [n] Clk MUX Vmax_Reg Reset Reg. Vmax [n] + Reg. Posedge-Sync Vipple[n] Dig. Comp. If In<A1 If In<A2 If In<A3 Else PID Initial Value LUT Dig. Comp. Clk Clk Clk Ripple Measuement Figue B-8: Ripple measuement and PID Re-Initialization