Analysis and Implementation of LLC Burst Mode for Light Load Efficiency Improvement

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1 Analysis and Implementation of LLC Bust Mode fo Light Load Efficiency Impovement Bin Wang, Xiaoni Xin, Stone Wu, Hongyang Wu, Jianping Ying Delta Powe Electonics Cente 238 Minxia Road, Caolu Industy Zone, Pudong, Shanghai, 2129, China Tel: , Fax: , Abstact Bust mode contol is applied to impove light load efficiency of LLC convete in this pape. Detailed analysis on chaacteistic and opeation pocesses of LLC bust mode contol with SR is pesented. Based on the analysis, some impotant ules of LLC bust mode contol ae poposed, which is the key to achieve high light load efficiency. The ules include: the suitable pimay and seconday diving timing, design guild line of output filte, easonable contol stategy etc. To veify the analysis, a pototype with 12V/1A output has been built. Thanks to the poposed contol stategy and optimum design, light load efficiency of LLC convete can be impoved significantly, such as efficiency at 1% load can be impoved fom 92.5% to 94.8%. I. VQ1,VQ4 VQ2,VQ3 VQ5 VQ6 il A ilm A Figue 2. Key wavefom of LLC convete at light load INTRODUCTION little fom zeo load to full load, and it can pevent fequency fom going too highe at light load. But it also esults in that magnetizing cuent ilm at light load is the same as heavy load, and output cuent flows evesely fom seconday to pimay in aea A at light load. That will cause lage switching loss; coe loss and conduction loss at light load. Table.1 shows LLC loss beakdown at 1 A load. The loss mainly includes switching loss, coe loss and conduction loss. The efficiency of powe stage is only 92.5%, and if dive loss and contol loss ae consideed, the convesion efficiency is only about 89.8%. The loss of lowe load is almost the same as that at 1A, so the efficiency will be much lowe at load lowe than 1A. Efficiency equiement of powe supply is going highe and highe ecently, and the efficiency demand is not only focused on heavy load but also on light load. And seveal companies and oganizations have pesented thei own equiements fo light load efficiency. a) LLC seies esonant convete with SR LLC seies esonant convete daws much attention nowadays because high efficiency can be achieved with pope SR contol methods. But its light load efficiency is not compaative with its high efficiency at heavy load. Fig.1 shows the cicuit diagam of full bidge LLC seies esonant convete. This topology can achieve ZVS tun on and low tun off cuent of Q1~Q4 and ZCS of Q5~Q6 fom zeo to full load ange [1], but this bings some constant loss because of its opeation pinciple. Fig.2 shows LLC convete key wavefoms at light load. Zeo-coss SR contol method [2] is applied. SR MOSFETs Q5, Q6 ae tuned on at the same time when coesponding pimay MOSFETs ae tuned on, and tuned off at zeo-coss point of synchonous cuent. This contol method esults in that switching fequency vaies a Q1 Q2 TABLE I Loss beakdown of LLC convete at 1% load Switching loss ilm Lm Q5 Q3 Q4 Vo il Figue 1. Cicuit diagam of LLC seies convete /9/$ IEEE 2.4W Conduction loss 2W Dive loss 2.7W Contol loss 1W Bust mode contol is widely applied to impove light load efficiency, usually in potable devices. This contol method blocks oiginal switching dive signals peiodically, and powe convesion only happens duing the time having dive signals, so it can educe dive loss and switching loss a lot [3]. But this method is used to educing loss at exteme light load in ode to consume less powe at standby mode [4]. If this contol Q6 L Coe loss b) Bust mode contol T ipo C 5.3W 58

2 method is applied fo light load efficiency impovement of high powe LLC convete with SR, seveal aspects need to be studied caefully. So, this pape focuses on the chaacteistic of bust opeation of LLC convete with SR, and detailed analysis on opeation pocesses and powe loss is pesented in the fist section. The design consideation of output filte is discussed in seconday section. Besides, this pape poposes a piecewise contol method to ensue that the highest efficiency can be achieved at diffeent load point. The expeiment esults of a 12W/12V pototype demonstate that efficiency can be impoved at load ange fom %-15% by optimum design. II. BURST OPERATION ANALYSIS Bust opeation pocesses ae shown in Fig.3, t to t3 is a whole bust opeation peiod T bust, and bust fequency f bust =1/T bust is defined. The whole peiod can be divided into thee stages. seconday diodes keep evese biased until Vt ising to N Vo + V ), if diode ectifying is applied. ( FD Figue 4. Equivalent woking cicuit in stage 1 Fig.4 shows the equivalent woking cicuit in this stage, and Vt(t), i L (t), V C (t) duing this stage can be deduced: Vt t) = ( Vin V ( t)) cos w ( t t) L /( L + L ) (2) ( C m L C i ( t) = ( Vin V ( t))sin w ( t t) / Z (3) Figue 3. Wavefom of bust opeation a) Bust opeation pocess (1) Stage 1 of bust opeation The fist stage (t-t1) is the esonant enegy established time. The dive signals ae blocked befoe this stage. The initial condition at t is assumed that: Voltage of switch Q1 is V Q1 (t), Resonant cuent i Lm (t) is zeo, Voltage of esonant capacito C is V C (t). Then at t, dive signals ae ecoveed, switch Q1, Q4 and Q2, Q3 ae tuned on altenately. Suppose that the fist switch tuned on is Q1 in this stage, so paasitic capacito of Q1 is dischaged to zeo and that of Q2 is chaged to Vin. This had switching pocess will cause powe loss: P = 2Vin V 1 ( t) Coss (1) h Afte this had switching, input voltage Vin is coss the esonant tank: L, C and Lm. So esonant cuent i L begins to ciculate, pimay tansfome voltage Vt begins to ise and Q whee Vc( t) = Vin ( Vin V ( t)) cos w ( t t) (4) w = 1 / ( L + L ) C, Z = ( L + L ) C. m C m / Fom the (2), it can be seen that Vt(t) can not ise highe than N ( Vo + VFD) in fist half cycle, because N ( Vo + VFD) 1. 1Vin is designed and V C (t) is positive which can be deduced late, seconday diodes will not conduct with diode ectifying. But if seconday synchonous MOSFET is tuned on with SR contol scheme mentioned above, the output voltage will be coss the tansfome and magnetizing inductance Lm instantly, which will poduce evese cuent flowing fom seconday to pimay side and cause lage powe loss, so discading SR diving signal is the optimum opeation in this stage. Resonant cuent i L (t) inceases fom zeo to i L (t1) and V C (t) is chaged to V C (t1) highe than V C (t). Resonant enegy is established duing this stage to ensue powe tansmission in next stage. Powe loss of this peiod includes the had switching loss P h and conduction loss P con1, coe loss P coe 1 and switching loss P sw 1 which can be assumed as half cycle loss of nomal opeation at light load. Pcon + Pcoe + Psw P 1 = ( Ph + ) fbust (5) 2 whee: Pcon, Pcoe, Psw ae conduction loss, coe loss and switch loss of each cycle without bust contol at light load. (2) Stage 2 of bust opeation The second stage (t1-t2) is powe convesion time. Q1, Q4 ae tuned off at t1, and afte a shot deadtime, Q2 and Q3 ae tuned on. Geneally, this switching is soft o patial soft because of i L (t1) established. Afte this switching, Vin is added to the esonant tank. Vt(t) of this time can be deduced: /9/$ IEEE 59

3 whee w Vt( t) = ( Vin V Z I L C ( t1))cos w ( t t1) ( t1) sin( t t1) = 1 / L C, Z = L / C. Though caefully design, Vt(t) will be highe than N ( Vo + VFD) at this time, and diodes of seconday side will conduct because VC(t1) is positive and esonant capacito has been chaged fo a half switching cycle. SR contol can be used in this stage, and opeation pocess is just the same as nomal. Powe tansmits fom pimay side to seconday side duing this peiod, and high efficiency is pusued. So, woking cycles duing this peiod should be designed to wok at as load with high convesion efficiency. That detemines the length of this stage which can be defined as bust duty. il D bust = (7) I Lh whee: i L is the load cuent cuently, I Lh is the load cuent with high efficiency. Fom (7), D bust should be egulated with load to maintain same opeation condition of each woking cycle with vaious load condition. But esonant cuent will vay in each opeation cycle due to inceasing Vo in each cycle. Befoe this stage, load is supplied by output capacito Co, and Vo falls to Vo(t1) the lowest voltage value duing the whole bust peiod. Afte t1, Co is chaged in each switching cycle, and Vo inceases gadually in this stage, then Vo eaches the highest point at t2. i L (t) s vaiety is opposite to Vo, the esonant cuent deceases gadually in this peiod, the highest value is poduced at the fist switching cycle. So efficiency of each cycle is not the same, and the efficiency of whole peiod is the mean value of all cycles. The loss of this peiod is distibuted just as the nomal opeation, including switching loss, coe loss and conduction loss. So the powe loss can be estimated appoximately as: P N 2 = Psw _ i + Pcon _ i + Pcoe _ i + Pcap _ i ) i= 1 (6) ( f (8) P con _ i P coe _ i sw _ i bust whee:, and P ae coesponding conduction loss, coe loss and switching loss of each cycle with nomal opeation at heavy load. P is output cap _ i capacito loss of each cycle mainly caused by ESR and is lage in this stage because of lage pulse chaging cuent. This loss will be discussed in next section in detail. If it is assumed that esonant cuent of each cycle is the same and has the same efficiency, the loss can be calculated as: heavy load. P is capacito loss of each cycle, and f is cap switching fequency of heavy load at nomal contol. (3) Stage 3 of bust opeation The last stage (t2-t3) is idle time, and diving signals ae blocked duing this stage. This stage can be subdivided into two stages. The fist one is time fom t2 to t2 and the othe is fom t2 to t3. Figue 5. Equivalent woking cicuit fom t2 to t2 At time t2, Q1 and Q4 have been tuned off, so esonant cuent dischages paasitic capacito of Q2 and chages paasitic capacito of Q1, and same thing happens to Q3 and Q4. Fig.5 shows the equivalent woking cicuit in this sub-stage. The paasitic capacitos of Q2 and Q3 will be dischaged to zeo and that of Q1 and Q4 will be to Vin, then this cuent will chage the pimay capacito though body diodes of Q2, Q3 until i L (t) deceases to zeo. Meanwhile, seconday diodes will conduct, and i L (t) will chage output capacito though tansfome until i L (t) is lowe than i Lm (t). i L (t) and V C (t) can be deduced in this peiod: il( t) = il( t2)cos w( t t2) + Vin Vo Vc( t2) sin w ( t t2) Z Vc( t) = ( Vin Vo Vc( t2))cos w ( t t2) Vin Vo + zil( t2)sin w ( t t2) sw (1) (11) whee w = 1 / L C, Z = L / C. At the end of this peiod, V C (t) will be chaged highe than V C (t2) which is the highest value at nomal opeation, and i L (t) will be dischaged to zeo. Then, body diodes of Q2 and Q3 ae evese biased, esonant components including paasitic capacitos of pimay and seconday switches, esonant inducto, esonant capacito and magnetizing inducto begin fee oscillation. The equivalent cicuit is show in Fig.6. Cp1 is the paasitic capacitos of Q1 and Q3, Cp2 is that of Q2 and Q4, and Cs is the paasitic capacitos of seconday switches. P = ( P + P + P + P ) D f 2 sw con coe cap bust sw (9) whee: Pcon, Pcoe and Psw ae conduction loss, coe loss and switching loss of each cycle with nomal opeation at Figue 6. Equivalent woking cicuit fom t2 to t /9/$ IEEE 6

4 This oscillating enegy will attenuate step by step fo consumption by ESR of inductos and EPR of capacitos. At the end of oscillation, the esonant cuent will attenuate to zeo, and the voltage of capacitos afte oscillation can be calculated: 1 1K V C ( t3) = ( Vin VC ( t2' )) (12) 2C + Cp C p + 1 Loss(W) 5 1K 5K whee: C p is paalleled capacitance of two pimay switches. Because Cp is much smalle than C, almost one tenth of C; and V C (t2 ) is compaable with Vin, V Cp1 (t3) will be lage than Vin/2. So, if Q1 and Q4 ae chosen to tun on fistly in next bust peiod, less had switching loss in stage 1 will be achieved. The powe loss in this stage mainly includes conduction loss and coe loss. Loss poduced in fist sub-stage can be calculated as one quate of conduction loss and coe loss of nomal opeation. Enegy emained in esonant tank is little, so loss poduced by oscillation can be neglected. So powe loss in this stage is: Loss(W) A il Io Figue 7. Loss calculated with vaious loads 2A 15A 1A 5A Pcon + Pcoe P3 = fbust (13) 4 whee: Pcon and Pcoe ae conduction loss and coe loss of each cycle with nomal opeation at light load. b) Loss analysis of bust opeation Fom analysis above, we can get whole powe loss of the bust opeation as: P = P (14) 1 + P2 + P3 Accoding to (14), bust fequency and duty affect the efficiency a lot. Loss poduced duing stage 1 and 3 will be lage with highe bust fequency and lowe fequency will cause audible noise and affect a lot on opeation in stage 2 because low bust fequency will poduce lage output ipple, esonant cuent in each woking cycle will be much diffeent, so high efficiency in each cycle can not be ealized. But this influence on stage 2 is not eflected in this equation, and same opeation condition of each cycle of stage 2 is assumed. Fig.7 shows the loss calculated with vaious load. The bust fequency selected is 1K, 5K and 1K, and the dashed line show the loss at light load with nomal contol. It can be seen that the loss inceases with load unde bust contol, and will be lage than loss of nomal contol at some load point. Fig.8 shows the loss cuve vaying with diffeent bust fequency, and load condition is 5A, 1A, 15A and 2A. Low loss can be achieved with low fequency. The influence of bust duty is clea. If D bust calculated is not applied, each cycle of stage 2 will not wok at load with high efficiency, so high efficiency of bust contol can not be ensued fbust (Hz) Figue 8. Loss calculated with vaious bust fequencies Fig.9 shows loss compaison with vaious bust duty. The loss shown in solid line has minimum value unde vaious loads, and it is calculated by (7) using I Lh with highest efficiency. If othe bust duty without optimum design is applied, the loss poduced will be lage, as loss shown in dashed line and dot line. Loss(W) c) Summay 1 5 i L D Bust = 5 i L D Bust = 8 i L D Bust = il (A) Figue 9. Loss compaison with vaious D bust Based on analysis of opeation pocesses and loss of bust opeation, seveal opeation ules should be applied to achieve the highest efficiency with bust opeation: The fist SR diving signal should be discaded to pevent fom enegy flowing evesely. Bust duty should be egulated accoding to load cuent by (7), and I Lh selected should be the load cuent with the highest efficiency /9/$ IEEE 61

5 z z If CLC filte is applied, output capacito selection can only focus on two aspects: output voltage ipple will not be highe than the maximum voltage stess of SR MOSFETs, and ESR loss of capacito caused by lage chaging cuent in stage 2 can satisfy equiement. Equation (16) can be used to calculate the ESR loss of each cycle, and the diffeence between bust contol and nomal contol is that Io is the mean value of io(t ) in nomal contol, but in bust contol, Io is much smalle. As shown in Fig.12, with same ectified cuent io(t ), Io in solid line is output cuent in nomal contol which equals the mean value of io(t ), and the dashed line is output cuent unde bust contol which is much lowe. The diffeence between io(t ) and Io is the AC cuent flowing though ESR of output capacito, which is much lage unde bust contol than unde nomal contol which will cause lage loss. Bust fequency should be selected as low as possible by consideation of output ipple equiement, output capacito selection, etc. The switch tuned on fist in this bust peiod should be the switch last tuned off in last bust peiod in ode to educe fist had switching loss. III. OUTPUT FILTER DESIGN Output capacito plays a vey impotant ole in bust contol. This capacito will influence not only the output voltage ipple but also the loss in bust contol..15 C(F) ) 1K.1 ) Pbust =.5 5K 4K.5.1 T (io(t ) Io) 2 ESR dt (16) whee: io(t ) is ectified cuent in seconday side, and Io is the mean value of output cuent..15 U(V) Figue 1. Capacitance needed with diffeent ipple equiements io(t) Because powe tansmitted to output capacito is discontinues unde bust mode contol, thee is output voltage elated to bust fequency. To satisfy ipple equiement, the capacitance needed without consideation of ESR of capacitos is: Io Figue 12. Cuent wavefoms of output capacito Io C= U f bust (15) Fig.13 shows the loss of each cycle vaying with ESR. The solid line epesents the loss unde bust contol at 1% load, and dashed line epesents the loss unde nomal opeation at 5% load. The loss of each cycle with bust contol is appoximately twice of nomal contol with same ESR, so exteme low ESR capacito should be selected to educe this loss with bust contol. whee: U is the voltage equiement. Fig.1 shows the capacitance needed with diffeent ipple equiement, and the dashed line is the capacitance needed with nomal contol. 1mF capacitance is needed fo 1mV voltage ipple equiement with 1 KHz fbust; coespondingly, only 25 uf is needed in nomal opeation. If influence of ESR is consideed, the demand fo this capacito will be much highe. To decease the demand of this capacito, CLC filte can be selected. Fig.11 shows the CLC filte stuctue, Lf and Cf ae added to filte output voltage ipple. 6 Loss(/1-5 W) Lf 8 Cf Bust contol 4 Nomal contol 2 C ESR(Ω) es Figue 11. CLC filte stuctue Figue 13. ESR loss of capacito of each cycle The design ule of these two components is: the coss fequency should be lowe then bust fequency, and ensue enough attenuation at bust fequency in ode to depess ipple to satisfy equiement. Fo loss and dynamic consideation, Lf is one tun, and satuate at load not using bust mode. IV. CONTROL STRATEGY /9/$ IEEE Based on analysis above, bust duty should be egulated by load cuent to ensue high efficiency. Bust fequency 62

should be fixed by tadeoff between output capacitance of output capacito, audio noise and efficiency. Fig.14 is the poposed contol diagam of bust mode contol.

6 should be fixed by tadeoff between output capacitance of output capacito, audio noise and efficiency. Fig.14 is the poposed contol diagam of bust mode contol. The cuent sense module sense load cuent, and this load signal is sent to micopocesso to geneate coesponding bust duty with fixed fequency. To pevent fom bust duty switching so fequently, piecewise contol is applied. As shown in Fig.15, bust duty is divided into seveal pieces, and aound each switching point, thee is a hysteesis loop. pimay cuent ip, output voltage Vo and DS voltage of Q2 at 15A load. Fig.17 shows the efficiency tested with vaious load condition, and Fig.18 shows the tested loss. ip Vds cuent sense MCU Figue 14. Contol diagam of bust mode Accoding to desciption above, the bust duty is egulated by output cuent with fixed bust fequency and open loop contol; output voltage is egulated by switching fequency as nomal contol. So this kind contol can obtain stable woking opeation and output egulation. But also because of the fixed bust fixed duty and fequency, the high efficiency of exteme light load, such as lowe than 2% load, can not be achieved. But that fom 5A to 15A is unde optimum design. Figue 16. Wavefoms of Vo, Vds, ip at 15A Bust contol Nomal contol Load (A) Figue 17. Efficiency compaison with vaious loads Nomal contol W) Bust contol Figue 15. Contol stategy of bust duty V. EXPERIMENTAL RESULTS The poposed bust mode contol is implemented on a built pototype. The switching fequency of LLC unde nomal contol is 38 KHz, output is 12V/1A, and the highest efficiency 97.4% is poduced at 5A load. The designed paametes of bust contol ae listed in table.2. TABLE II Key paametes of bust mode Bust fequency Output capacitance ESR of C Lf Cf 1K 8mF 2.3m 1uH 2mF Bust mode contol is applied at load unde 15A, namely 15% load. Fig.16 shows the expeimental wavefoms of Load (A) Figue 18. Loss compaison with vaious loads Fom Fig.16, it can be seen that the fist switching is had switching, and thee is no powe tansmission in the fist half switching cycle. Afte that, thee ae seveal cycles fo powe convesion, esonant cuent deceases gadually, and Vo inceases gadually. Then, powe emained in esonant tank flows evesely in about one quate cycle and oscillation begins. Vds of Q2 oscillates aound voltage level lowe than Vin/2, and the output voltage ipple afte LC filte is lowe than 1 mv. Fom the compaison data shown in Fig.17 and Fig.18, it can be seen that efficiency can be impoved a lot. VI. CONCLUSION To achieve high light load efficiency of LLC convete, bust mode contol is applied in this pape. With detailed analysis, Bust mode opeation of LLC with SR is divided into thee pocesses, and loss distibution of each pocess is discussed caefully in ode to find the ules of educing powe loss as low as possible. Output filte fo bust mode /9/$ IEEE 63

7 contolled LLC is also studied to meet voltage ipple equiement and educing ESR loss. As a total solution, coesponding contol stategy is also poposed. To veify the analysis and contol method, a pototype with 12V/1A was built, and efficiency at light load can be impoved significantly, such as efficiency at 1% load can be impoved fom 92.5% to 94.8%. Based on the analysis and expeimental esults, some conclusions can be obtained: Bust mode contol can be applied to impove light load efficiency of LLC convete with SR. The suitable pimay and seconday diving timing and low bust fequency should be selected, to achieve the high efficiency. Low ESR output capacito should be selected to educe ESR loss, and LC filte can be added to meet output ipple equiement. Suitable contol stategy ealizes bust duty vaied with output cuent to achieve the high efficiency. REFERENCE [1] Bo Yang, Fed Lee, Alpha J. Zhang, Guisong Huang, LLC Resonant Convete fo Font End DC/DC Convesion, IEEE Applied Powe Electonics Confeence and Exposition (APEC 2), 22. [2] Ocean Wu, Cutis Wang, John Zeng, Jianping Ying, A Method of Synchonous Rectification fo LLC Convete, Poceeding of DPEC Semina, 27 [3] Jin-ho Choi, Dong-young Huh, Young-seok Kim, The Impoved Bust Mode in the Stand-by Opeation of Powe Supply, IEEE Applied Powe Electonics Confeence and Exposition (APEC 4), 24. [4] Yu Fang, Dehong Xu, Yanjun Zhang, Fengchuan Gao, Lihong Zhu, Yi Chen, Standby Mode Contol Cicuit Design of LLC Resonant Convete, IEEE Powe Electonics Specialists Confeence (PESC 7), pp , /9/$ IEEE 64

Design of an LLC Resonant Converter Using Genetic Algorithm

Design of an LLC Resonant Convete Using Genetic Algoithm H. H. Nien, C. K. Huang, S. K. Changchien, C. H Chan Dept. of Electical Engineeing, Chienkuo Technology Univesity E-mail: nien@ctu.edu.tw Dept,