UNIVERSITY OF CALGARY. Tahsina Hossain Loba A THESIS SUBMITTED TO THE FACULTY OF GRADUATE STUDIES IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE

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1 UNIVERSITY OF CALGARY Improving Inverter Efficiency at Low Power Using a Reduced Switching Frequency by Tahsina Hossain Loba A THESIS SUBMITTED TO THE FACULTY OF GRADUATE STUDIES IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE GRADUATE PROGRAM IN MECHANICAL AND MANUFACTURING ENGINEERING CALGARY, ALBERTA SEPTEMBER, 2015 Tahsina Hossain Loba 2015 i

2 Abstract The inverter is a major component of a renewable energy system and its performance affects the overall performance of the system. For typical household applications in rural areas, often there is need to operate at low power conditions where inverter efficiency can drop dramatically. Efficient operation at low power is important especially for stand-alone solar systems in developing countries where system cost must be kept low. In this thesis, the impact of switching frequency upon switching loss for a SPWM inverter is investigated. Results, from mathematical modeling, simulation and experimental implementation, show the same trend that reducing the switching frequency reduces switching loss at low power levels thus improves inverter efficiency. This may result in a reduced PV module size requirement and thus lower system cost. The inverter proposed in the thesis operates efficiently at low power (e.g. 9W) as well as at rated power conditions (e.g. 200W). ii

3 Acknowledgements In the name of Allah, the Most Beneficent, the Most Merciful. I am highly grateful to my supervisor, Dr. David Wood, and co-supervisor Dr. Ed Nowicki for their kind support, invaluable advice, readiness to have meetings frequently throughout the period I have been doing research work. I am thankful to them for believing in me and supporting me morally and intellectually when I was struggling with my experiments. I am also thankful to my colleagues for their continuous inspiration. I am most thankful to Allah who helped me at every stage during the course of my research work and life. iii

4 Dedication I dedicate this thesis work to my beloved husband, Wali, who constantly supported me through the entire time I spent in this master s program. Without his help and support, it would not have been possible to complete the degree. iv

5 Table of Contents Abstract... ii Acknowledgements... iii Dedication... iv Table of Contents... v List of Tables... vii List of Figures and Illustrations... viii List of Symbols, Abbreviations and Nomenclature... x CHAPTER ONE: INTRODUCTION Problem Statement Background and Motivation Objective of the Thesis Scope of the Thesis Thesis Outline... 6 CHAPTER TWO: LITERATURE REVIEW DC/AC Power Inverter Categorizing Power Inverters Modified Sine Wave Inverters Full Bridge Inverter Pulse Width Modulation SPWM Switching Techniques SPWM with Bipolar Switching SPWM with Unipolar Switching Advantages of using Unipolar SPWM Overview of the Related Work Chapter Summary CHAPTER THREE: INVERTER LOSS MODEL AND DESIGN CONSIDERATIONS Introduction Full Voltage Design and Scaled Down Design Proposed Inverter Topology Inverter Loss Components based on Loss Model Conduction Losses Switching Losses IGBT Gate Drive Losses Inverter Efficiency Calculation Chapter Summary CHAPTER FOUR: SIMULATION RESULTS FOR PROPOSED FULL BRIDGE INVERTER Schematic of the Full Bridge Inverter System under Study v

6 4.2 Simulation Circuit Description SPWM Controller Gate Drive Circuit IGBT Switching Circuit Different Load Conditions Simulation Results Chapter Summary CHAPTER FIVE: EXPERIMENTAL RESULTS Introduction Hardware Overview Power Supply for Transistor Drive Circuit Isolation Circuit Optocoupler Circuit Operation Full Bridge Inverter Circuit Snubber Circuit RC Snubber Load Modeling and Load Value Calculations Determination of Component values for Light Load (CFL) Model Heavy Load Model Calculations Current Sense Resistors Experimental Results Measurement Approach Results and Discussion Chapter Summary CHAPTER SIX: CONCLUSIONS Summary Contributions Suggestions for Future Work REFERENCES APPENDIX A: SCHEMATIC DIAGRAM OF FULL BRIDGE INVERTER APPENDIX B: COMPONENT LIST FOR EXPERIMENTAL SETUP APPENDIX C: MICROCONTROLLER (MSP430G2553) OVERVIEW APPENDIX D: MICROCONTROLLER CODE vi

7 List of Tables Table 3.1 Power Loss Calculation under Different Load Conditions for Variable Switching Frequency (for Vdc, Rated Power 200W) Table 3.2 Efficiency under Different Load Conditions for Variable Switching Frequency (for Vdc, Rated Power 200W) Table 3.3 Power Loss Calculation under Different Load Conditions for Variable Switching Frequency (for 25Vdc, Rated Power W) Table 3.4 Efficiency under Different Load Conditions for Variable Switching Frequency (for 25Vdc, Rated Power W) Table 4.1 Unipolar SPWM Switching Logic Table 4.2 Simulation Results Under Different Load Conditions For Variable Switching Frequency (For Vdc) Table 4.3 Simulation Results Under Different Load Conditions For Variable Switching Frequency (For 25Vdc) Table 5.1 Hardware Results of Full load and Light load Table 5.2 Comparison of the efficiencies vii

8 List of Figures and Illustrations Figure 2.1 Modified Sine Wave, Sine Wave, Square Wave Inverter Output Waveforms. 9 Figure 2.2 Modified Sine Waveform Figure 2.3 Full Bridge Inverter Topology Figure 2.4 (a) Comparison of Triangular Wave and Sinusoidal Wave (total time period = 20ms, 1ms per division (horizontally), 0.1V per devision (vertically) ) Figure 2.4 (b) Resultant SPWM Wave (total time period = 20ms, 1ms per division (horizontally), 0.1V per devision (vertically) ) Figure 2.5 Comparator Used to Generate the Bipolar SPWM Signals Figure 2.6 Waveform for SPWM with Bipolar Voltage Switching (a) Comparison of Reference and Triangular Waveform (b) Output Waveform with Sinusoidal Fundamental Component Shown by Dashed Line Figure 2.7 Two Comparators Generating Unipolar SPWM Signal Figure 2.8 Waveform for SPWM with Unipolar Voltage Switching (a) Comparison of Reference and Triangular Waveform (b) Gating Pulses for A + and B- (c) Gating Pulses for A- and B + (d) Output Waveform Figure 3.1 Block Diagram of Inverter System Including Controller Figure 3.2 IGBT Vce and Rq (where, Rq = Vce/ iq) at Rated Load Condition; note that points plotted here are taken from the Device Datasheet Figure 3.3 Diode Vd and Rd (where, Rd = Vak/ id) at Rated Load Condition; note that points plotted here are taken from the Device Datasheet Figure 3.2 IGBT Vce and Rq (where, Rq = Vce/ iq) at Light Load Condition; note that points plotted here are taken from the Device Datasheet Figure 3.3 Diode Vd and Rd (where, Rd = Vak/ id) at Rated Load Condition; note that points plotted here are taken from the Device Datasheet Figure 4.1 Schematic of Controller for generating SPWM gating signals as used in PSpice Simulations Figure 4.2 Simulated Waveforms for SPWM with Unipolar voltage switching (a) Sinusoidal Reference waveform and Triangular Carrier waveform, (b), (c),(d),(e) gating pulses for A +, A-, B +and B- respectively after Sine and Triangular comparison viii

9 Figure 4.3 PSpice Modelling of IGBT Gate Drive Circuit. (a) PSpice Gain Circuit which is also called an E Block. (b) Op Amp Symbol. (c) Op Amp model Figure 4.4 Simulated Output Voltage Waveform of the inverter at 2.5kHz for SPWM with the Unipolar Switching Figure 4.5 Schematic of Equivalent Circuit of CFL Model connected as a load at the inverter output Figure 4.6 Simulated Current Waveform from the Equivalent Circuit of CFL Model connected as a Load at the Inverter output (Total Time Interval = 30ms, 1ms time division (horizontally), 10mA current division (Vertically)) Figure 4.7 Simulated Voltage Waveform from the Equivalent Circuit of CFL Model connected as a load at the inverter output (Total Time Interval = 20ms, 1ms time division (horizontally), 50V voltage division (Vertically)) Figure 4.8 Schematic of Equivalent Circuit of CFL Model connected as a load at the inverter output Figure 4.9 Simulated Current Waveform from the Equivalent Circuit of Heavy Load Model connected as a load at the inverter output (Total Time Interval = 30ms, 1ms time division (horizontally), 1A current division (Vertically)) Figure 4.10 Simulated Voltage Waveform from the Equivalent Circuit of Heavy Load Model connected as a load at the inverter output (Total Time Interval = 20ms, 1ms time division (horizontally), 50V voltage division (Vertically)) Figure 5.1 Partial Schematic of the Experimental Inverter System Figure 5.2 Internal Circuit of FOD3184 IC Figure 5.3 Block Diagram showing Optocoupler Interface Figure 5.4 Equivalent Circuit of the Snubber Circuit Figure 5.5 Equivalent Circuit Model of CFL for Scaled Down Version Figure 5.6 Equivalent Heavy Load for Scaled Down Version Figure A-1 Full Bridge Inverter Supplying Power to the Heavy Load Figure B-1 DC-DC Converter NME0515SC Figure B-2 DC-DC Converter NME0515SC Figure B-3 Optocoupler FOD ix

10 List of Symbols, Abbreviations and Nomenclature Symbol A A + B B + C dc C s C Load C gate D E E off E on E tot E f Control f carrier f sw I I CC I F I PK I Total I d(rms) I dc I o (pk) I q(rms) I RMS I test I Out (t) I in (t) K g m a m f P emitter P gate driver(tot) P internal P input P output P q con Definition Bottom left switch Upper left switch Bottom right switch Upper right switch DC load capacitor Snubber capacitor Load capacitor Total gate capacitance Duty cycle Total energy dissipated Turn off energy loss IGBT Turn on energy loss IGBT Total energy loss IGBT Total energy dissipated Frequency of control signal Frequency of carrier signal Switching frequency Closed circuit current Collector Current LED forward current Worst case peak current Total current through load circuit RMS current flowing through diode DC current for charging circuit Peak load current RMS current flowing through IGBT RMS output current Test current IGBT Output current in time domain Input current in time domain Correction factor Amplitude modulation index Frequency modulation index Emitter power loss Total gate driver loss Internal circuitry power loss Input power Output power Total conduction loss IGBT x

11 P d con P tot sw Q gate R Load R Sense R d R q S t On v ak v ce v ak v ce V q V d V o V s V F V q +V DC V DC V CC V EE V GE V Carrier V Control V system V rect V RMS V Total V test V Out (t) V in (t) V control V carrier V ce V ak X C Z θ CFL Total conduction loss diode Total switching loss Total gate charge Load resistor Sense resistance Diode on state resistance Collector to emitter on state resistance Apparent power Turn on voltage of IGBT Diode forward voltage Collector to emitter voltage Diode forward voltage Collector to emitter voltage IGBT on state voltage Diode on state forward voltage Open circuit voltage Bus voltage LED forward voltage IGBT on state voltage Positive DC Voltage Negative DC Voltage Supply voltage Emitter Voltage Gate to emitter voltage Triangular carrier signal Reference sinusoidal signal Input AC system Rectified voltage RMS output voltage Total supply voltage Test voltage IGBT Output voltage in time domain Input voltage in time domain Peak magnitude of control signal Peak magnitude of carrier signal Voltage difference between collector and emitter Voltage difference of diode forward voltage Capacitive reactance Total impedance Total CFL phase angle Total heavy load phase angle xi

12 Chapter One: Introduction Much of the world s population is without electricity. Solar energy is a sustainable means of providing electricity, and is especially suitable for locations where it is difficult or too expensive to construct high voltage transmission lines. The efficiency of a solar energy system largely depends on the efficiency of the system power inverter. This thesis addresses the inverter efficiency issue at low power levels for rural stand-alone solar home systems. Chapter one describes the research problem, motivation behind the research, contributions and brief outline of the next chapters. 1.1 Problem Statement In the case of a stand-alone rural solar home system in a developing country, the typical load profile can vary between 0W to 200W [1]. Under optimal conditions for a rural stand-alone solar home system, the inverter may operate at around 85%-95% efficiency while operating at its maximum rated power. 200W is considered as the maximum rated power in the context of this thesis. But the efficiency of the same inverter drops significantly while operating under 20% of its maximum rated load [2]. This is a challenging problem for a stand-alone solar home system in a developing country where the household load profile remains at low power for most of the time during the day and at night [3]. The inverter efficiency at low power is investigated and improved in this thesis which may improve the overall usefulness of the solar home system. Specifically, 9W (4.5% of maximum rated power 200W) is considered as an example of low power that might 1

13 be used to operate a Compact Fluorescent Lamp (CFL). The improvement in inverter efficiency may result in decreased cost of the overall solar home system. Previous research [3], [24], [25], [26], [27], [28], [29], [30] does not sufficiently address the low power (i.e. 5W-10W) inverter efficiency problem found in rural solar home systems in developing countries. To address the problem in this thesis, a 200W inverter is simulated and a scaled down W version is implemented experimentally. The W version was chosen for quick implementation, but operated at RMS current level of the full voltage design. The proposed inverter has acceptable efficiency even at low power levels with a simple control circuit and without the need of a filter circuit at the inverter output. However, it is yet to be determined which loads can be operated without the output filter. 1.2 Background and Motivation Due to geographical and socio-political challenges, over 1.2 billion people or 20% of the world's population, are without access to electrical grid power, almost all of whom live in the developing countries. Hence, the development of micro-grids and stand-alone power systems is seen as an economic way to raise the living standard for remote villages which are not connected to the grid. One of the renewable sources that receives much attention is solar photovoltaic (PV) power. Every hour the sun radiates more energy onto the earth s surface than is consumed globally in one year [4]. To harness the power of solar energy, improvements in the efficiency of photovoltaics and electrical storage are required to reduce the variability and intermittency of solar power. So, considering a scenario where there is no electric grid connection and ample sunlight, a stand-alone solar home system is often preferable to other forms of renewable energy. The main components 2

14 of a typical solar home system are solar module(s), charge controller, battery, DC-DC converter and the inverter. One of the essential parts of the stand-alone solar home system is a single-phase full-bridge inverter. An inverter is necessary because the majority of the electrical appliances run on 220VAC (applicable for developing countries in general). The inverter is needed to convert the DC output of the solar module or battery into usable AC power. In a typical developing world context, residential electrical demand is highly dynamic and stays at low power levels for about 20 hours in a day [3]. For a rural solar home system, the load demand remains at low power (1W to 10W) for a significant amount of time, especially at night. Improving inverter efficiency at low power means more efficient use of the renewable energy resource. Conversion efficiency is a prime consideration for all switch-mode power supplies (SMPSs). It is even more critical for solar home systems, where prolonging battery life is a key goal, especially at night and for cloudy days, when there is little or no solar energy supply from the PV modules. In addition, if the energy input to the inverter can be efficiently converted at low power, it is suggested in this thesis that it may also be possible to reduce the PV module area. In both cases this may result in savings of the system capital cost. At low power, switching loss becomes a significant portion of total power that is wasted. Thus, the switching loss is mainly responsible for the decrease in efficiency of the inverter during low power operations. One way to reduce switching loss at low power is to reduce the switching frequency which also results in decreased power quality. The term power quality is used in reference to the voltage, current and frequency of the power delivered [5]. For the purposes of this thesis, high power quality means a sinusoidal inverter output voltage of nominal RMS voltage at 3

15 the nominal power frequency. Power quality is an issue in grid connected inverters and there are stringent requirements to comply with standards (e.g. IEEE Std 1547 is typical of such standards). Also, the IEEE [6] and the IEC [7] standards put limitations on the maximum allowable amount of injected dc current into the grid [8]. However, the power quality of a stand-alone solar home system is not subject to these constraints. In this thesis, it is suggested that a reduction in switching frequency at low power levels, and some degradation in power quality, may result in a significant improvement in inverter efficiency at low power levels. Another motivating factor is that higher switching loss not only results in reduced energy efficiency but also exerts more stringent requirements on the thermal management for the switching devices. 1.3 Objective of the Thesis The objective of the thesis is to develop an inverter for low power applications (on the order of 50W to 500W rated power) with high efficiency operation over a wide range of power levels (i.e. down to about 5% of the rated power). One example of a low power load is a Compact Florescent Lamp (CFL) which may consume only 5W to 10W depending on the light output desired. As noted above, in this thesis the inverter is rated for a power output of 200W (this is also referred to as the maximum rated power) and low power operation of that inverter is considered to be 9W or 4.5% of 200W. Therefore, the objective is to design an inverter that operates efficiently both at low power and maximum rated power. Using simulation, a 200W inverter prototype is designed which has about 85% efficiency even when operated at 9W utilizing inexpensive and reliable components available in a developing country. 4

16 1.4 Scope of the Thesis In this research, inverter efficiency is improved for low power operation by reducing switching frequency. Inverter switching loss (the dominant loss component at low power) is a function of switching frequency and the current flowing through the switching device [3]. The choice of the switching frequency involves a trade-off between requirements for high efficiency, sinusoidal output power quality if a filter is employed, and low cost [8]. At rated power (200W in this context) there are several kinds of losses that play a significant role in terms of decreasing the inverter efficiency [5]. Low power means less current, less current means less loss but switching losses increase in proportion to the switching frequency for a given constant load level [9], [10]. That means, reduction of switching loss at low power is the key to improved inverter efficiency. Therefore, to address the research problem, switching frequency is reduced to improve the inverter efficiency at low power. In addition, inverter output characteristics and power quality are also considered while operating at a reduced switching frequency. The reduced switching frequency does reduce power quality, but it is expected that most household loads will tolerate this reduced power quality. The scope of the research includes the following: 1. Inverter loss model and efficiency calculation based on mathematical analysis. 2. Inverter simulation in OrCad PSpice to observe efficiency for heavy and light load profiles. 3. Experimental implementation of the scaled down version (of rated power W) for quick prototype development to observe inverter efficiency. 5

17 4. Analysis of efficiency trends by comparing efficiencies found in mathematical analysis, simulation and experimental implementation. 1.5 Thesis Outline The remainder of the thesis is organized as follows: Chapter 2 briefly presents the relevant literature and describes recent research to improve inverter efficiency at low power. A classification of different kinds of inverters commonly used in a standalone solar home system is presented. The detailed working principles of the modified sine wave inverter and the reason for using this inverter is explained in detail. The full-bridge inverter topology is also discussed in this chapter. The switching pattern of the full- bridge inverter using the USPWM (Unipolar Sinusoidal Pulse Width Modulation) technique is presented in a table to explain the states of each transistor while switching. The chapter also describes and critiques previous research in the area of low power inverter efficiency improvement. Chapter 3 details a mathematical analysis of the inverter loss components. Transistor and diode model parameters are calculated using datasheet information. The process of obtaining the parameters is a modification of a technique found in the literature. Based on the equations presented in this chapter, a table has been provided showing the individual loss components and the efficiencies for different switching frequencies. This chapter also presents the design considerations and topology of the proposed inverter. The reason behind using a hard switched inverter instead of using a soft switched is explained in detail. 6

18 Chapters 4 presents the computer simulation results of the proposed inverter. The simulation results are discussed and analyzed in terms of efficiency for different switching frequency and load levels. Equivalent load models of the heavy load and light load conditions are implemented in PSpice to observe the output voltage and current characteristics of the inverter. A similar table to that in chapter 3, showing the total loss and efficiency measurements is presented in this chapter. Chapter 5 describes experimental implementation of the scaled down version of the proposed inverter. It begins with an overview of the overall inverter prototype and how different blocks interact with each other to provide AC at the inverter output. The description of the selection of the overall inverter circuit components is presented. A detailed calculation of the value of the components used to build the equivalent heavy (12.856W) and light (0.578W) load is also provided in this chapter. A comparative analysis of the three results (mathematical, simulation, experimental) is also presented in a table to show the agreement among them. Based on the operation of the scaled down inverter version (i.e W), it is suggested that it is worthwhile to proceed with the full voltage design (i.e. 200W) in the near future. Chapter 6 presents conclusions based on the mathematical model, simulation model and experimental results. Also, future work directions are suggested. 7

19 Chapter Two: Literature Review 2.1 DC/AC Power Inverter Power inverters are devices which convert DC to AC. The purpose of a DC/AC power inverter is to take the DC power supplied by a battery or solar module and transform it into the standard AC output (220VAC at 50Hz in the context of developing countries in general, e.g. Bangladesh residential power). The solar modules and the batteries can store and supply only DC power but most household appliances and other electrical equipments require AC input power to perform. To supply the AC power to the household appliances the inverter is an essential part of the solar home system [8]. 2.2 Categorizing Power Inverters There are three different types of power inverter output waveforms; square wave, modified sine wave and pure sine wave as shown in Figure 2.1. These inverter output waveforms differ, providing varying levels of distortion that can affect electronic devices in different ways. Modified sine wave inverters have a lower Total Harmonic Distortion (THD) than a square wave inverter but higher THD than a sine wave inverter [11]. THD measures how much the power waveform is distorted by the harmonics. For running typical household appliances a modified sine wave inverter is a reliable and cost-effective choice. Though the modified sine wave inverter does not produce a true AC sine wave power, it does provide an affordable option and for many power 8

20 applications is perfectly adequate. Modified sine wave inverters approximate a sine wave and have low enough harmonics that they do not cause problems with typical household equipment [11]. Modified Sine wave sits at zero for a certain time then rises or falls Modified Sine Wave Sine wave Square Wave Figure 2.1 Modified Sine Wave, Sine Wave, Square Wave Inverter Output Waveforms The modified sine wave inverter costs half the price of the sine wave inverter [11]. In the context of a rural stand-alone solar home system, where power quality is not a regulated requirement, modified sine wave inverters provide affordable and portable AC power [12] Modified Sine Wave Inverters In the modified sine wave inverter, there are three voltage levels in the output waveform, positive, negative, and zero as shown in Figure 2.2, with a dead zone between the positive and negative pulses [11]. Modified sine wave inverters can be designed to satisfy the efficiency requirements of the photovoltaic system while being less expensive than pure sine waveform inverters [12]. These inverters are capable of operating a wide variety of loads; electronic and household items including, CFLs, filament bulbs, TV, VCR, satellite receiver, computer, refrigerator, sewing 9

21 machine etc. [13]. Thus, most of the household appliances commonly used in a developing country will work satisfactorily with a modified sine wave inverter [11]. Figure 2.2 Modified Sine Waveform Since modified sine wave inverters have higher THD than pure sine wave inverters, they are not suitable for applications where the power quality requirement is stringent (e.g. grid connected solar systems). Grid connected power inverters must comply with the appropriate standards for THD where modified sine wave inverters do not [6], [7]. After choosing the modified sine wave inverter the next step is to determine suitable topologies and the control techniques for the proposed inverter. 10

22 2.3 Full Bridge Inverter Figure 2.3 displays the basic inverter circuit using the full bridge topology. A full bridge inverter is a switching configuration composed of four switching devices (e.g. IGBT switches) in an arrangement that resembles an H shape (hence the alternative name H-bridge) [13]. The H- bridge circuit may be designed for a particular modified sine wave inverter application. By controlling the switches in the bridge by controller signals, a positive, negative, or zero potential voltage can be placed across the bridge output i.e. between A and B, as shown in Figure 2.3. The switching and control techniques are described in detail in section 2.3. A+ B+ VDC Load + _ A B A- B- Figure 2.3 Full Bridge Inverter Topology The switches used to implement a full bridge configuration can be mechanical or built from solid state transistors, though mechanical switches are almost no longer in use. Normally, Bipolar Junction Transistors (BJT), Metal Oxide Semiconductor Field Effect Transistors (MOSFET) or Insulated Gate Bipolar Transistors (IGBT) devices are used as switches, each type having its own advantages and disadvantages. In this thesis, the IGBT has been used as a switching device due to 11

23 its high-current handling capability and suitability for varying load, low duty cycle (ON time of a pulse divided by the total switching period) and low frequency applications. IGBTs can operate within a wide range of switching frequencies and are very easily configurable for varying switching frequency applications. Generally, the IGBT has superior conduction characteristics compared to the MOSFET. In this thesis, a low loss IGBT is chosen as the switching device as it can operate over a wide range of switching frequencies (<40kHz in hard switching) [14], [15]. 2.4 Pulse Width Modulation There are various ways to control the switches of a full bridge inverter and generate the desired inverter output. In power electronic converters, Pulse Width Modulation (PWM) is extensively used as a means of powering the AC devices from a DC source [16]. Variation of the duty cycle (if the switch is pulsed ON at variable durations, the duty cycle varies) [18] in the PWM signal is used to provide a specific voltage pattern that will appear to the load as an AC signal [17]. The pattern at which the duty cycle of a PWM signal varies, can be created through simple analog components, a digital microcontroller, or specific PWM integrated circuits [13]. Most commonly, PWM signals are generated through the microcontroller due to the ease of implementation, long term-reliability and precise switch timing [14]. Some other techniques are also used for high frequency switching (e.g. multilevel switching, Pulse Frequency Modulation, Pulse Amplitude Modulation, etc.) but due to its many advantages, a PWM technique is usually chosen over other switching techniques. 12

24 PWM is the process of modifying the width of the pulses in a pulse train in direct proportion to a control signal (for example, the greater the control voltage, the wider the resulting pulses) [15]. When the control signal is sinusoidal the process is called Sinusoidal Pulse Width Modulation (SPWM). By using a sinusoid at the desired frequency as the control voltage for a SPWM circuit, it is possible to produce a high power waveform whose average voltage varies in a sinusoidal manner suitable for driving the semiconductor devices used for switching. The analog SPWM control approach requires the generation of both the reference and the carrier signals that feed into a comparator which creates output signals based on the difference between the signals [14]. As mentioned earlier, the reference signal is sinusoidal with the frequency of the desired output signal, while the carrier signal is often either a saw tooth or triangular wave at a frequency significantly greater than the reference frequency. The frequency of the reference signal determines the inverter power output frequency and the reference peak amplitude controls the modulation index and the RMS value of the output voltage [16]. This process is shown in Figure 2.4(a) with the triangular carrier wave in green, the sinusoidal reference wave in red and the resultant SPWM pulses in blue in 2.4(b). 13

25 Figure 2.4 (a) Comparison of Triangular Wave and Sinusoidal Wave (Total Time Period = 20ms, 1ms per Division (Horizontally), 0.1V per Devision (Vertically) ) Figure 2.4 (b) Resultant SPWM Wave (Total Time Period = 20ms, 1ms per Division (Horizontally), 0.1V per Devision (Vertically) ) 14

26 2.4.1 SPWM Switching Techniques The two types of SPWM switching techniques are unipolar and bipolar switching to create either a unipolar or bipolar output at the load. The control signals depend on comparing a reference signal and carrier signal [19], [20]. They are now discussed in turn SPWM with Bipolar Switching This technique uses a comparator as shown in Figure 2.5, to compare the reference voltage waveform V Control with the triangular carrier signal V Carrier as shown in Figure 2.6 (a). In SPWM with bipolar switching, the H-bridge output voltage swings between +Vdc and Vdc as shown in Figure 2.6(b). The switching scheme that will implement bipolar switching using the full bridge inverter, as shown in Figure 2.6, is determined by comparing the instantaneous reference and carrier signals [19]: A + and B are on when V Control > V Carrier (V output = +Vdc) (2.3) B + and A are on when V Control < V Carrier (V output = Vdc) (2.4) 15

27 VControl VCarrier + _ Not A+ and B- A- and B+ Figure 2.5 Comparator Used to Generate the Bipolar SPWM Signals Figure 2.6 Waveform for SPWM with Bipolar Voltage Switching (a) Comparison of Reference and Triangular Waveform (b) Output Waveform with Sinusoidal Fundamental Component Shown by Dashed Line 16

28 SPWM with Unipolar Switching In this scheme, the triangular carrier waveform (V Carrier ) is compared with two control signals (V Control ) which are positive and negative signals. The basic circuit to produce SPWM with unipolar voltage switching is shown in Figure 2.7. The difference between the bipolar SPWM and unipolar SPWM generators is that the latter uses another comparator to compare between the inverse reference waveform V Control shown in Figure 2.7. The comparison of these two signals produces the unipolar voltage switching signal. The output waveform is switched either from high (+Vdc) to zero or from low ( Vdc) to zero as shown in Figure 2.8 (a). The gating pulses of the four IGBT switches and output waveform are shown in Figure 2.8 (b), (c) and (d). The effective switching frequency seen by the load is doubled that of gating signal. Due to this, the harmonic content of the output voltage waveform is reduced compared to bipolar switching. In Unipolar switching, the amplitude of the significant harmonics and its sidebands is much lower for all modulation indexes [19]. VCarrier VControl + _ Not A+ B- VControl + _ Not A- B+ Figure 2.7 Two Comparators Generating Unipolar SPWM Signal 17

29 The switching scheme to implement unipolar switching using the full bridge inverter as shown in Figure 2.8 is determined by comparing the instantaneous reference and carrier signals [20], [21]: A + is on when V Control > V Carrier (2.5) B is on when V Control < V Carrier (2.6) B + is on when V Control > V Carrier (2.7) A is on when V Control < V Carrier (2.8) Figure 2.8 Waveform for SPWM with Unipolar Voltage Switching (a) Comparison of Reference and Triangular Waveform (b) Gating Pulses for A + and B (c) Gating Pulses for A and B + (d) Output Waveform The number of pulses per half-cycle depends upon the ratio of the frequency of the carrier signal (f Carrier ) to the modulating sinusoidal signal (f Control ). The frequency of the control signal (i.e. of the modulating signal) sets the inverter output frequency (f Output ) and the peak magnitude of control signal controls the modulation index m a (ratio of the peak magnitude of control signal, 18

30 V Control to the peak magnitude of carrier signal, V Carrier ) which in turn controls the RMS output voltage. If t On is the width of n th pulse, the RMS output voltage can be determined by [19]: 2p 2t on T V o = Vdc( n=1 ) 1/2 (2.9) The amplitude modulation index is defined as: m a = V Control V Carrier (2.10) where, V Control = peak magnitude of control signal (modulating sine wave) V Carrier = peak magnitude of the carrier signal (triangular signal) The frequency modulation ratio is defined as: m f = f Carrier f Control (2.11) where, f Control = frequency of control signal (sinusoidal wave) f Carrier = frequency of carrier signal (triangular wave) 19

31 2.5 Advantages of using Unipolar SPWM The unipolar SPWM voltage switching scheme is selected in this thesis because this method offers the advantage of effectively doubling the switching frequency of the inverter voltage. A particular advantage of the unipolar SPWM approach is that, this method reduces the harmonics in the single phase inverter [22], [23]. That means, selecting unipolar SPWM as the switching scheme in the proposed inverter is appropriate as there is no filter at the inverter output. 2.6 Overview of the Related Work Researchers have tried to improve inverter efficiency at low power in many different ways. Five different and typical techniques have been identified from the large number of techniques in the literature. These techniques are: 1. Using hybrid switches (combination of MOSFET and IGBT) [3]. 2. Enabling pulse skipping mode (operating the inverter at the maximum efficiency point for shorter intervals) [26]. 3. Implementing a combination of hybrid pulse width modulation (HPWM) and zero voltage switching (ZVS) to improve the efficiency of the inverter for high switching frequency applications [27]. 20

32 4. Resonant mode switching methods can be used such as the LLC burst mode for gridconnected applications (where there is a slight improvement in efficiency for light load related to a small change in switching frequency) [28], [29], [30]. 5. Using variable switching frequency in discontinuous current mode (DCM) (variable switching frequency control method allows extending the input voltage range considerably) [31]. In [3], parallel IGBT-MOSFET switch operation is analyzed and it has been shown that light load efficiency can be improved with hybrid switch use. The faster response of the MOSFET to switching signal commands, compared to the IGBT, is used for minimizing IGBT turn-off losses. This paper suggests that if such a hybrid switch is employed it is better to use the MOSFET only for light loads. The lowest power level is 100W and the efficiency is around 78%. However, consideration must be given to protect the light load switch (MOSFET/IGBT) from a sudden increase in load current. In [26] a pulse skipping control strategy is developed to improve inverter efficiency at low power. The pulse skipping technique is preferable in grid tied inverters. When the input power drops below a certain level, the inverter can be controlled to stop feeding power into the grid continuously. Thus, enter the pulse-skipping operation mode. This strategy is not suitable for stand-alone inverter 21

33 systems due to its complex control circuitry and with this control method the efficiency drops significantly while operating under 30W (where the inverter is rated for 200W). [27] implements hybrid pulse width modulation (HPWM), and zero voltage switching (ZVS) together, to improve the efficiency of the inverter for high switching frequency applications. The HPWM scheme while operating with ZVS during positive half cycle of the output frequency reduces the switching loss to approximately one half of the loss with a standard bipolar PWM technique. However, the efficiency reduces significantly if IGBT switches are chosen instead of the MOSFET switches in the HPWM inverter. Because, the ZVS technique while applied in a HPWM inverter, cannot reduce the losses due to the IGBT tailing current losses. Also, the additional circuitry (containing: parasitic capacitor, resonant inductor, DC-link capacitor, etc.) with an additional DC-link switch in order to implement the ZVS technique for ZVS operation adds some power loss [27]. Efficient operation can only be achieved for a very small load range. The HPWM prototype only works at the high end of the switching frequency range (50kHz to 180kHz) and suffers from high switching losses. In [28] burst mode control along with synchronous rectifier (SR) is applied to improve light load efficiency of an LLC resonant converter. The LLC resonant converter refers to a unique combination of two inductors and one capacitor ( L-L-C ) in the integrated transformer stage before the inverter stage [25], [29]. In this technique, LLC series resonant converter is employed in order to achieve zero voltage switching (ZVS) low turn on and turn off current in the full bridge inverter configuration on primary side of the transformer. While in the half bridge configuration of the secondary side, zero current switching (ZCS) is achieved to maintain low turn on and turn 22

34 off current. Thus, suffers from large switching loss, conduction loss and core loss at light load because of the magnetizing current which flows reversely from secondary to primary. To address this large losses at light load condition, later a burst mode control was applied in order to block the switching driver signals periodically and thus limiting the power conversion only during the time having switching driver signals. Thus, the driver loss and the switching loss were reduced at light load. This method is only applicable for improving inverter efficiency at 10% of the rated load condition, and the ripple voltage and burst mode losses increase significantly at around 5% of the rated load. The LLC series resonant converter needs to be further modified while operating at rated load conditions. In order to address, high voltage ripple at the inverter output at around 10% of the rated load and to reduce losses during burst mode operation, a Capacitor-Inductor- Capacitor ( CLC ) output filter is applied. This technique fails to perform efficiently if the capacitor values are not chosen to satisfy the ripple requirements at different load points. As mentioned above, this technique also requires a resonant transformer stage before the inverter stage, which will add to the overall loss of the system along with increased cost [29]. The switching frequency range is maintained in a relatively narrow range and is applicable only when the switches are controlled through a soft switching method. Further, the overall topic and analysis is still considered complex, and is poorly understood [30]. In [31] a variable switching frequency control method is proposed to address the low input voltage range and high conduction loss issue in a discontinuous conduction mode ( DCM ) fly-back micro-inverter. This technique is again more preferable for grid connected inverter system, focuses on reducing the conduction loss in order to improve the overall efficiency and the output current is reduced significantly. Also, in this technique switching frequency is in the range of 40kHz to 100kHz and operates within a range of 260W to 80W. 23

35 2.7 Chapter Summary Based on the literature review, it can be concluded that the techniques investigated so far for improving inverter efficiency at low power are mostly done at power levels higher than those of interest here, have complex and expensive control circuitry, and are applicable for high switching frequency applications. As the proposed inverter is not connected to the grid some techniques are not suitable. At low power, switching losses dominate all other losses in the inverter system and it has been demonstrated that switching loss is a function of inverter switching frequency [32]. Therefore, the technique proposed in this thesis to improve inverter efficiency at low power by reducing switching frequency is a simple and appropriate solution for a stand-alone solar home system with light load household appliances. 24

36 Chapter Three: Inverter Loss Model and Design Considerations 3.1 Introduction To reduce switching loss at low power levels for a single phase SPWM stand-alone inverter, the switching frequency is reduced [78]. Decreasing the switching frequency to improve the overall inverter efficiency is possibly the simplest of all the techniques. The objective of this thesis is to design a 200W inverter which is capable of performing at about 85% efficiency even when operated at 9W (4.5% of its rated power). The proposed design does not include a filter, to reduce the cost and to keep the design simple. The critical design aspect considered in this context is to allow distortion of the load current without hampering operation (such as a CFL light or cell phone charger) at lower switching frequency. During mathematical modelling, the switching frequency is varied from 20kHz to 200Hz to observe the change in inverter efficiency. The maximum efficiency at low power is found by dividing the output power by input power at 200Hz which is the minimum switching frequency in this context. While operating at low switching frequency the load has to deal with higher total harmonic distortion of the inverter output current and voltage waveforms which results in low power quality at the inverter output. Hence, it is suggested here that a reduction in switching frequency at low power levels and some degradation in power quality, may result in a significant improvement in inverter efficiency at low power levels. 25

37 3.2 Full Voltage Design and Scaled Down Design In this thesis two inverter designs are considered. The full voltage design is rated for 200W power output. The intended application is in a rural home in the developing world. Many countries have a 220V RMS AC standard at 50Hz. This is the standard used in this thesis. For a 200W power output, a 220V RMS sinusoidal voltage has a peak value of 2x220V=311V. For the 200W design, an 80% modulation index is chosen (in case the DC supply drops, the modulation index can be increased to compensate for the drop). Thus the nominal dc supply voltage is 311V/0.80 = 389V. The next step is to find the RMS output current when the inverter is operating in the heavy load and light load scenarios. The formula for calculating the RMS output current of the inverter is, I Output_RMS = P Output / (V RMS PF). Thus, the RMS current output of the inverter output at heavy load is, 200W/(220V*0.8) = 1.136A, where, the output power is 200W, the RMS output voltage is 220V and the power factor is 0.8 (corresponding to an inductive household load, e.g. table fan, small refrigerator, sewing machine or combination of these). Similarly, the RMS current output of the inverter output at light load is, 9W/(220V*0.65) = 62.9mA, where, the output power is 9W, the RMS output voltage is 220V and the power factor is The reason for choosing a smaller power factor for light load scenario (e.g. 9W CFL) is explained in section of Chapter 5. The experimental implementation of the inverter is based on a scaled down version of the 200W design (for quicker implementation). This scaled down design is based on a dc supply voltage of 25V (available from a lab power supply). Thus, for a modulation index of 80%, the peak of the sinusoidal output voltage is 25Vx0.80 = 20V, giving a RMS output voltage of 20V/ 2 = V. 26

38 The output current rating for the scaled down design is kept equal to that of the full-voltage design. For the heavy load scenario where the rated power is W (i.e. 200W x scaling factor, where the scaling factor is 20V/ 2V / 220V = ) and the RMS output voltage is V, given a modulation index of 0.8, the RMS current rating is W/(14.142V*0.8) = 1.136A (as expected, since voltage is scaled but current is not). For the light load scenario where the output power is W (i.e. 4.5% of W) and the RMS output voltage is V, given a modulation index of 0.65, the RMS current rating is W/(14.142V*0.65) = A or, 62.9mA (again, as expected). The detailed explanation of the reasons behind using a lower power factor (0.65) for light load (CFL) is explained in section of Chapter 5. As mentioned before, although the RMS voltage has been scaled down from 220V to V, the RMS current values (i.e A for heavy load and 62.9mA for light load) and power factors (i.e. 08 for heavy load and 0.65 for light load) are maintained to be the same for the full voltage design and the scaled down version. 3.3 Proposed Inverter Topology As shown in Figure 3.1 a hard switched unipolar SPWM single phase full bridge inverter was simulated and a prototype of the proposed inverter was built. A hard switched inverter is appropriate in this context because of its inexpensive implementation, simple control circuitry and ease of maintenance [33]. Unipolar SPWM has been chosen as the modulation technique because the inverter does not have any filter and unipolar SPWM can better approximate a sinusoid compared to the case of bipolar SPWM [20]. The full bridge topology is chosen with considerations that it must be capable of delivering high current at low voltage. This high current 27

39 at low voltage property is important if the inverter is designed for photovoltaic applications [34]. The standard for output current THD (<100%) is maintained for both rated and light load conditions [35]. Vdc IGBT gate Drive Optocoupler A+ A- io A VAB Load B B+ B- IGBT gate Drive Optocoupler IGBT gate Drive Optocoupler IGBT gate Drive Optocoupler Controller Figure 3.1 Block Diagram of Inverter System Including Controller 3.4 Inverter Loss Components based on Loss Model Evaluating the losses associated with the inverter provides a clearer idea of the reasons behind the reduction of the inverter efficiency at low power levels. Here a detailed mathematical analysis of the losses in the SPWM inverter is made. Based on these equations for estimating the various 28

40 losses in the inverter, efficiency at light load and heavy load while varying the switching frequency from 200Hz up to 20kHz can be calculated. Typically, two thirds of the power loss in a hard switched inverter is the result of conduction and switching losses in the inverter devices [32], [36]. Conduction losses occur due to the on-state voltage across the device as well as the current flow through the device while it is conducting current. More precisely, conduction losses occur between the end of the turn-on transition and the beginning of the turn-off transition [36]. An effective model of conduction losses includes the effect of device on-voltage and conduction resistance [37]. Switching losses arise from the transient situation where both device voltage and current are changing as the device is turning on or turning off [38], [39]. Evaluation of the conduction and switching losses can be done using simplified device models described in [40], [41] and [42]. However, there are also other losses associated with inverter operation. These include gate driver circuit loss, control circuit loss and losses due to snubber circuits. The gate drive circuit losses have been calculated but it is observed that they contribute a very small amount of the total loss. The snubber circuit loss and the control circuit losses have been ignored while developing the overall loss model given that they contribute to a very minimal amount of loss compared to switching loss and conduction loss. 29

41 3.4.1 Conduction Losses To evaluate the conduction loss through a simplified model which is appropriate for both IGBT and diodes, the device is simplified as a constant voltage drop in series with a linear resistor [42]. The on-state voltage of an IGBT and a diode can be calculated using an IGBT datasheet. During the time that the IGBT is on, the collector to emitter voltage, v ce, is given by v ce = V q + i q R q (3.1) The same approximation can be used for the anti-parallel diode, giving v ak = V d + i d R d (3.2) Here, voltage source V q represents the IGBT on-state zero-current collector-emitter voltage and R q stands for collector to emitter on-state resistance. Similarly, V d denotes on-state zero-instantaneous current forward voltage for the antiparallel diode and R d stands for diode on-state resistance. i q and i d are the currents flowing through the IGBT and diode respectively. The parameters V q, R q, V d and R d can be estimated directly from the component datasheets [40]. Figure 3.2 to 3.5 show the derivation of the parameters using datasheet information. Note in [41] that a log-log plot of current vs. voltage is used to obtain the parameters, but is it suggested here that linear scales provide more accurate parameter estimation related to the expected operating 30

42 conditions of the inverter transistors. As mentioned before, the rated RMS output current is 1.136A and for a 4.5% load the corresponding output current is 62.9mA. Figure 3.2 and Figure 3.3 show the derivation of the v q, R q, v d and R d parameters when the transistor (IGBT) is operating under rated load conditions. Figure 3.4 and Figure 3.5 show the derivation of the v q, R q, v d and R d parameters when the transistor is operating under light load conditions. Figure 3.2 IGBT V ce and R q (where, R q = V ce i q ) at Rated Load Condition; note that points plotted here are taken from the Device Datasheet Figure 3.3 Diode V d and R d (where, R d = V ak ) at Rated Load Condition; note that points id plotted here are taken from the Device Datasheet 31

43 Figure 3.4 IGBT V ce and R q (where, R q = V ce i q ) at Light Load Condition; note that points plotted here are taken from the Device Datasheet Figure 3.5 Diode V d and R d (where, R d = V ak ) at Rated Load Condition; note that points id plotted here are taken from the Device Datasheet 32

44 To simplify the calculation of the device average and RMS currents, the load current is assumed to be sinusoidal. Power dissipated in a component with a constant voltage drop is the average current times the voltage drop [40]. The RMS current squared times the resistance signifies the power dissipated in a resistor. The average and RMS currents of the IGBT and diode in an inverter (given sinusoidal pulse width modulation) are [40] I q = I o (pk) [ 1 + m a cos 2π 8 ] (3.3) I q(rms) = I o (pk) m a cos 3π (3.4) I d = I o (pk) [ 1 m a cos 2π 8 ] (3.5) I d(rms) = I o (pk) 1 8 m a cos 3π (3.6) Here, I o (pk) denotes the peak load current, denotes the load power factor angle, m a the modulation index, I q, I d denote the average currents and I q(rms), I d(rms) denote RMS currents flowing through the IGBT and the antiparallel diode [40]. The conduction losses in the IGBT, P q con and diode, P d con are obtained using [40], [41]. P q con = V q I q + R q I q(rms) 2 (3.7) 33

45 P d con = V d I d R d I d(rms) 2 (3.8) The total conduction losses, P tot con of the four IGBTs along with their anti-parallel diodes can be calculated from P tot con = 4(P q con + P d con ) (3.9) The total conduction loss associated with the inverter is found easily using equation (3.9). Equation (3.9) shows that the conduction losses depend on the load conditions [41], [42], [43], [44] Switching Losses In power inverters, switching loss typically contributes significantly to the total system losses. The switching loss in the IGBT depends on the IGBT and diode's dynamic characteristics [45]. Three components of the switching losses in the hard switching inverter can be identified: IGBT turn on losses, IGBT turn off losses, and the losses due to diode reverse recovery. During turn-on, the semiconductor is exposed to a high current peak as a consequence of the reverse recovery of the freewheeling diode. At the same time the collector-emitter voltage is still high, thus causing high switching losses. During turn-off, the losses can be even higher due to the long collector current tail [44]. So, the turn-on losses are due to the rate of current change and the stored charge in the free wheel diode. On the other hand, the turn-off losses depend on the speed of the gate drive and the IGBT's current tail due to the recombination of minority carriers [46]. The semiconductor is 34

46 said to be hard switching under these conditions of simultaneous high current and high voltage during the switching transient. Evaluation of the switching losses, in the hard switching inverter consisting of four 15A, 600V IGBT and ultrafast soft recovery diodes, can be done using the measured values of switching energy from the data sheets. Generally, datasheets provide the values of turn-on and turn-off energy (E on and E off ) for a conventional test voltage and current (V test and I test ). The calculated values of turn-on energy comprise the losses due to diode reverse recovery and tail current losses. The total energy loss during turn on and turn off transients of the switch, E tot, can be calculated based on [40] using E tot = K g (E on + E off ) V s V test I o (pk) I test (3.10) Equation (3.10) represents V s as the bus voltage, I o (pk) as the peak load current and K g as the correction factor to account for the gate drive impedance. The total switching losses, P tot sw, of the proposed inverter can found using P tot sw = 4f sw E tot π (3.11) Here, f sw denotes the SPWM switching frequency [43, 44]. Evidently, the switching losses in the hard switching inverter are directly proportional to the switching frequency. Further, from equation (3.11) the switching energy is proportional to the voltage across the device during switching, so 35

47 the losses can be eliminated if the voltage across the device is zero during the switching. This kind of switching technique is called soft-switching or zero voltage switching (described in section 2.6) but the added components will result in cost and reliability penalties [47] IGBT Gate Drive Losses IGBTs are voltage controlled devices and require a gate voltage to establish conduction between collector and emitter. To provide the gate voltage, the FOD3184-ND is used as the gate drive optocoupler. The total gate driver power loss can be derived from the summation of the total power dissipated for the emitter (P emitter ), internal circuitry (P emitter ) and the output ( P output ) of the IGBT driver IC [48]: P gate driver(tot) = P output + P emitter + P internal (3.12) IGBT total gate capacitance, C gate, is the total gate charge Q gate divided by the gate drive supply voltage V GE [48]. C gate = Q gate V GE (3.13) This means that the charging and discharging the IGBT gate is equivalent to the charging and discharging a capacitor. Hence the power dissipated for the output of the IGBT driver IC can be defined by 36

48 P output = C gate V GE 2 f sw (3.14) Where, f sw is the switching frequency. The power dissipated in the IGBT driver emitter can be derived from the diode forward current I F, maximum diode duty cycle D and diode forward voltage V F [48]: P emitter = I F V F D (3.15) Finally, the power dissipated in the IGBT driver internal circuitry depends on I CC, the collector current, and the collector to emitter voltage (V CC V EE ). Note the collector to emitter voltage can be any value between a minimum of -0.5V and a maximum of the device peak forward rating. Thus P internal = I CC (V CC V EE ) (3.16) 3.5 Inverter Efficiency Calculation Using equation (3.9) for conduction loss, equation (3.11) for switching loss and equation (3.12) for gate drive loss, the different loss components of the proposed inverter at different load and switching frequency conditions are calculated. Shown in Table 3.1 are the results for the proposed inverter system (the topology is shown in Figure 3.1, and system details are provided in Chapter 4). The table shows a decrease in switching and drive circuit loss for each load condition 37

49 when the switching frequency is decreased. Whereas, as shown in Table 3.2 the improvement in the inverter efficiency in relation to the decrease in the switching frequency suggests that reduction of switching frequency results in significant inverter efficiency improvement especially at low power. The results of the proposed inverter loss model is presented for the full voltage design and also for the low voltage scaled down design. Table 3.1 Power Loss Calculation under Different Load Conditions for Variable Switching Frequency (for Vdc, Rated Power 200W) Load Switching Frequency Conduction Loss Switching Loss Drive Loss (khz) (W) (W) (W) Full Load (200W) Light Load (9W)

50 Table 3.2 Efficiency under Different Load Conditions for Variable Switching Frequency (for Vdc, Rated Power 200W) Load Switching Frequency Output Power Total Loss Input Power Efficiency (khz) (W) (W) (W) (%) Full Load (200W) Light Load (9W) The efficiency (η) calculated above is the reference for simulation and experimental implementation of the proposed inverter. Ideally, inverter output power should be equal to the inverter input power given that there is no loss in the ideal inverter system. Practically, there are always some losses in the inverter system and input power can be expressed as sum of output power and total loss. The basic formula for calculating inverter efficiency is, η = Output Power/ Input Power. Considering inverter loss explicitly, the formula can be re-written as, η = Output Power/ (Output Power + Total Loss). For example for 2.5kHz, the output 39

51 power is 200W, the total losses are 4.046W so the input power is now, W, thus the efficiency is, η = 200/ ( ) = 98.02%. The efficiency calculations in Table 3.4 in the last column is also done in the same way as with the sample calculation for 2.5kHz. The trend of an increase in inverter efficiency with decreasing switching frequency is evident from the efficiency calculations (Table 3.2). For example, inverter efficiency for 9W is 79.27% when operated at 20kHz and 95.75% when operated at 200Hz. Interestingly the inverter efficiency does not change dramatically as the switching frequency changes from 2.5kHz to 200HZ (i.e % to 95.75% for 200W in Table 3.2). The inverter loss model analysis based on different loss components is done for an inverter circuit operating with a sinusoidal output current (i.e. no harmonic distortion). Harmonic distortion, spikes, and controller losses are circuit specific characteristics and cannot be modeled accurately without observing implemented inverter circuit characteristics. To obtain the values of the equation parameters (v q, r q, v d, r d in Equation. 3.1, 3.2), the datasheet graphs (log-log scale) have been linearized (Figure 3.2, 3.3, 3.4, 3.5) to approximate required parameters. Since a scaled down version (12.856W) of the full voltage design (200W) was implemented experimentally, a similar kind of loss model analysis and efficiency calculation is performed for the scaled down version as shown in Table 3.3 and Table

52 Table 3.3 Power Loss Calculation under Different Load Conditions for Variable Switching Frequency (for 25Vdc, Rated Power W) Load Switching Frequency Conduction Loss Switching Loss Drive Loss (khz) (W) (W) (W) Full Load (12.856W) (0.578W)

53 Table 3.4 Efficiency under Different Load Conditions for Variable Switching Frequency (for 25Vdc, Rated Power W) Load Switching Frequency Output Power Total Loss Input Power Efficiency (khz) (W) (W) (W) (%) Full Load (12.856W) Light Load (0.578W) Similar to the full voltage design, Table 3.4 shows an increase in efficiency as the switching frequency is decreased for the scaled down design. For example, inverter efficiency for 0.578W is 34.80% when operated at 20kHz and 75.16% when operated at 200Hz. 42

54 The results found from the mathematical analysis above, show that as the switching frequency decreases, the losses in the inverter circuit decrease. As seen, this can be attributed to the change in switching losses, unlike conduction and drive losses that remain nearly constant for a given load condition. 3.6 Chapter Summary A detailed mathematical analysis of the losses in the inverter circuit is presented in this chapter. An inverter loss model is applied to show how reducing switching frequency improves the inverter efficiency. The loss model gives information about how the transistor switching losses impact inverter efficiency when the power level drops. 43

55 Chapter Four: Simulation Results for Proposed Full Bridge Inverter 4.1 Schematic of the Full Bridge Inverter System under Study Before going to a practical circuit implementation, the simulation of the inverter circuit is performed in OrCAD PSpice. PSpice is a computer simulation program that models the behavior of an electrical circuit containing analog devices. PSpice is often chosen by design engineers for its ability to simulate practical load characteristics. It is essentially a computer based breadboard which allows prediction of AC and DC steady state waveforms and to perform transient analysis. The simulation results from the PSpice inverter circuit model can be compared with the mathematical model and with the experimental data. By verifying the PSpice model against experimental data and the mathematical model, parametric studies of the inverter efficiency at reduced switching frequency at low power may be conducted confidently. In PSpice, the practical model of the IGBT can be used for the hardware circuit analysis and sinusoidal pulse width modulation (SPWM) can be simulated in the control. Using the practical model of IGBT (IRG4BC20UD) is useful and significant to observe the impact of switching loss associated with switching frequency on the inverter efficiency. Also, the equivalent simplified PSpice models of the heavy load and light load conditions help to predict the overall efficiency outcome of the simulated inverter before going to hardware circuit analysis. To observe the impact of decreasing switching frequency on the inverter efficiency, switching frequency is varied over a range of 20kHz to as low as 200Hz. This wide frequency range is useful to observe the change in inverter efficiency as one goes from higher to lower frequency for heavy load and light load conditions. The inverter system under study is shown in Figure 3.1 in Chapter 3 and also in Appendix A. 44

56 4.2 Simulation Circuit Description The inverter circuit simulated in PSpice is a Voltage Source SPWM inverter. The simplest dc voltage source for Voltage Source Inverter (VSI) consists of a battery bank [49]. The battery bank usually consists of several batteries in series and/or parallel combination. Solar Photovoltaic cells can also be employed to create the dc voltage source [50]. The proposed inverter is simulated in PSpice for the full voltage design and also simulated for the low voltage scaled down design SPWM Controller The number of pulses per half cycle is typically on the order of 100 pulses. As discussed earlier in section 2.5, because of the advantages specific to the proposed inverter, unipolar SPWM is selected as the suitable switching technique. Choosing the optimum switching technique for the IGBT switching is an important design consideration for the proposed inverter. The PSpice schematic shown in Figure 4.1 generates SPWM control signals. The sinusoidal signal generator produces, a sinusoidal pulse signal V Control at a frequency of f Control. The control frequency, f Control is equal to the output frequency f o (i.e. 50HZ) of the output voltage V o [39]. The modulation index m a is set to be 0.8. The control signal, V Control is then rectified through a precision rectifier in order to implement unipolar SPWM topology (discussed in detail in section ). 45

57 ABS IF(V(%IN1)-V(%IN2)>0, 1, 0) Comparator g1 1-V(%IN) Inverter g4 + _ + _ Vcontrol + _ Vcarrier Vx 1-V(%IN) Inverter Vy g3 1-V(%IN) Inverter g2 0 Figure 4.1 Schematic of Controller for Generating SPWM Gating Signals as used in PSpice Simulations The triangular wave generator generates the carrier signal V carrier at the switching frequency of f sw. The switching frequency, f sw = 2Nf o, where N is the number of switching angles per quarter cycle [50]. The switching frequency f sw controls the speed at which the inverter switches are turned on and turned off. In this thesis, the switching frequency is varied in a range of 20kHz to 200Hz. The change in switching frequency is made by changing the value of N as the output frequency, f o is fixed at 50Hz. Once the two signals are generated (V Control and V Carrier ) the four gating pulses are generated by comparing the triangular signal, V Carrier with the absolute of the sinusoidal signal, V Control [51]. The four gating signals as shown in Figure 4.2 is then applied to the four IGBT gates of the full bridge inverter in order to create desired AC signal at the inverter output. 46

58 Figure 4.2 Simulated Waveforms for SPWM with Unipolar voltage switching (a) Sinusoidal Reference waveform and Triangular Carrier waveform, (b), (c),(d),(e) gating pulses for A +, A, B + and B respectively after Sine and Triangular comparison (Total Time Interval = 20ms, 1ms time division (horizontally), 5V voltage division (Vertically)) Gate Drive Circuit It is customary to protect the IGBTs power devices used in the inverter so that they can continue to function despite somewhat unpredictable conditions that characterize the renewable energy scenarios. In particular, designers build in protection to avoid damage resulting from conditions such as under voltage, over voltage, short circuits etc. [52]. An optocoupler is often used in IGBT gate drive circuitry to isolate the controller part from the rest of the circuit. The optocoupler output diode is connected to a totem-pole pair of BJT devices as shown in Figure B-3 (Appendix B) to provide fast switching of the IGBT (note that an isolated 47

59 + supply is needed for the totem-pole pair). In a PSpice simulation the optocoupler and totem-pole arrangement is modelled using a Gain Circuit, also called an E Block, as shown in Figure 4.3 (a). Within the PSpice Gain Circuit is an isolation op-amp circuit, illustrated in Figure 4.3 (b). Shown in Figure 4.3 (c) is a model of the internal op-amp structure. The main characteristics of an op amp are very high input resistance (R 1 ), very low output resistance (R O ) and very high gain (A is on the order of 10 5 ). Note that a gate drive circuit must be able to provide a voltage of 15V to 20V between gate and source of the IGBT, to ensure that the IGBT is fully on and in a state of low conductance [53]. Vn Vp _ + (a) Vo Vn Vp R1 Ro (b) A(Vp-Vn) Vo Vn Vp R2 + _ E + + A(Vp-Vn) (c) Ro Vo Figure 4.3 PSpice Modelling of IGBT Gate Drive Circuit. (a) PSpice Gain Circuit which is also called an E Block (b) Op Amp Symbol (c) Op Amp model IGBT Switching Circuit In order to generate a modified sine wave at the inverter output V AB requires both a positive and negative voltage across the load, for the positive and negative parts of the wave respectively [54]. A modified sine wave as shown in Figure 4.4 at the output of the inverter can be achieved from a 48

60 single source through the use of four IGBT switches arranged in an H-Bridge configuration as shown in Figure 4.1. In order to minimize power loss and utilize higher switching speeds, N- Channel IGBTs were chosen as switches in the H-bridge inverter circuit. Figure 4.4 Simulated Output Voltage Waveform of the Inverter at 2.5kHz for SPWM with the Unipolar Switching (Total Time Interval = 20ms, 1ms Time Division (Horizontally), 50V Voltage Division (Vertically)) The top two IGBT switches (IRG4BC20UD) are A + and A while the bottom switches are B + and B (shown in Figure 3.1) each co-packaged with HEXFREDTM ultrafast, ultra- soft-recovery anti-parallel diodes for the use in H-bridge configurations [Appendix B]. The anti-parallel diodes provide an alternate path for the load current if any of the power switches are turned off. For example, if the lower IGBT ( B ) in the left leg is conducting and carrying current towards the negative dc bus, this current would regulate or commutate into the diode across the upper IGBT ( B + ) of the left. In order to avoid a short circuit of the DC bus, both IGBTs of the same leg can never be conducting at the same time. In the unipolar SPWM switching scheme the output voltage 49

61 of the inverter swings from 0 to +Vdc and 0 to Vdc as shown in Figure 4.5. In the proposed inverter switching scheme, when the switches A + and B are kept on, the output voltage across the load is equal to +Vdc (311V). When A and B + are turned on, then at that time the output voltage is equal to Vdc (-311V) [19]. The logic behind the switching of the devices in the leg connected to A and B is given in Table 4.1, Table 4.1 Unipolar SPWM Switching Logic Switching Logic Switch On State Voltage V Control > V Carrier A + V AN = +( Vdc 2 ) V Control < V Carrier B V BN = -( Vdc 2 ) V Control > V Carrier A V BN = +( Vdc 2 ) V Control < V Carrier B + V AN = -( Vdc 2 ) Here, V control is denoted as the voltage of the reference signal in negative half cycle [19]. The operating principle of the full bridge inverter is similar to the half bridge inverter except a half bridge inverter has only one switching device so that only the positive part of the sine wave can get through the inverter. On the contrary, the single phase full bridge inverter has four switching devices but instead of just clipping off half the wave it reverses the polarity of half the wave, thereby increasing the efficiency and doubling the frequency [33]. 50

62 4.2 Different Load Conditions At rated power, in a rural typical household, loads such as a table fan, a refrigerator, a sewing machine and lights could all be operating at the same time. However, there are situations where the total load can be quite light, for example, at night only a single CFL (compact florescent lamp) and/or a single cell phone charger. To represent light loads, an equivalent model of the Compact Fluorescent Lamp (CFL) has been simulated in PSpice. Typically, CFLs have two main components: a magnetic or electronic ballast and a gas-filled tube (also called bulb or burner). Modern electronic ballasts contain a small circuit board with rectifiers, a filter capacitor and usually two switching transistors [55], [56]. The incoming AC current is first rectified to DC, then converted to high frequency AC by the transistors, connected as a resonant series DC to AC inverter. The resulting high frequency is applied to the lamp tube [57]. In the proposed inverter, only the ballast stage of the CFL consisting of a rectifier circuit and a parallel RC circuit is simulated in PSpice. The simplified equivalent PSpice model as shown in Figure 4.5 is useful for observing the nonlinear behavior [58], [59] of the 9W CFL as shown in Figure 4.6 and Figure 4.7. In particular, the harmonic limits applied to the CFLs are less stringent compared to LED (Light Emitting Diode) lighting [60], [61], [6] and [7]. CFL lighting, even with high THD (<100%), is still used in rural locations [62]. 51

63 D1 D1N3940 D3 D1N3940 Cdc 0.7 uf Rload 5.315kΩ Inverter Block Vsystem = 220VRMS Frequency= 50hz D2 D1N3940 D4 D1N3940 Figure 4.5 Schematic of Equivalent Circuit of CFL Model connected as a load at the inverter output As shown in Figure 4.6, the passive front-end single-phase diode bridge rectifier is the standard circuit for converting AC to DC. The rectifier stage in a CFL circuit has four rectifier diodes. In this case, D1N3940 is used in the rectifier circuit which is commonly used in full bridge rectifier circuits for CFL for its low forward voltage of 1V for a maximum forward current of 10 ma. This circuit operates by first rectifying the single-phase input ac system voltage, V system (e.g. 220V RMS), or rectifying the voltage delivered at the output of the inverter circuit, to produce a positive cycle voltage waveform, V rect, at twice the system frequency (i.e. 100Hz compared to system frequency 50Hz). This voltage is then applied to the load capacitor, C dc. When V rect is greater than Vdc, the load capacitor will start to charge and draw current from the inverter. At this point, as there is no inductance present in the charging circuit, the dc current of the charging circuit I dc would cease instantaneously. During the time it takes I C to reach zero, Vdc will continue to increase. Thus, the charging and discharging process results in non-linear operation of the bridge rectifier circuit [60]. The diode bridge rectifier at the front end of the electronic ballast influences 52

64 that the CFLs draw non-linear current from the supply [60]. The charging state of the CFL load circuit can be represented by a RC circuit driven by the rectified system voltage, V rect [61]. In Chapter 4, the light load is considered to be a 9W CFL and the heavy load is considered to be a load model of 200W combined heavy loads. However, in the experimental setup, the output power for both cases (heavy and light) is scaled down to W and 0.578W respectively for a 25Vdc supply input for practical reasons (discussed in detail in section 3.2). The CFL model parameters were chosen in a way so that the power rating of the CFL can be maintained at 9W. The set of equations to calculate the load circuit parameters is shown in section 5.3 of Chapter 5 for the scaled down version. The full voltage design parameters are also calculated in the same manner using the same set of equations except the supply voltage is different than the scaled down version. After connecting the equivalent CFL model as a load at the inverter output, the current and voltage waveform as shown in Figure 4.6 and Figure 4.7 was observed. 53

65 Figure 4.6 Simulated Current Waveform from the Equivalent Circuit of CFL Model connected as a Load at the Inverter output (Total Time Interval = 30ms, 1ms time division (horizontally), 10mA current division (Vertically)) Figure 4.7 Simulated Voltage Waveform from the Equivalent Circuit of CFL Model connected as a load at the inverter output (Total Time Interval = 20ms, 1ms time division (horizontally), 50V voltage division (Vertically)) To observe the inverter efficiency at rated power (200W) along with the change in frequency an equivalent model of the heavy load is simulated in PSpice. In the heavy load simulation an inductive-resistive load as shown in Figure 4.8 was used. 54

66 Inverter Block Vsystem = 220VRMS fsystem = 50hz L H Rload Ω Figure 4.8 Schematic of Equivalent Circuit of CFL Model connected as a load at the inverter output When the inverter is connected to an inductive-resistive load, the anti-parallel diode of the IGBT helps the IGBT to perform as a fully functional switch. The antiparallel diode connected to the IGBT provides suitable reverse current for the inductive load. The current and voltage waveform shown in Figure 4.9 and Figure 4.10 represent typical heavy load characteristics. Figure 4.9 Simulated Current Waveform from the Equivalent Circuit of Heavy Load Model connected as a load at the inverter output (Total Time Interval = 30ms, 1ms time division (horizontally), 1A current division (Vertically)) 55

67 Note that, as shown in the above Figure 4.10, the inverter output current waveform operates (heavy load condition) in a transient state during approximately the first 10ms and reaches almost steady state after 10ms of its operation period (the LR time constant of the load is 2.40ms). Figure 4.10 Simulated Voltage Waveform from the Equivalent Circuit of Heavy Load Model connected as a load at the inverter output (Total Time Interval = 20ms, 1ms time division (horizontally), 50V voltage division (Vertically)) 4.3 Simulation Results To observe the trend of improved inverter efficiency along with decrease in switching frequency, the proposed inverter has been simulated for the full voltage design and also for the scaled down low voltage design (discussed in detail in section 3.2). For both cases (full voltage design and the scaled down version) simulation results of the PSpice inverter under different load conditions and variable switching frequencies are presented in Table 4.2 and Table

68 Table 4.2 Simulation Results Under Different Load Conditions For Variable Switching Frequency (For Vdc) Load Switching Frequency Output Power Total Loss Input Power Efficiency (khz) (W) (W) (W) (%) Full Load (200W) Light Load (9W) The efficiency calculated shows an increasing trend as the switching frequency decreases from 20kHz to 200Hz. The change in efficiency is more evident at the light load scenario when only a 9W CFL is connected at the inverter output. As shown in the fourth column of the above table, Table 4.2, the efficiency is 63.96% for 20kHz and the efficiency for the given constant load changes into 86.64% when the inverter is operating at a switching frequency of 200Hz. The efficiency of the simulated inverter is calculated using the same efficiency equation (Efficiency = 57

69 Output Power/ Input Power, where, Input Power = Output Power+ Total Loss) described in section 3.5 of Chapter 3. Table 4.3 Simulation Results Under Different Load Conditions For Variable Switching Frequency (For 25Vdc) Load Switching Frequency Output Power Total Loss Input Power Efficiency (khz) (W) (W) (W) (%) Heavy Load (12.856W) Light Load (0.578W) The efficiency calculations as shown above show an increasing trend even for a very low power level of 0.578W (from 34% to 65.98%). As shown in Table 4.3, for both cases (heavy load and 58

70 light load) an additional switching frequency of 5kHz is added between the switching frequencies 10kHz and 2.5kHz. The significance of adding an additional switching frequency in the efficiency calculation table is that, while implementing the experimental inverter prototype, the switching frequencies were maintained within a close range, where the highest switching frequency was 5kHz and lowest was 200Hz with a 2.5kHz switching frequency in between. Thus, while comparing the mathematical analysis, simulation and experimental efficiency results of the inverter, the comparison can be done for all the three switching frequency levels (e.g. 5kHz, 2.5kHz, 200kHz). The reason behind keeping the switching frequencies within a close range for the scaled down version from 5kHz to 200Hz is that the same snubber circuit was used for varying switching frequencies for practical purposes (c.f. section 5.2.6). The reason for ignoring the higher switching frequencies (e.g. 10kHz and 20KHz) is that at very low power (e.g W) where the output current is very small (e.g. 62.9mA RMS), the current waveform becomes excessively distorted by the effect of electromagnetic interference caused by the higher switching frequencies. The result was overheating of the transistors. In order to correct this problem, the snubber would have needed to be re-designed which is not done in practice (the snubber components are usually fixed values). A Fourier analysis of the output current is performed in PSpice for both full load and light load conditions. Based on the analysis, Total Harmonic Distortion (THD) is observed for both conditions. For full load it is observed that the output current is a near-sinusoidal waveform with total harmonic distortion of around 17.50% for the lowest switching frequency of 200Hz. The THD of the output current at 200Hz which is 17.50% is within the acceptable range of 20% for household appliances for stand-alone solar home systems [6]. When considering a CFL as a load 59

71 for the inverter, the output current has a higher total harmonic distortion of 57.14% for a switching frequency of 200Hz which is also acceptable (<100%) for non-linear loads like a CFL which produces a high current THD factor [35], [61], [62], [63] and [64]. 4.4 Chapter Summary Presented in this chapter is the inverter simulation model. The model consists of a dc power supply, controller circuit, gate drive circuit, switching circuit implemented for heavy and light load conditions. Simulation results support the results from the mathematical analysis of the previous chapter. Hence, suggests that reducing the switching frequency at low power decreases the switching loss, thus increasing efficiency for the same load. The THD of the output current of the inverter under heavy load and light load meet the stand-alone solar home THD requirements [6], [35]. Hardware implementation can be conducted confidently based on the design considerations and analysis of results obtained from the PSpice simulation of the proposed inverter circuit. The gate drive circuit losses did not reduce the inverter efficiency significantly as was found in the mathematical analysis. The results found from the loss model developed in Chapter 3 and the results obtained from the simulations shows agreement in the efficiency trend. The mathematical loss model is useful to observe the increasing efficiency trend but it is extremely important to simulate the inverter through PSpice before going to practical implementation. The PSpice simulation platform is useful to verify that the individual components work well together in order to provide useful AC at the inverter output. 60

72 Chapter Five: Experimental Results 5.1 Introduction The experimental verification of the proposed single phase full bridge SPWM inverter to improve inverter efficiency at low power is described and discussed in this chapter. A prototype of the inverter circuit was built on a breadboard which is then controlled by the MSP-430 microcontroller that includes a PC interface for programming purposes. This chapter has two main parts. Section 5.2 to 5.3 provide a description of the hardware components and the process to select component values. These components are: the control circuit for generating switching signals, the isolation circuit, the gate drive circuit, and the snubber circuit. Calculations are provided for snubber component values, load component values and current sense resistor values. In the second part of this chapter, the experimental results are presented, which are compared with the simulation results of Chapter 4 as well as the mathematical results of Chapter 3. The 25Vdc dual mode DC power supply voltage was applied to the inverter in order to simplify the experimental work instead of high voltage (389.98Vdc). The mathematical loss model in Chapter 3 and the PSpice model in Chapter 4, discusses both the full voltage and the scaled down versions. However, this chapter only includes the low voltage design (i.e. the scaled down version at W rated power) which was implemented experimentally in the lab set-up. 61

73 5.2 Hardware Overview Figure 5.1 is a partial circuit diagram of the inverter (only the gating lines are shown of the MSP430 microcontroller). The dual mode DC power supply provides a constant 5V dc voltage to the DC-DC converters. Each DC-DC converter in turn provides a constant 15V supply to each optocoupler. There are four optocouplers in the inverter circuit and each of them needs an isolated power supply otherwise transistor gate inputs become shorted. The four DC-DC converters provide the isolated power supply to each of the optocoupler ICs which provides isolation between a microprocessor gating line and the IGBT transistor gate. The output of the optocoupler is connected to the IGBTs gate through the gate resistor. As mentioned in the previous section, the 25Vdc dual mode power supply provides the input voltage for the full bridge inverter. This is the input voltage for the experimental inverter circuit (in practice a much larger supply voltage, for example, Vdc is needed in order for the inverter to power 220VAC equipment). Although the supply voltage is a scaled down it is expected that a similar efficiency trend will be observed as would be the case for the full voltage design. Chapter 4 described the full voltage design for generating a 220VAC voltage at the output of the inverter. In section 4.3 the efficiency calculations showed that the inverter efficiency increases with decreasing switching frequency irrespective of the load (heavy or light). The following sections detail how each specific part is constructed and interacts with other parts. The hardware design for this project was divided into four main blocks (a) Power supply for transistor drive circuit; (b) Isolation circuit for each transistor; (c) Full bridge inverter circuit and (d) Snubber circuit for each transistor. 62

74 The MSP430 was used to generate four gating pulses. The MSP430G2553 is an ultra-low power, mixed signal microcontroller with built-in 16-bit timers. There are up to 24 I/O capacitive-touch enabled pins, a versatile analog comparator and a 10-bit analog-to-digital (A/D) converter. Up to seven SPWM signals can be generated with the Timer A of MSP430G2553 [Appendix C]. In Figure 5.1 only four SPWM output pins 2.1, 2.2, 2.4, 2.5 of the MSP430 are shown which has been used to generate four gating pulses [65]. The MSP430 code that is used to generate these four gating pulses is discussed in detail in Appendix D. 63

75 DC Power Supply 5V + _ 25V + COM _ A+ B ohm DC-DC Converter 90 ohm 0.1uF Optocoupler 50 ohm 0.1uF 5.1uF 10 ohm 10 ohm Snubber Circuit 50 ohm 90 ohm Optocoupler 0.1uF 0.1uF 35 ohm DC-DC Converter Load Snubber Circuit A- B DC-DC Converter 1 0.1uF ohm 0.1uF Optocoupler 5.1uF 10 ohm 10 ohm 50 ohm uF 90 ohm uF Optocoupler 35 ohm DC-DC Converter 90 ohm MSP Figure 5.1 Partial Schematic of the Experimental Inverter System The inverter circuit as shown in Figure 5.1 was designed to deliver AC power to the loads used in the households, but is a scaled down version, operating at a reduced voltage to simplify the experimental work. Although it was not possible to run 230VAC equipment with this scaled down version it was possible to investigate the variation in efficiency at different switching frequencies. 64

76 5.2.1 Power Supply for Transistor Drive Circuit The gate drive circuit requires 15Vdc to operate. To provide this voltage, a DC-DC converter circuit was used, The DC-DC converter was NME0515SC which is an isolated 1W single output DC/DC converter [Appendix B]. The output current of the DC-DC converter is 66mA with an input current of 250mA and a conversion efficiency of around 80%. Minimum load to meet datasheet specification which is 10% of the full rated load (1W) across the specified input voltage range was used. Lower than 10% minimum loading will result in an increase in the output voltage, which may rise to typically double the specified output voltage if the output load falls to less than 5%. As per the datasheet, a 0.1uF capacitor was connected in parallel to the converter to remove the noise coming from it and thus protect the overall circuit Isolation Circuit An isolation circuit is needed to protect the microprocessor from the overvoltage damage. The gate to signal isolation for inverter switches is generally achieved by means of optical isolator circuits. As shown in Figure 5.2, the FOD3184 was used as the gate drive optocoupler [Appendix B]. FOD3184 is suitable for high speed IGBT such as IRG4BC20UD which has been used as the switching device in this experiment. The voltage and current supplied by the optocoupler is ideally suited for driving the specific IGBT rated at 600V/6.5A. As shown in Figure 5.2 and in Figure B- 3 [Appendix B] FOD3184 consists of an Aluminum Gallium Arsenide (AlGaAs) light emitting diode optically coupled to CMOS detector with PMOS and NMOS output power transistors integrated circuit power stage. As mentioned earlier a 0.1uF bypass capacitor was required to be 65

77 connected between pins 5 and 8. This 0.1uf capacitor acts in effect like a low pass filter, adding some smoothing to the input signal and bypassing sharp spikes Optocoupler Circuit Operation The input stage of the optocoupler IC is a light emitting diode (LED) that emits light when forward biased. The light output of the LED falls on reverse biased junction of an optical diode as shown in the optocoupler figure. The gate control pulses for the switch are applied to the input LED through a current limiting resistor (R) of appropriate magnitude. These gate pulses, generated by the MSP430 microcontroller, are essentially in the digital form. A high level of the gate signal is an on command and a low level is connected to the ground point of the MSP430 microcontroller ground. The anode is fed with the gating pulse generated by the MSP430. The circuit on the output (photo-diode) side was connected to a floating dc power supply, as shown in Figure 5.2. The control supply ground was isolated from the floating supply ground to the output. The circuit on the output (photo-diode side is connected to a floating dc power supply ground of the output. In the figure the two grounds have been shown by two different symbols. The schematic connection in the figure indicates the magnitude of the reverse leakage current of the diode. When the input signal is high, the LED conducts and the emitted light falls on the reverse biased p-n junction. Irradiation causes generation of significant number of electron-hole pairs in the depletion region of the reverse biased diode. As a result, the magnitude of reverse leakage current of the diode increases appreciably. The resistor connected in series with the photo-diode now has higher voltage drop due to the increased leakage current. The two transistors work together as a signal comparator circuit and senses this condition. The signal comparator then outputs a high level 66

78 signal, which is amplified before being output. Thus an isolated and amplified gate signal is obtained and may directly be connected to the gate terminal of the switch. Power Supply Vdd =15V(Floating) NC 1 8 Vdd Input Pulse R ANODE 2 LED Photo- Diode 7 Vo2 Output CATHODE 3 6 Vo1 NC 4 5 Vss Control Ground Floating Ground Figure 5.2 Internal Circuit of FOD3184 IC In this thesis, FOD3184 optocoupler IC is employed to drive the IGBT. As shown in Figure 5.3 below the FOD3184 optocoupler IC isolates an IGBT from the controller circuit. Each optocoupler requires a 15V isolated DC supply since an IGBT can only be placed in a low conduction state if the gate to source voltage is much greater than the transistor threshold voltage. This 15Vdc is supplied by a DC to DC converter circuit (discussed in section 5.2.1). The optocouplers are controlled by the MSP430 microcontroller unit. 67

79 MSP430 Microcontroller Instructions Oprocoupler IC 15V DC From DC-DC Converter IGBT Drive IGBT Figure 5.3 Block Diagram showing Optocoupler Interface Full Bridge Inverter Circuit The single phase full bridge switching circuit has been shown in Figure 5.1. Thus the single phase full-bridge (often, simply called as bridge ) circuit has two legs of switches, each leg consisting of an upper switch (e.g. A +, B + ) and a lower switch (e.g. A, B ). Junction point of the upper and lower switches is the output point of that particular leg. The emitters and bases of the upper and the lower IGBTs are shorted as shown in the Figure 5.1. An IGBT is turned on and off by the MSP430 microcontroller to produce a high frequency SPWM signal which is later converted to a modified sine wave at the output [Appendix C]. The individual control signal for the switches needs to be provided across the gate and emitter terminals of the particular switch. The gate control signals are low voltage signals referred to the emitter terminal of the switch. For each IGBT switch, when gate to source voltage is more than threshold voltage for turn-on, the switch turns on and when it is less than threshold voltage the switch turns off. In this thesis, IGBT model IRG4BC20UD has been used for switching purposes. The threshold voltage of the specific IGBT is +6V but the turn-on gate voltage magnitude is +15V 68

80 for quicker switching whereas turn-off gate voltage is 0V. The two switches of an inverter-leg are controlled in a complementary manner as shown to generate the AC output of the desired frequency (50 Hz) at the inverter output. As shown in Figure 5.4 when the upper switch of any leg is on, the corresponding lower switch remains off and vice-versa. When a switch is on its emitter and collector terminals are virtually shorted. Thus with upper switch on, the emitter of the upper switch is at positive dc bus potential. Similarly with lower switch on, the emitter of upper switch of that leg is virtually at the negative dc bus potential. Emitters of all the lower switches are shorted with the collectors of the lower switches as shown in Figure 5.1. Since gate control signals are applied with respect to the emitter terminals of the switches, the gate voltages of all the upper switches must be floating with respect to the dc bus line potentials. The emitters of the lower switches of both of the legs are at the same potential (since they are connected to the negative DC bus) and hence the gate control signals of lower switches need not be isolated among themselves. However, there are spikes (with ringing effect) at the output current and output voltage waveform of the inverter caused by the circuit parasitic inductance when a switch opens. To eliminate voltage spikes a snubber circuit has been used which provides an alternate path to ground for the current flowing through the circuit's parasitic inductance. The snubber reduces the voltage transient and damps the subsequent ringing with the parasitic capacitance that occurs when the switch opens. 69

81 5.2.5 Snubber Circuit Snubbers are circuits which are placed across the semiconductor devices (in this case IGBTs) for protection and to improve performance [66]. They are voltage limiting or current limiting devices connected to the power terminals (collector and emitter of an IGBT device). For voltage snubbing, the snubber is connected in parallel with the power transistor to reduce the peak value of voltage switching transients. Snubbers are used to prolong the life of contacts by reducing arcing in semiconductor devices RC Snubber There are many different kinds of snubbers. The two most common ones are the resistor capacitor (RC) damping network and the resistor-capacitor-diode (RCD) turn-off snubber. Figure 5.4 shows the RC snubber circuit is implemented in this thesis, to get rid of the spikes at the output voltage of the inverter circuit [67]. An RC snubber is most commonly used in inverters for both rate-of-rise control and damping. The RC snubber absorbs energy during each voltage transition and can reduce efficiency. Also, the RC snubber can reduce the switching speed of the IGBT switch. Care must be taken in choosing the value of resistor and capacitor to optimize the total performance [68]. In addition to removing spikes at the inverter output signal, a RC snubber is also responsible to damp the parasitic ringing in the circuit [69]. In these applications, the value of the resistor must be close to the characteristic impedance of the parasitic resonant circuit it is intended to damp [70]. 70

82 Rs Cs Snubber Circuit Figure 5.4 Equivalent Circuit of the Snubber Circuit If the DC supply is assumed to have negligible internal impedance, the worst-case peak current in the snubber circuit can be calculated by the following equation [67], I PK = V o R s (5.1) where, R S = Snubber resistance, V o = Open circuit voltage The energy dissipated by the snubber is the energy stored in the snubber capacitor, C S. Thus the total energy dissipated through the resistor can be expressed as, E = 1 2 C s(v o ) 2 2f S (5.3) = C S (V o ) 2 f S (5.4) where, f S = switching frequency, 2f S = number of transitions per cycle 71

83 The snubber capacitance, C S has to meet two requirements. First, the energy stored in it must be greater than the energy in the circuit's inductance. 1 2 C SV o 2 > 1 2 LI2 (5.5) which can be rearranged as, C S > LI 2 /V o 2 (5.6) where, V o = open circuit voltage, I = closed circuit current and L = circuit inductance Secondly, the time constant of the snubber circuit should be small compared to the shortest on time expected, usually 10% of the on time. R s C s < T ON 10 (5.7) where, T on = Shortest on-time expected Using equations (5.1) to (5.6) as a guide [66], [67], the snubber resistor value was chosen to be 10Ω and the snubber capacitor to be 5.1uF for switching frequency 2.5kHz. The snubber reduces ringing by limiting the peak voltage on a switching transistor (i.e. IGBT in this thesis). As shown in equation (5.4), the snubber capacitance, C S is directly proportional to the switching frequency, f s. So, according to the proportional relationship, C S should change every time the switching frequency changes but in a lab set up it is impractical to change the snubber circuit of the inverter prototype every time the switching frequency changes. C S value is calculated for 2.5kHZ switching frequency and then the same snubber has been used for 2.5kHz and 5kHz as well. In order to use 72

84 the same snubber capacitor, the switching frequencies (200Hz, 2.5kHz and 5kHz) are kept in a close proximity. 5.3 Load Modeling and Load Value Calculations For the implementation of the scaled down version, the heavy load and light load are scaled down to W and 0.587W respectively for a 25Vdc supply input for practical reasons. In the hardware implementation, the same CFL model parameters described in section 4.3 is converted to match the scaled down power requirement. Figure 5.5 shows the CFL model with re-calculated values for C load and R load. The equivalent CFL model used in Figure 5.5 is similar as the simulation CFL model in section 4.2, except the sense resistor, R Sense is introduced in the load circuit in order to measure the total current flowing into the load from the inverter output while implementing in the hardware. Sense Resistor Rsense 1.56Ω ITotal Idc D1 D1N4148 D3 D1N4148 CLoad Vrect uf Vdc Rload Ω Inverter Block Vsystem = 14.14VRMS Frequency= 50hz D2 D1N4148 D4 D1N4148 Figure 5.5 Equivalent Circuit Model of CFL for Scaled Down Version As shown in Figure 5.5, the passive front-end single-phase diode bridge rectifier is the standard circuit for converting ac to dc in a CFL circuit which has four rectifier diodes. In this case, 73

85 D1N3940 is used at the rectifier circuit which is commonly used in full bridge rectifier circuits for CFL for its low forward voltage of 1V for a maximum forward current of 10mA. The sense resistance of the charging circuit, R Sense, represents the resistance through which the voltage drop is measured to measure the total current, I Total going through the load circuit of the inverter circuit [55] Determination of Component values for Light Load (CFL) Model As shown in Figure 5.4 above, the load capacitor C Load and the load resistor R Load resembles a RC parallel circuit. To obtain the values of load capacitor C Load and load resistor R Load a complete analysis of the RC parallel circuit stage is discussed in this section [71], [72]. The total phase angle for the CFL circuit is given by, θ CFL = tan 1 ( R Load X C ) (5.8) where, X C is the total capacitive reactance in the parallel RC circuit and as shown in Figure 5.5 and R Load is the load resistance. The total impedance in parallel RC circuit can be expressed as, Z = R LoadX C R Load 2 +X C 2 (5.9) 74

86 which can be rewritten as follows, R Load = tan θ CFL X C (5.10) Now combining equation (5.8) and equation (5.9) the following equation can be found, Z = x 2 C tan θ CFL = X C tan θ CFL (x c tan θ CFL ) 2 +x 2 C tan θ 2 +1 (5.11) Now, in order to find the value of the total impedance, Z of the RC parallel circuit, the value of θ CFL needs to be inserted. The value of θ CFL is known as it comes from the load power factor, cos θ. The power factor cos θ is a measure of the phase difference between the voltage and the current. CFLs are known for their low power factor, which is usually the result of a significant phase difference between the voltage and current at the load terminals, or it can be due to a high harmonic content or a distorted current waveform. For 9W CFL, the power factor is usually 0.65 [73]. The main reason for a low power factor in a CFL as a load is that it draws current that is not in phase with the voltage waveform. Poor power factor (<1) causes inefficiency in the delivery of electricity to the end-user, requiring more energy to compensate for losses on the line but also makes them an inexpensive and most available lighting option in rural households [74], [75]. In this thesis although the light load power was scaled down to 0.578W but the power factor is still maintained at 0.65 as with the full voltage design. For a power factor of 0.65, it can be written that, 75

87 cos θ = 0.65 (5.12) So, θ = cos 1 (0.65) = Here, tan = , so the total impedance of the RC parallel circuit can be derived from the following equation, Z = X c (1.169) = 1.169X C Therefore, Z = 0.76X C (5.13) Now, to find out the RMS current, I RMS, the total power can be written as P Total = V RMS I RMS cos θ CFL (5.14) = I RMS 0.65 I RMS = A (5.15) The apparent power, S of the RC parallel circuit can be expressed as S = V RMS I RMS Therefore, S = = VA (5.16) 76

88 In other terms, apparent power can also be written as, S = ( V Total Z )2 Z = (14.142)2 Z So, Z = Ω (5.17) Therefore by substituting the value of Z into equation (5.13) the load capacitance C Load can be found from the following equation = π 50 C Load C Load = π = 10.75uF And finally, R Load = X C tan θ = π = Ω Only the input voltage is scaled down from V to 25V and the output voltage is scaled down from 220V RMS to V RMS but the output current has been kept the same which is 62.9mA I RMS, output current for light load condition. The load capacitance can be calculated by using, 77

89 C Load = = 10uF The load capacitor, C Load = 0.7uF for 9W load capacitor by following the above equations and load resistor and capacitor calculations. The calculated values for 9W load capacitor and load resistor is used in the equivalent light load circuit in PSpice circuit described in chapter 4. A scaling factor of was used to find out the approximate values of the load capacitor and load resistor when the voltage is scaled down as mentioned before. Similarly the resistance can be calculated as, R = = Ω Ω Heavy Load Model Calculations RLoad Rsense 0.156Ω ITotal LLoad Vsystem = Vrms fsystem = 50Hz Figure 5.6 Equivalent Heavy Load for Scaled Down Version 78

90 As mentioned above, the heavy load is modeled as a simplified equivalent combination of a table fan, mini refrigerator and a sewing machine. The heavy load is mostly inductive-resistive in nature. When the inverter is connected to an inductive-resistive kind of load, the anti-parallel diode of the IGBT helps the IGBT to perform as a fully functional switch [76]. The antiparallel diode connected to the IGBT provides suitable reverse current for the inductive load. To obtain the values of load resistor, R Load and load inductance, L Load in the context of heavy load a complete analysis of the RL series circuit stage is discussed in this section. The power factor for the heavy load is considered to be 0.8 [73], so the power factor angle can be expressed as, cos = 0.8 = cos 1 (0.8) = (5.17) The total phase angle can also be written as, tan = ωl R Load (5.18) tan( ) = 0.75 = ω L R Load ωl R Load 0.75R Load = ωl L = 0.75R Load ω Therefore, L = R Load (5.19) 79

91 Now, the total power of the RL circuit can be expressed as, P = V RMS I RMS cos = I RMS 0.8 I RMS = A It is important to note that only the RMS voltage has been scaled down to V from 220V but the current remains same for both power levels of W and 200W. Thus, the RMS current is maintained at 1.136A. By following Ohm s law the total RMS current can also be expressed as, I RMS = V RMS Z (5.20) The total impedance Z can be written as, Z = R Load 2 + (2πfL) 2 (5.21) Substituting the equation (5.21) into equation (5.20), I RMS = V RMS R 2 +(2πfL) 2 (5.20) By substituting the value of I RMS into equation (5.20), 80

92 1.136 = R 2 +(2πfL) 2 Now, by substituting equation (5.19) into equation (5.20), = = = R 2 +(2πf R) R 2 {1+(2πf )} R Therefore, R = = Ω Substituting the value of resistance into equation (5.19), the load inductance, L Load = ( ) (2π 50) = H Thus, the resistor is Ω and the inductor is H. 81

93 5.3.3 Current Sense Resistors As shown in Figure 5.6 the shunt resistor is used to measure current at the heavy load output. Generally, when designing power supplies and regulated battery circuits, the aim is to eliminate the risk of short circuits or over current conditions which are likely to damage other components. Current resistors are a simple and economic means to protect the switch mode power supplies like the inverter circuit. The current resistors, also called shunt resistors, are used to monitor the current in a circuit and translate the current into a voltage that can be easily measured and monitored. Such resistors have very low resistance values, typically less than 1Ω [77]. In this thesis, for heavy load the sense resistor is taken to be but for light load the sense resistor was chosen to be 1.56Ω. A bigger resistor for current measurement is required for this experiment, as both the input and output current for light load is very small and difficult to measure accurately with the available measurement tools. The currents flowing into the inverter circuit which is the input current of the inverter and through the load circuit which is the output current of the inverter is measure though the current resistors for both heavy and light load cases but with different resistor values. 5.4 Experimental Results The inverter prototype was developed and tested in a modular fashion. Several tests were conducted to check if components are working individually. Then, components are integrated to 82

94 make the whole inverter circuit. After verifying inverter prototype operation, the results listed in Table 5.1 were obtained Measurement Approach For hardware result analysis the Tektronix 3100 oscilloscope data was used with RS232 serial data transmission cable. The oscilloscope window was set to 20ms to capture a full cycle of the signal. The data acquired through the RS232 was then transferred to the laptop through a Tektronix software called Open Choice Desktop. The data is captured through waveform data capture and then the data table is saved as a.csv file. The.csv file contains 10,000 samples for 20ms data. The following data files are generated for each switching frequency using Open Choice Desktop : 1. Voltage at input and output side before the sense resistor. 2. Voltage at input and output side after the sense resistor. 3. Output voltage for specific load condition. Once the voltage drop across the sense resistor is found, the voltage difference is divided by the value of the sense resistor (0.156 for light load, 1.56 for heavy load) to find out the input and output current. The voltage drop at the inverter output is taken by using the MATH function of the oscilloscope. Input and output voltages are directly available from oscilloscope data. MATLAB code was written for output and input power calculations. After acquiring the both voltage and 83

95 current vectors in MATLAB.csv file (10,000 samples within 20ms), they are integrated over time using the trapz function. This quantity is further divided by 20ms to obtain the average input and output power. After the input and output power was calculated the efficiency calculation is done by dividing the output power by input power in a separate MATLAB file. The values of hardware results (scaled down version) found through the data analysis of MATLAB are shown in the Table Results and Discussion The hardware results for a scaled down version of the full voltage design are shown in Table 5.1. Table 5.1 Hardware Results of full load and light load Load Switching Output Total Input Efficiency Frequency Power Loss Power (khz) (W) (W) (W) (%) Full Load (12.856W) Light Load (0.578W)

96 The results show the same trend as the simulations and loss model based efficiency calculation. As mentioned before, only the scaled down version (12.856W rated power) has been implemented in the lab. The inverter efficiency increases as the switching frequency is reduced. The hardware results agree with the simulation and mathematical results of the scaled down version as shown in previous chapters. The efficiency of the experimental inverter circuit as shown in the fourth column in the above table (Table 5.1) is calculated by dividing the average output power by the average input power. The average output power is given by, P Output = t=20ms t=0 V Out (t) I Out (t)dt 20ms, once the circuit is operating in steady-state, where the output power is an integral of the output voltage times output current which is then divided by the total time 20ms. The average input power is found in a similar manner, using, P Input = t=20ms t=0 V In (t) I In (t)dt 20ms, once the circuit is operating in steady-state, where the input power is an integral of the input voltage times input current which is then divided by the total time 20ms. The comparison between the results (scaled down version) of the mathematical analysis, simulation model and the hardware prototype is presented in Table

97 Table 5.2 Comparison of the Efficiencies Load Switching Frequency Mathematical Analysis PSpice Simulation Hardware Implementation (khz) (%) (%) (%) Full Load (12.856W) (0.578W) As shown in the above table, Table 5.2, there is a slight difference in efficiency between the mathematical analysis and the other two models (simulation and hardware). One reason for the discrepancy maybe the linearization performed using datasheet information (see Figures 3.2 to 3.5). However, the simulation is performed in PSpice using practical component models and thus shows good agreement with the hardware test results. 5.5 Chapter Summary This chapter discusses the details of how the inverter prototype was built and tested. The full voltage design (rated power 200W) was not implemented in hardware. Instead a scaled down 86

98 design of W was used. The first part of this chapter describes the calculation of the component values for the light and heavy load tests. The hardware results show the expected result that reducing the switching frequency at low power decreases switching loss, thus increases efficiency for the same load. The hardware results also show the similar results as simulation and mathematical results as described in Chapters 3 and 4. The mathematical and simulation result tables (Table 3.1 and Table 4.1) for the full voltage design shows less variation in efficiency than at low power (Table 5.1). 87

99 Chapter Six: Conclusions 6.1 Summary In Chapter 2, a detailed analysis of different techniques to improve inverter efficiency is carried out. Five different techniques were discussed: hybrid switch (combination of MOSFET and IGBT), enabling pulse skipping mode, implementing Zero Voltage Switching (ZVS) while turning on and off, limiting current through burst mode LLC and using variable switching frequency in discontinuous current mode (DCM). It was found that the decreasing switching frequency is superior in improving the inverter efficiency at low power than the hybrid switch configuration, ZVS and burst mode LLC. Also, there is a need for an optimum snubber circuit for each switching frequency. For grid connected inverters, more complex control circuits for maintaining the power quality at the inverter output are required. However, for a stand-alone rural solar home system the power quality is traded off with the increased inverter efficiency at low power. The research work is given in three main parts: Chapters 3, 4 and 5. Chapter 3 presents the mathematical analysis of the proposed full bridge SPWM inverter and results found by using the loss equations. Chapter 4 describes the PSpice simulation of the proposed inverter and the simulation results for varying switching frequencies. In Chapter 5, the hardware implementation is presented and results are found for the scaled down version of the rated load and the light load. In Chapter 5 the comparison of the mathematical analysis, simulation model and inverter prototype is shown for the scaled down version which shows agreement among the results found from these three analyses. 88

100 6.2 Contributions The major contributions of the thesis, presented in Chapter 3 and verified through simulation studies done in Chapters 4 and the prototype study in Chapter 5, are: 1. The loss components are calculated both for maximum rated power and low power operation using the loss model equations and device datasheet values. Several loss components (i.e. conduction loss, switching loss, drive loss) that affect inverter efficiency are taken into account. The switching frequencies are varied from higher to lower values to see the efficiency trend from rated to low power conditions. The mathematical model results are then verified by results achieved in simulation and experimental lab implementation of the proposed inverter. 2. The inverter design is simulated in OrCad PSpice CIS Lite (Version 16.6), to better understand losses and to accurately predict operation of the inverter in a practical set-up. The efficiency trends as a function of switching frequency seen in simulations resemble the efficiency trends in the practical hardware set-up. The simplified load models simulated in PSpice and the characteristics of the output voltage and current of the simulated inverter also comply with the practical inverter prototype. 3. Experimentally, a scaled down version of the proposed 200W inverter is implemented in the lab setup W is considered to be the maximum rated power and 4.5% of the rated 89

101 power is 0.578W is considered as a low power scenario for the lab implementation. The inverter is tested by changing switching frequencies for both cases with simplified experimental load models. The current rating is kept the same in the scaled down version as for the full voltage design, in order to observe the similar inverter efficiency trend as in the full voltage design (200W rating). A cost effective microcontroller, the MSP3430, is used to generate the control signals. To suppress the transient voltage spikes at the inverter output, a snubber circuit is designed. The switching frequencies are kept in a closed range so that the same snubber circuit can be used for different switching frequencies. 4. The comparison of the efficiency trend results is presented for the loss model based calculation, computer simulation and the lab based inverter prototype. Issues are discussed related to the improved inverter efficiency when switching frequencies are decreased at low power. In mathematical modeling a wide range of switching frequency (200Hz 20kHz) is used to measure the efficiency at rated and low power levels. However, while measuring efficiency for simulations and hardware implementation the switching frequency is kept in a more restricted range of 200Hz to 5kHz for the scaled down version (e.g W rating). The restricted range of frequency is employed in order to use the same snubber circuit for all the switching frequencies. 90

102 6.3 Suggestions for Future Work 1. The full scale design to provide 50Hz, 220V RMS developed in the mathematical analysis and for the simulated inverter should be implemented in hardware and a similar analysis can be performed to verify the efficiency and total loss calculations. 2. To maximize the inverter efficiency at different power levels, there should be an automated load sensing technique that would sense the load to send feedback to the controller in order to set the optimum switching frequency. 3. Instead of using the simplified load models in the hardware implantation, real loads (e.g. CFL, mini refrigerator, sewing machine) can be used to observe the inverter output voltage and current characteristics. 4. The snubber circuit losses can be included in the loss calculations and the snubber circuits can be included in the PSpice inverter model. Also, further investigation can be done in terms of designing an optimum snubber which will perform well through a wide range of switching frequencies. 5. Further investigation is needed to determine the practical range of switching frequencies. It is expected that this will not be a trivial task. The higher switching frequencies assist in reducing current THD for inductive loads but at the cost of reduced inverter efficiency. The 91

103 lower switching frequencies increase inverter efficiency but with increased current THD for some loads. 6. This thesis is based on the idea that an inexpensive inverter, for use in the developing world, may not require an output filter for many household loads. This ideas needs to be investigated further: loads for which this is true; effect on load performance, load longevity, etc. Also, if it is found that a filter is necessary, or may be an option for certain loads, an investigation of filter requirements and means to simplify filter design and reduce filter cost, would all be helpful. 92

104 References [1] J. Muñoz and E. Lorenzo, Technical Standard for Stand-Alone PV Systems using Inverters, in European Photovoltaic Solar Energy Conference, Munich, Germany, 2003, pp [2] F. Vignola, F. Mavromatakis and J. Krumsick, Performance of PV Inverters, in ASES Annual Conference, San Diego, CA, [3] H. Akca and U. S. Selamogullari, Hybrid Switch use for Light Load Efficiency Improvement of a Power Inverter for Stand-Alone Residential Renewable Energy System, in European Conference on Power Electronics and Applications (EPE), IEEE, Lille, France, 2013, pp [4] B. Johansson, Renewable Energy in Energy-Efficient, Low-Pollution Systems, PhD diss., Lund University, [5] W. E. Reid, Power Quality Issues- Standards and Guidelines, in IEEE Power Delivery, vol. 32, no. 3, May/June [6] IEEE Application Guide for IEEE Std 1547, IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems, IEEE Standard 1547, Photovoltaics, Dispersed Generation, [7] Characteristics of the Utility Interface for Photovoltaic (PV) Systems, IEC Standard 61727, International Electro-technical Commission, Report of IEC, [8] S. B. Kjaer, J. K. Pedersen and F. Blaabjerg, A Review of Single-Phase Grid-Connected Inverters for Photovoltaic Modules, in Industry Applications, IEEE, vol. 41, no. 5, pp , [9] Y. Xiong, S. Sun, H. Jia, P. Shea and Z. J. Shen, New Physical Insights on Power MOSFET Switching Losses, in Power Electronics, IEEE, vol. 24, no. 2, pp ,

105 [10] D. Songquan, H. Mao, T. Wu, S. Xiao and I. Batarseh, Power Losses Estimation Platform for Power Converters, in Applied Power Electronics Conference and Exposition, IEEE, 2004, Anaheim, CA, pp [11] J. H. Hahn, Modified Sine-Wave Inverter Enhanced, in Power Electronics Technology, vol. 32, no. 8, [12] O. Turna, Pure Sine vs. Modified Sine Wave Inverters, San Francisco, CA, April 8, 2011, [Online], Available: Access date: September [13] F. L. Luo and H. Ye, Advanced DC/AC Inverters: Applications in Renewable Energy, CRC Press, January 22, [14] N. N. Sayeed, A. A. S. Hossain, N. Hasan and M. A. Bhuiyan, Design of a Pure Sine Wave Inverter for PV Application, PhD diss., BRAC University, [15]J. Doucet, D. Eggleston and J. Shaw, DC/AC Pure Sine Wave Inverter, MSc diss., NECAMSID, [16] P. H. Zope, P. G. Bhangale and S. R. Suralkar, Design and Implementation of Carrier Based Sinusoidal PWM (Bipolar) Inverter, in International Journal of Engineering Science and Research, vol. 1, no. 3, December [17] D. Homes, T. Lipo, Pulse Width Modulation for Power Converters: Principles and Practice John Wiley & Sons, Ch. 1, pp. 1-56, [18] G. A. Mazur, Digital Multi-meter Principles, in American Technical Publishers, [Online], Available: Access date: November 11,

106 [19] S. Jian, Dynamics and Control of Switched Electronic Systems, Springer-Verlag London Limited, Ch. 2, pp , [20] A. K. Sharma, A. K. Sharma and N. Vijay, Unipolar and Bipolar Voltage Modulation Type Inverter for Improved Switching Frequencies, in International Journal of Engineering Sciences and Research Technology, vol. 3, no. 8, August [21] D. Li and C. Ramos, Design of a High-Low Unipolar Pulse Width Modulated Inverter, Senior project, Electrical Engineering Department, California Poly technique State University, June [22] P. N. Swetha and D. S. Reddy, Design and Implementation of Combined Unipolar and Bipolar PWM Technique for Reducing Current Distortions and Current Ripples. in International Journal of Computational Science, Mathematics and Engineering, vol. 2, no. 5, May [23] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, Springer Science & Business Media, Ch. 2, pp , [24] R. Beiranvand, B. Rashidian, M. R. Zolghadri and S. M. H. Alavi, Using LLC Resonant Converter for Designing Wide-Range Voltage Source, in Industrial Electronics, IEEE Transactions, vol. 58, no. 5, pp , [25] H. Hu, W. A. Hoor, N. H. Kutkut, I. Batarseh and Z. Shen, Efficiency Improvement of Grid- Tied Inverters at Low Input Power using Pulse-Skipping Control Strategy. in IEEE Transactions on Power Electronics, vol. 25, no. 12, pp , December [26] V. Yousefzadeh, D. Maksimović and Q. Lig, A Zero Voltage Switching Single-Phase Inverter using Hybrid Pulse-Width Modulation Technique, in Power Electronics Specialists Conference, IEEE, 2004, vol. 2, pp

107 [27] B. Wang, X. Xin, S. Wu, H. Wu and J. Ying, Analysis and Implementation of LLC burst mode for light load efficiency improvement. in Applied Power Electronics Conference and Exposition, IEEE, Washington, DC, February 2009, pp [28] E. Seinen, How to Get Higher Efficiency at Lower Loads: A New LLC Platform Makes it Possible, NXP International Product, March [29] S. Maniktala, Understanding and using LLC Converters to Great Advantage, Microsemi, Analog Mixed Signal Group, [30] Z. Zhang, M. Chen, M. Gao, Q. Mo, and Z. Qian, An Optimal Control Method for Grid- Connected Photovoltaic Micro-inverter to Improve the Efficiency at Light-Load Condition, in Energy Conversion Congress and Exposition (ECCE), IEEE, Phoenix, AZ, USA, pp , [31] O. A. Naseem, R. W. Erickson and P. Carlin, Prediction of Switching Loss Variations by Averaged Switch Modeling, in Applied Power Electronics Conference and Exposition, IEEE, Dallas, TX, USA, 2000, vol. 1, pp [32] B. L. C. Martinez, R. Li, K. Ma and D. Xu, Hard Switching and Soft Switching Inverters Efficiency Evaluation, in International Conference on Electrical Machines and Systems, Wuhan, China, 2008, pp [33] B. Ismail, S. Taib, M. Isa and C. M. Hadzer, Development of a Single Phase SPWM Microcontroller-based Inverter, in Power and Energy Conference, IEEE, Gaborone, Botswana, 2006, pp [34] N. Allet, F. Baumgartner, J. Sutterlueti, S. Sellner and M. Pezzotti, Inverter Performance under Field Conditions, in EU PVSEC, Hamburg, Germany, 2010, pp

108 [35] N. Ekren, N. Onat and S. Saglam, Household Type Load s Effects on Photovoltaic Systems, in WSEAS Transactions on Circuits and Systems, vol. 7, no. 12, pp , [36] J. H. Lee and B. H. Cho, Large Time-Scale Electro-Thermal Simulation for Loss and Thermal Management of Power MOSFET, in Power Electronics Specialist Conference, IEEE, Acapulco, Mexico, June 2003, pp [37] M. C. Oberdorf, Power Losses and Thermal Modeling of a Voltage Source Inverter, PhD diss., Naval Post Graduate School, Monterey, CA, March [38] M.H. Bierhoff and F. W. Fuchs, Semiconductor Losses in Voltage Source and Current Source IGBT Converters Based on Analytical Derivation, in Power Electronics Specialists Conference, IEEE, Aachen, Germany, 2004, vol. 4, pp [39] S. K. Pattnaik and K. K. Mahapatra, Power Loss Estimation for PWM and Soft-switching Inverter using RDCLI, in International Multi Conference of Engineers and Computer Scientists, Hong Kong, March 17-19, 2010, vol. 2. [40] C. Graovac and M. Purschel, IGBT Power Losses Calculation using the Data-Sheet Parameters, Infineon Technologies AG Application Note, January [41] K. Berringer, J. Marvin and P. Perruchoud, Semiconductor Power Loss in AC Inverter, in Industry Applications Conference, Orlando, Florida, USA, 1995, vol. 1, pp [42] B. K. Bose, Power Electronics and Motor Drives: Advances and Trends Academic press, Ch. 2, pp , [43] C. Liu, B. Wu, N. R. Zargari, D. Xu and J. Wang, A Novel Three-Phase Three-Leg AC/AC Converter using Nine IGBTs, in Power Electronics, IEEE Transactions, vol. 5, no. 24, pp ,

109 [44] U. Nicolai and A. Wintrich, Determining Switching Losses of SEMIKRON IGBT Modules, SEMIKRON Application Note, AN 1403, August [45] J. Karlsson, The Concept of IGBT Modeling and the Evaluation of the PSPICE IGBT Model, MSc. Diss., Industrial and Electrical Engineering and Automation (IEA), [46] L. J. Sheng, Resonant Snubber-based Soft-Switching Inverters for Electric Propulsion Drives, in Industrial Electronics, IEEE Transactions, vol. 44, no. 1, pp , [47] IGBT/MOSFET Gate Drive Optocoupler, Application Note 91, [Online], Available: access date: November [48] N. Chandrasekaran and K. Thyagarajah, Simulation and Experimental Validation of AC motor and PMDC Motor Pumping System Fed by Photovoltaic Cell, in Indian Journal of Engineering and Materials Sciences, vol. 21, no. 1, pp , February [49] S. Maheshri and K. Prabodh, Simulation of Single Phase SPWM Unipolar Inverter, in International Journal of Innovative Research in Advanced Engineering (IJIRAE), vol. 1, no. 3, October [50] P. H. Zope, P. G. Bhangale, P. Sonare and S. R. Suralkar, Design and Implementation of Carrier based Sinusoidal PWM Inverter, in International Journal of advanced research in electrical, electronics and instrumentation engineering, vol. 1, no. 4, pp , [51] H. L. Chen and C. K. Tee, Keeping Inverters Safe, Avago Technologies San Jose, EET, [Online], Available: Access date: September 23, [52] B. R. Sidney and D. Holliday, Optimal Regular-Sampled PWM Inverter Control Techniques, in Industrial Electronics, IEEE Transactions, vol. 54,no. 3, pp ,

110 [53] S. Jeevananthan, R. Nandhakumar and P. Dananjayan, Inverted Sine Carrier for Fundamental Fortification in PWM Inverters and FPGA based Implementations, in Serbian Journal of Electrical Engineering, vol. 4, no. 2, pp , [54] C. Cresswell, Steady State Load Models for Power System Analysis, Phd diss., May [55] W. M. Kwok, Standards of Power Quality with Reference to the Code of Practice for Energy Efficiency of Electrical Installations, Energy Efficiency Office, Electrical & Mechanical Service Department, September [56] J. Molina and S. Luis, Model of Electronic Ballast Compact Fluorescent Lamps, in Power Delivery, IEEE, vol. 29, no. 3, pp , [57] N. R. Watson, T. Scott and S. Hirsch, Compact Fluorescent Lamps (CFL) Implications for Distribution Networks, Application Note AS/NZS , [Online], Available: s.pdf [58] K. Deželak, P. Sukič and G. Štumberger, Impact of Compact Fluorescent Lamps on the Excessive Transmission Line Losses, in International Conference on Renewable Energies and Power Quality, Santiago de Compostela, Spain, [59] V. George, A. Bagaria, P. Singh, S. R. Pampattiwar and S. Periwal, Comparison of CFL and LED lamp-harmonic Disturbances, Economics (cost and power quality) and Maximum Possible loading in a Power System, in Utility Exhibition on Power and Energy Systems: Issues & Prospects for Asia (ICUE), International Conference, IEEE, Pattaya, Thailand, 2011, pp [60] Power Quality Implications of Compact Fluorescent Lamps in Residences, National Electrical Manufacturers Association, 1999, [Online], Available: 99

111 Residences.aspx, Access date: March 11, [61] B. Ledbuizen, Lamp measurement report - CFL E27 30W Germany, in Environmental Change Institute, January [62] A. M. Ahmed, A. A. Bashit, M. S. Alam and H. Begum, Improvement of Input-Side Current of a Single Phase Rectifier with Variable Output Voltage Range using Boost Converter and Investigation of Harmonic Minimization, in International Journal of Scientific & Engineering Research, vol. 4, no. 13, pp , March [63] B. Ireland, The Hidden Costs of CFLs, in Electrical Construction and Maintenance, [Online], available: Access date: November 5, [64] Code Composer Studio, vol. 6.1, MSP430 User's Guide, may 2009 Revised may [65] F. Z. Peng, S. J. Gui, L. M. Tolbert, A Passive Soft-Switching Snubber for PWM Inverters, in Power Electronics, IEEE, vol. 19, no. 2, pp , March [66] J. Hagerman, Calculating Optimum Snubbers, Hagerman Technology, July 24, [67] W. McMurray, Optimum Snubbers for Power Semiconductors, in Industry Applications, IEEE, pp , September [68] RC Snubbers, Illinois Capacitor. INC, [Online], Available: Access date: December 31, [69] W. McMurray, Selection of Snubbers and Clamps to Optimize the Design of Transistor Switching Converters, in Power Electronics Specialists Conference, IEEE, CA, USA, July 1979, vol. 16, no. 4, pp

112 [70] T. L. Floyd, Electric Circuits Fundamentals, in Prentice Hall, Inc., Ch. 5, pp , July 3, [71] C. Alexander, C. K. Alexander and M. N. Sadiku, Fundamentals of electric circuits, Urban Media Comics, pp. 64, [72] J. Ware, Power Factor Correction (PFC), IEE Wiring Matters, July [73] J. Tsao, N. Lewis, G. Crabtree, Solar FAQs, Sandia National Labs, April 20, [74] W. E. Reid, Power Quality Issues- Standards and Guidelines, in IEEE Power Delivery, vol. 32, no. 3, May/June [76] J. Dodge and J. Hess IGBT Tutorial, Advanced Power technology, application note APT0201, EE Times, July [77] P. Semig and C. Wells, A Current Sensing Tutorial-Part 1: Fundamentals, Texas Instruments, EE Times, August [78] T. H. Loba, D. H. Wood and E. P. Nowicki, Improving Inverter Efficiency at Low Power by Reducing Switching Frequency, in Canadian Conference on Electrical and Computer Engineering (CCECE), IEEE, May 2015, pp

113 APPENDIX A: SCHEMATIC DIAGRAM OF FULL BRIDGE INVERTER Figure A-1 Full Bridge Inverter Supplying Power to the Heavy Load. Inverter shown in Figure A-1 is supplying power to the simplified equivalent heavy load model. L1 and R1 make the equivalent load model. The SPWM controller generates gating signals for the four switches and controls the switching in such a way that AC signal is delivered at the output of the inverter. A pair of antiparallel diodes are forward biased based on which switching IGBT pair is switching. 102

114 Figure A-3 Full Bridge Inverter Supplying Power to the Light Load. 103

115 APPENDIX B: COMPONENT LIST FOR EXPERIMENTAL SETUP The inverter circuit mainly consists of four components: 1. DC-DC converter IC (NME0515SC) 2. Optocoupler IC (FOD3184) 3. IGBT (IRG4BC20UD) 4. Microcontroller development kit (MSP430) DC-DC Converter IC NME0515SC is an isolated 1W single output DC/DC converter, shown in Figure B-1. The nominal input voltage of the converter is 5V and the output voltage is 15V. The maximum output current is 66mA with conversion efficiency of 80%. Figure B-1 DC-DC Converter NME0515SC (Picture from device data sheet: pdf) 104

116 IGBT IC IRG4BC20UD is an ultra-fast, generation 4 IGBT design co-packaged with anti-parallel diode shown in Figure B-2. The collector to emitter voltage rating is 600V and the continuous collector rating is 6.5A. The diode forward voltage drop of the anti-parallel diode is 1.4V for a current of 7A. Figure B-2 DC-DC Converter NME0515SC (Picture from device data sheet: Optocoupler IC FOD3184 is a high speed MOSFET/IGBT gate driver optocoupler with 3A peak output current, shown in Figure B-3. It has a wide output voltage range of 15V to 30V. The input current, I F, to turn on the LED is 10mA to 16mA. 105

117 Figure B-3 Optocoupler FOD3184 (Picture from device data sheet: In this thesis, a MSP430 development kit has been used in order to implement SPWM control. The details of MSP430 are discussed in Appendix C. 106

118 APPENDIX C: MICROCONTROLLER (MSP430G2553) OVERVIEW The microcontroller is the heart of the inverter system. The MSP430G2553 microcontroller IC is programmed to generate four SPWM signals which are fed to the gates of the IGBTs through the optocouplers. The chosen microcontroller is small in size, light in weight and inexpensive. Other considerations for choosing the MSP430G2553 is its high computing power and ultra-low power consumption. The MSP430 LaunchPad TM (http of TI website) is an economical microcontroller development board. The MSP430G2553 IC is embedded in the MSP430 LaunchPad TM (conveniently in an IC socket). The LaunchPad comes with free software and a full series of tutorials. Also, the MSP430 LaunchPad (Figure A3) includes: a communication module port for computer interfacing, debug mode for testing the programmes, access to input/output microcontroller's ports, Universal Asynchronous Receiver/Transmitter Interface (UART) port, and the necessary software and drivers for the computer. Figure C-1 MSP430 LaunchPad. 107