Studies of Upset and Nonlinear Effects in Circuits and Systems

Transcription

1 IREAP Studies of Upset and Nonlinear Effects in Circuits and Systems John Rodgers, Todd Firestone, Victor Granatstein, Thomas Antonsen, Ed Ott, Steve Anlage*, Renato Mariz de Moraes*, Vassili Demergis*, Alexander Glasser* and Marshal Miller* Institute for Research in Electronics and Applied Physics *Department of Physics University of Maryland College Park, MD 2742

2 IREAP Goals of Microwave Effects Task Not another cookbook approach Investigate basic high-frequency electronics Measure the (out-of-band) frequency response of fundamental devices excited by microwave pulses Map transfer characteristics of circuits Develop simple but comprehensive models for simulations Understand how RF response scales with device size, speed, logic levels and operating voltages.

3 IREAP Outline Overview of nonlinear circuit elements and their microwave characteristics Examples of experimental results: Parasitic resonances in integrated circuits Simple rectification by electrostatic discharge (ESD) protection Bias shift, RF gain, and instability in devices Effects from RF sources with wideband modulation Chaotic circuit response Results from high-frequency SPICE Models RF Effects in systems

4 IC development and technological trends Circuits under test at UMD Number in Service Faster, Smaller, Lower Voltage Source: Logic Reference Guide, Texas Instruments Inc., 22.

5 IREAP Examples of input circuitry in advanced logic Virtually all chips have electrostatic discharge protection integrated into their physical layout

6 IREAP Typical layout of a CMOS gate with electrostatic discharge (ESD) protection Capacitive loading is predominately from ESD

7 RF Pulse IREAP Schematic of a CMOS data line ESD Diode L parasitic C(V,f) Vcc Driver Bus Line ESD Diode C(V,f) Inverter IC Package Typical LC values in advanced CMOS have GHz resonant frequencies

8 Analysis of simplified CMOS input (series RLD circuit) with equivalent diode model A V V 1+ sc R = = V + s L C + sc R d j S 2 in 1 P j j S A ( ω ) = 1 j L / C ( V )/ R V R P j D S Q = Lp / Cj( VD)/ Rs Typical values: C 3 L R R j P V S pf 1 nh 1 MΩ 1Ω Give:.5 < f < 3GHz R 2< Q < < A < 6 V

9 Calculated capacitance, impedance and voltage gain for simplified CMOS model Cj =3.6 pf, Lp=16nH, Rs=15 Ω Voltage Gain

10 IREAP Measured input impedance (small signal) vs. frequency and bias voltage in typical micron-scale CMOS Impedance [Ohms] Vbias= -.6 Vbias=. Vbias= Frequency [GHz] C j, f r, and Q depend on bias voltage Logic voltages at input shift the microwave response How about rectified voltages?

11 Rectification of RF in Circuits w/ ESD Diodes and Parasitic Elements Input I-V characteristic of CMOS w/ ESD diodes Input Voltage RF RF V dd V il Input Current, Time L Vdd V logic steers RF current which determines circuit impedance and response V rf V logic I RF L in ESD ESD I RF PMOS NMOS Vout ESR C BP V dd

12 Realistic digital waveforms have high probability of being near the threshold voltage where RF susceptibility is high. 6 Voltage [V] V_out V_logic RF -4 Eye diagram of Pentium data Time [µsec] Also, the high-frequency response (f r, and Q) in devices is a moving target.

13 The diode detects the AM (pulse) frequencies on the RF carrier and generates harmonics of the excitation signal Amplitude 1 RF Harmonics Baseband Amplitude 1 Frequency 2 Frequency Detected voltage (small-signal) at baseband: v v G RF-to-Baseband voltage transfer related to diode parameters. The signal the CMOS sees occupies two distinct frequency bands. det 2 RF

14 Effects due to Rectification of RF pulse by ESD diodes Voltage Prompt Bit Error Vout Vin Voltage Oscillations Vout Vin Time (µsec) -2 Time (µsec) Voltage [V] Undefined Voltages & Latent Latch Vin Vout Time [µsec] Voltage More Oscillations Vout Vin Time (µsec)

15 Example of CMOS family (LVX) that is latched by RF only when input is biased high Voltage (V) Vin Vout Time ( µsec )

16 Contours of measured large-signal response in advanced CMOS HCT ALVC

17 IREAP RF pulse biasing both CMOS transistors into conduction where they amplify high-frequencies. +Vdd Tail End of LVX Input and Output Voltages as RF Pulse Terminates 2.5 ESD PMOS Ids 2 Vin Lparasitic ESD NMOS Vout Voltage Vin Vout Time [microseconds]

18 IREAP Nonlinear response in circuits generates harmonics of the RF and modulation signals which can excite high and low-frequency oscillations in the circuit. 5 4 Vout Vin 3 Voltage 2 1 Video Clip Time (µsec)

19 CMOS RF RF transfer characteristics 3 8 Output Voltage [V] Voltage Current Supply Current [ma] Measurements RF Amplitude [V] RF Gain [dbv] Gain Amplitude Output RF Amplitude [V] Simulation Results Video Clip RF Amplitude [V] Video Clip

20 How to hit a moving target Attenuator Vbias.2 Hughes 8537H TWTA Variable Atten. Delay Line 3 db 2 db 2 db Spectrum Analyzer RF Detector Bias Tee DUT= ALVC Vout RF Amplitude Scope Time [us] -15 Spectral Power [dbm] A(t-7tau/4) Frequency [GHz] A(t)

21 Response of Advanced Low-Voltage CMOS to wideband RF source (RF amplitude = 45 mv) 2 5 Input Response Voltage Output Voltage Time [ µsec ] -5

22 Chaos in the Driven RLD Circuit Data 1 R L D Voltage across Resistor R ~ I 2 4 chaos I V sin(ωt) f = 2.5 MHz Maximum Voltage across Resistor R 1 4 chaos 2 Driving Amplitude V (V) Bifurcation diagram R = 25 Ω L = 5 µh D = NTE61 f = 2.5 MHz

23 Search for Period Doubling and Chaos in Driven RLD Circuit Diode τ RR (ns) C j (pf) Results with f ~ 1/τ RR 1N Period-doubling and chaos for f/f ~ N Period-doubling and chaos for f/f ~ N5475B Period-doubling and chaos for f/f ~ NTE Period-doubling and chaos for f/f ~ V LF L RLD V sin(2π ft) D R Results with f ~ 1/τ RR Period-doubling and chaos f/f ~ Period-doubling and chaos for f/f ~ No chaos, nor period-doubling Period-doubling only for f/f ~ f = 2π 1 LC j Results with f ~ 1/τ RR No chaos, nor period-doubling No period doubling or chaos No chaos, nor period-doubling No chaos, nor period-doubling

24 Chaos in the Driven Diode IREAPDistributed Circuit R g mismatch Transmission Line V g (t) Z delay T V inc V ref A simple model of p/n junctions in computers Delay differential equations for the diode voltage + V(t) - New Time-Scale!

25 Chaos in the Driven Diode IREAPDistributed Circuit Simulation results V g =.5 V Period 1 V(t) (Volts) Time (s) V g = 2.25 V Period 2 V(t) (Volts) Time (s) V g = 3.5 V Period 4 V(t) (Volts) Time (s) V g = 5.25 V f = 7 MHz T = 87.5 ps R g = 1 Ω Z = 7 Ω PLC, C r = C f /1 Chaos V(t) (Volts) Time (s)

26 Chaos in the Driven Diode IREAPDistributed Circuit Simulation results Strobe Points (Volts) Period 1 Period 2 f = 7 MHz T = 87.5 ps R g = 1 Ω Z = 7 Ω PLC, C r = C f /1 Period 4 V g (Volts) Chaos

27 IREAP RF effects modeling using SPICE L p V DD = 3V ESD_LVC_V DD 2 pf L p LVC CMOS 8 nh v RF 1 MHz LPF ESD_LVC.2 pf 1 MΩ v det 1 kω L p 8 nh V bias Includes: Package and bonding parasitics High frequency characteristics of power line and bypass capacitor ESD diodes: reverse recovery, C j (V), R s and charge conservation

28 IREAP Comparison of measured and simulated response in CMOS w/ ESD Models can even predict relaxation oscillations: Video Clip

29 IREAP RF Effects in communications and data systems Generalize approach for a wide variety of devices using scaling laws Study RF interactions between interconnected devices on transmission lines Develop systems-level response models Validate simulations with measurements

30 IREAP RF effects decease when devices are heavily loaded by low-impedance interconnects and line drivers. RF Pulse +Vdd ESD PMOS Driver Conductance Z line V det Lparasitic ESD NMOS Vout

31 Systems Example: Programmable LAN Switch 8 Pin Count I/O Logic System Controller CPU Memory Quality Factor Resonant Frequency (GHz)

32 IREAP Summary of Most Significant Results Identified the culprits: Nonlinear devices (e.g. ESD diodes) have been shown to be the likeliest cause of upset in circuits, µwave diode model works Know their MO: i.e. how to measure & model the fundamental HF elements and construct equivalent circuits Variety of effects (rectification, oscillation, RF gain and instability) in circuits have been characterized. Studied some important scaling laws: device size, speed, operating and logic voltages, package parasitics Can predict RF effects: High-frequency SPICE models are fast, easy & work Outline a systems-level approach: looks promising, significant progress made Note: Basis for intelligent design of HPM sources (frequency, bandwidth, modulation, pulse width, etc.)

33 IREAP Future Work Study emerging technologies (BiCMOS, LinBiCMOS, Low Voltage Differential, deep submicron). Further investigate nonlinear effects and excitation: RF pulses with complex (esp. chirp), chaotic and ultrawideband modulation. Continue development of systems models which include: Voltage-frequency response statistics, RF gain, coupling and cascaded response in interconnected devices Effects from time delay and reflections in transmission linecoupled devices. Couple transfer characteristics devices and circuits to cables and enclosures.

34 IREAP Collaborations Titan-Jaycor Institute for Defense Analysis NRL ARL Philips Semiconductor Future: Univ. New Mexico, AFRL, DIA