E Series Power MOSFET

Transcription

1 E Series Power MOSFET SiHG73N6E PRODUCT SUMMRY (V) at T J max. 65 R DS(on) max. at 25 C (Ω) V GS = V.39 Q g max. (nc) 362 Q gs (nc) 8 Q gd (nc) 98 Configuration Single TO27C S G D ORDERING INFORMTION Package Lead (Pb)free Lead (Pb)free and Halogenfree G D S NChannel MOSFET FETURES Low figureofmerit (FOM) R on x Q g Low input capacitance (C iss ) Reduced switching and conduction losses Ultra low gate charge (Q g ) vailable valanche energy rated (UIS) Material categorization: for definitions of compliance please see PPLICTIONS Switch mode power supplies (SMPS) Power factor correction power supplies (PFC) Lighting Highintensity discharge (HID) Fluorescent ballast lighting Industrial Welding Induction heating Motor drives Battery chargers Renewable energy Solar (PV inverters) TO27C SiHG73N6EE3 SiHG73N6EGE3 BSOLUTE MXIMUM RTINGS (T C = 25 C, unless otherwise noted) PRMETER SYMBOL LIMIT UNIT DrainSource Voltage 6 GateSource Voltage V GS ± 3 V Continuous Drain Current (T J = 5 C) V GS at V T C = 25 C 73 I D T C = C 6 Pulsed Drain Current a I DM 236 Linear Derating Factor.2 W/ C Single Pulse valanche Energy b E S 23 mj Maximum Power Dissipation P D 52 W Operating Junction and Storage Temperature Range T J, T stg 55 to 5 C DrainSource Voltage Slope = V to 8 % 6 dv/dt Reverse Diode dv/dt d 8. V/ns Soldering Recommendations (Peak Temperature) c for s 3 C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. V DD = 5 V, starting T J = 25 C, L = 28.2 mh, R g = 25 Ω, I S = 2. c..6 mm from case. d. I SD I D, di/dt = 3 /μs, starting T J = 25 C. S5399Rev. E, 6Mar5 Document Number: 982

2 SiHG73N6E THERML RESISTNCE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junctiontombient R thj C/W Maximum JunctiontoCase (Drain) R thjc.2 SPECIFICTIONS (T J = 25 C, unless otherwise noted) PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static DrainSource Breakdown Voltage V GS = V, I D = 25 μ 6 V Temperature Coefficient Δ /T J Reference to 25 C, I D = 25 μ.65 V/ C GateSource Threshold Voltage (N) V GS(th) = V GS, I D = 25 μ 2 V GateSource Leakage I GSS V GS = ± 2 V ± n V GS = ± 3 V ± μ = 6 V, V GS = V Zero Gate Voltage Drain Current I DSS = 8 V, V GS = V, T J = 25 C μ DrainSource OnState Resistance R DS(on) V GS = V I D = Ω Forward Transconductance g fs = V, I D = 2 S Dynamic Input Capacitance C iss VGS = V, 77 Output Capacitance C oss = V, 32 Reverse Transfer Capacitance C rss f = MHz 5 Effective Output Capacitance, Energy pf Related a C o(er) 259 = V to 8 V, V GS = V Effective Output Capacitance, Time Related b C o(tr) 97 Total Gate Charge Q g GateSource Charge Q gs V GS = V I D = 2, = 8 V 8 nc GateDrain Charge Q gd 98 TurnOn Delay Time t d(on) Rise Time t r V DD = 8 V, I D = 2, 5 58 TurnOff Delay Time t d(off) V GS = V, R g = Ω ns Fall Time t f 2 8 Gate Input Resistance R g f = MHz, open drain.52 Ω DrainSource Body Diode Characteristics MOSFET symbol D Continuous SourceDrain Diode Current I S 73 showing the integral reverse G Pulsed Diode Forward Current I SM S p n junction diode 2 Diode Forward Voltage V SD T J = 25 C, I S = 36, V GS = V.9.2 V Reverse Recovery Time t rr ns Reverse Recovery Charge Q rr T J = 25 C, I F = I S = 2, di/dt = /μs, V R = 25 V μc Reverse Recovery Current I RRM 3.7 Notes a. C oss(er) is a fixed capacitance that gives the same energy as C oss while is rising from % to 8 % S. b. C oss(tr) is a fixed capacitance that gives the same charging time as C oss while is rising from % to 8 % S. S5399Rev. E, 6Mar5 2 Document Number: 982

3 SiHG73N6E TYPICL CHRCTERISTICS (25 C, unless otherwise noted) I D, DraintoSource Current () TOP 5 V V 3 V 2 V V V T J = 25 C 9 V 8 V 7 V 6 V 5 V , DraintoSource Voltage (V) Fig. Typical Output Characteristics R DS(on), DraintoSource On Resistance (Normalized) 3 I D = V GS = V T J, Junction Temperature ( C) Fig. Normalized OnResistance vs. Temperature I D, DraintoSource Current () TOP 5 V V 3 V 2 V V V 9 V 8 V T J = 5 C 7 V 6 V 5 V , DraintoSource Voltage (V) Fig. 2 Typical Output Characteristics Capacitance (pf) C oss C iss V GS = V, f = MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd C rss , DraintoSource Voltage (V) Fig. 5 Typical Capacitance vs. DraintoSource Voltage I D, DraintoSource Current () T J = 5 C T J = 25 C V GS, GatetoSource Voltage (V) Fig. 3 Typical Transfer Characteristics C oss (pf) C oss E oss Fig. 6 C oss and E oss vs. E oss (μj) S5399Rev. E, 6Mar5 3 Document Number: 982

4 SiHG73N6E V GS, GatetoSource Voltage (V) = 8 V = 3 V = 2 V Q g, Total Gate Charge (nc) I D, Drain Current () T J, Case Temperature ( C) Fig. 7 Typical Gate Charge vs. GatetoSource Voltage Fig. Maximum Drain Current vs. Case Temperature I SD, Reverse Drain Current () T J = 5 C T J = 25 C V GS = V V SD, SourceDrain Voltage (V), DraintoSource Breakdown Voltage (V) T J, Junction Temperature ( C) Fig. 8 Typical SourceDrain Diode Forward Voltage Fig. Temperature vs. DraintoSource Voltage Limited by R DS(on) * I DM Limited I D, Drain Current ().. Operation in this rea Limited by R DS(on) T C = 25 C T J = 5 C Single Pulse BVDSS Limited μs ms ms, DraintoSource Voltage (V) * V GS > minimum V GS at which R DS(on) is specified Fig. 9 Maximum Safe Operating rea S5399Rev. E, 6Mar5 Document Number: 982

5 SiHG73N6E Normalized Effective Transient Thermal Impedance. Duty Cycle = Single Pulse..... Pulse Time (s) Fig. 2 Normalized Thermal Transient Impedance, JunctiontoCase R D t p V GS D.U.T. V DD R G V DD V Pulse width µs Duty factor. % I S Fig. 3 Switching Time Test Circuit Fig. 6 Unclamped Inductive Waveforms 9 % V Q G Q GS Q GD % V GS t d(on) t r t d(off) t f V G Fig. Switching Time Waveforms Charge Fig. 7 Basic Gate Charge Waveform Vary t p to obtain required I S L Current regulator Same type as D.U.T. 5 kω R G V t p I S D.U.T. Ω V DD 2 V V GS.2 µf.3 µf D.U.T. V DS 3 m Fig. 5 Unclamped Inductive Test Circuit Fig. 8 Gate Charge Test Circuit I G I D Current sampling resistors S5399Rev. E, 6Mar5 5 Document Number: 982

6 SiHG73N6E Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period V GS = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 9 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see S5399Rev. E, 6Mar5 6 Document Number: 982

7 TO27C (High Voltage) Package Information 3 B R/2 Q E E/2 S 2 7 ØP (Datum B) Ø k M D B M ØP D2 2 x R (2) D D 2 3 D Thermal pad 5 L C 2 x b2 3 x b. M C M b Lead ssignments. Gate 2. Drain 3. Source. Drain 2 x e L See view B C DDE (b, b2, b) () Section C C, D D, E E MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX D E E b e 5.6 BSC.25 BSC b Ø k.25. b L b L b N 7.62 BSC.3 BSC b Ø P c Ø P c Q D R D S 5.5 BSC.27 BSC ECN: X33Rev. D, Jul3 DWG: 597 Notes. Dimensioning and tolerancing per SME Y.5M Contour of slot optional. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed.27 mm (.5") per side. These dimensions are measured at the outermost extremes of the plastic body.. Thermal pad contour optional with dimensions D and E. 5. Lead finish uncontrolled in L. 6. Ø P to have a maximum draft angle of.5 to the top of the part with a maximum hole diameter of 3.9 mm (.5"). 7. Outline conforms to JEDEC outline TO27 with exception of dimension c. 8. Xian and Mingxin actually photo. E View B C C Planting (c) E. M D B M View (b, b3, b5) Base metal c Revision: Jul3 Document Number: 936

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