Power MOSFET T C = 25 C

Transcription

1 Power MOSFET PRODUCT SUMMRY V DS (V) 200 R DS(on) () = 10 V 0.18 Q g max. (nc) 70 Q gs (nc) 13 Q gd (nc) 39 Configuration Single D I 2 PK (TO262) G D S D 2 PK (TO263) G G D S S NChannel MOSFET FETURES Surface mount Lowprofile throughhole vailable in tape and reel vailable Dynamic dv/dt rating 10 C operating temperature vailable Fast switching Fully avalanche rated Material categorization: for definitions of compliance please see Note * This datasheet provides information about parts that are RoHScompliant and / or parts that are nonrohscompliant. For example, parts with lead (Pb) terminations are not RoHScompliant. Please see the information / tables in this datasheet for details. DESCRIPTION Third generation power MOSFETs from Vishay provide the designer with the best combinations of fast switching, ruggedized device design, low onresistance and costeffectiveness. The D 2 PK is a surface mount power package capable of accommodating die size up to HEX. It provides the highest power capability and the last lowest possible onresistance in any existing surface mount package. The D 2 PK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. The throughhole version (SiHF60L) is available for lowprofile applications. ORDERING INFORMTION Package D 2 PK (TO263) D 2 PK (TO263) D 2 PK (TO263) I 2 PK (TO262) Lead (Pb)free and Halogenfree SiHF60SGE3 SiHF60STRLGE3 a SiHF60STRRGE3 a SiHF60LGE3 Lead (Pb)free IRF60SPbF IRF60STRLPbF a IRF60STRRPbF a Note a. See device orientation. BSOLUTE MXIMUM RTINGS (T C = 2 C, unless otherwise noted) PRMETER SYMBOL LIMIT UNIT DrainSource Voltage V DS 200 GateSource Voltage ± 20 V Continuous Drain Current at 10 V T C = 2 C 18 I T D C = 100 C 11 Pulsed Drain Current a, e I DM 72 Linear Derating Factor 1.0 W/ C Single Pulse valanche Energy b, e E S 80 mj valanche Current a I R 18 Repetitive valanche Energy a E R 13 mj Maximum Power Dissipation T C = 2 C 130 P T D = 2 C 3.1 W Peak Diode Recovery dv/dt c, e dv/dt.0 V/ns Operating Junction and Storage Temperature Range T J, T stg to 10 Soldering Recommendations (Peak temperature) d for 10 s 300 C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. V DD = 0 V, starting T J = 2 C, L = 2.7 mh, R g = 2, I S = 18 (see fig. 12). c. I SD 18, di/dt 10 /μs, V DD V DS, T J 10 C. d. 1.6 mm from case. e. Uses IRF60, SiHF60 data and test conditions. S16001Rev. E, 18Jan16 1 Document Number: 91037

2 THERML RESISTNCE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junctiontombient (PCB mounted, steadystate) a R thj 0 C/W Maximum JunctiontoCase (Drain) R thjc 1.0 Note a. When mounted on 1" square PCB (FR or G10 material). SPECIFICTIONS (T J = 2 C, unless otherwise noted) PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static DrainSource Breakdown Voltage V DS = 0 V, I D = 20 μ 200 V V DS Temperature Coefficient V DS /T J Reference to 2 C, I D = 1 m c 0.29 V/ C GateSource Threshold Voltage (th) V DS =, I D = 20 μ V GateSource Leakage I GSS = ± 20 V ± 100 n V DS = 200 V, = 0 V 2 Zero Gate Voltage Drain Current I DSS V DS = 160 V, = 0 V, T J = 12 C 20 μ DrainSource OnState Resistance R DS(on) = 10 V I D = 11 b 0.18 Forward Transconductance g fs V DS = 0 V, I D = 11 d 6.7 S Dynamic Input Capacitance C iss VGS = 0 V, 1300 Output Capacitance C oss V DS = 2 V, 30 pf Reverse Transfer Capacitance C rss f = 1.0 MHz, see fig. d 130 Total Gate Charge Q g 70 GateSource Charge Q gs I = 10 V D = 18, V DS = 160 V, see fig. 6 and 13 b, c 13 nc GateDrain Charge Q gd 39 TurnOn Delay Time t d(on) 1 Rise Time t r V DD = 100 V, I D = 18, 1 TurnOff Delay Time t d(off) R g = 9.1, R D =., see fig. 10 b, c ns Fall Time t f 36 Gate Input Resistance R g f = 1 MHz, open drain DrainSource Body Diode Characteristics Continuous SourceDrain Diode Current I MOSFET symbol S showing the 18 D integral reverse G Pulsed Diode Forward Current a I SM p n junction diode 72 Body Diode Voltage V SD T J = 2 C, I S = 18, = 0 V b 2.0 V Body Diode Reverse Recovery Time t rr ns Body Diode Reverse Recovery Charge Q rr T J = 2 C, I F = 18, di/dt = 100 /μs b, c μc Forward TurnOn Time t on Intrinsic turnon time is negligible (turnon is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. c. Uses IRF60/SiHF60 data and test conditions. S S16001Rev. E, 18Jan16 2 Document Number: 91037

3 TYPICL CHRCTERISTICS (2 C, unless otherwise noted) I D, Drain Current () 91037_01 Top 1 V 10 V 8.0 V 7.0 V 6.0 V V.0 V Bottom. V V 20 µs Pulse Width T C = 2 C V DS, DraintoSource Voltage (V) Fig. 1 Typical Output Characteristics, T J = 2 C R DS(on), DraintoSource On Resistance (Normalized) 91037_ I D = 18 = 10 V T J, Junction Temperature ( C) Fig. Normalized OnResistance vs. Temperature I D, Drain Current () 91037_ Top Bottom 1 V 10 V 8.0 V 7.0 V 6.0 V. V.0 V. V µs Pulse Width T C = 10 C V DS, DraintoSource Voltage (V). V Fig. 2 Typical Output Characteristics, T J = 17 C Capacitance (pf) 91037_ = 0 V, f = 1 MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd C iss C oss C rss V DS, DraintoSource Voltage (V) Fig. Typical Capacitance vs. DraintoSource Voltage 20 I D = 18 I D, Drain Current () 91037_ C 2 C 20 µs Pulse Width V DS = 0 V , GatetoSource Voltage (V), GatetoSource Voltage (V) 91037_ V DS = 100 V V DS = 0 V V DS = 160 V For test circuit see figure Q G, Total Gate Charge (nc) Fig. 3 Typical Transfer Characteristics Fig. 6 Typical Gate Charge vs. GatetoSource Voltage S16001Rev. E, 18Jan16 3 Document Number: 91037

4 20 I SD, Reverse Drain Current () 91037_07 10 C 2 C = 0 V V SD, SourcetoDrain Voltage (V) Fig. 7 Typical SourceDrain Diode Forward Voltage I D, Drain Current () 91037_ T C, Case Temperature ( C) Fig. 9 Maximum Drain Current vs. Case Temperature I D, Drain Current () 91037_ Operation in this area limited by R DS(on) 1 T C = 2 C T J = 10 C Single Pulse V DS, DraintoSource Voltage (V) 10 µs 100 µs 1 ms 10 ms Fig. 10a Switching Time Test Circuit V DS 90 % R g 10 V V DS Pulse width 1 µs Duty factor 0.1 % R D D.U.T. V DD Fig. 8 Maximum Safe Operating rea 10 % t d(on) t r t d(off) t f Fig. 10b Switching Time Waveforms 10 Thermal Response (Z thjc ) 91037_ Single Pulse (Thermal Response) t 1, Rectangular Pulse Duration (s) Fig. 10 Maximum Effective Transient Thermal Impedance, JunctiontoCase S16001Rev. E, 18Jan16 Document Number: P DM t 1 t 2 Notes: 1. Duty Factor, D = t 1 /t 2 2. Peak T j = P DM x Z thjc T C

5 1 V 10 V Q G V DS L Driver Q GS Q GD R g 20 V t p D.U.T. I S 0.01 Ω V DD V G Charge Fig. 12a Unclamped Inductive Test Circuit Fig. 13a Basic Gate Charge Waveform t p V DS Current regulator Same type as D.U.T. 0 kω 12 V 0.2 µf 0.3 µf D.U.T. V DS I S 3 m E S, Single Pulse Energy (mj) 91037_12c Fig. 12b Unclamped Inductive Waveforms Top Bottom I D V DD = 0 V Starting T J, Junction Temperature ( C) Fig. 13b Gate Charge Test Circuit I G I D Current sampling resistors Fig. 12c Maximum valanche Energy vs. Drain Current S16001Rev. E, 18Jan16 Document Number: 91037

6 Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period = 10 V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. V DS waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple % I SD Note a. = V for logic level devices Fig. 1 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see S16001Rev. E, 18Jan16 6 Document Number: 91037

7 Package Information TO263B (HIGH VOLTGE) (Datum ) 3 E L1 D H 1 2 C 3 C L2 B B Detail c2 B Gauge plane 0 to 8 L3 L L Detail Rotated 90 CW scale 8:1 H 1 B Seating plane 2 x b2 2 x e 2 x b M M B Plating b1, b3 c ± 0.00 M B Base metal E D1 (c) c1 Lead tip (b, b2) Section B B and C C Scale: none E1 View MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX D E b E b e 2. BSC BSC b H b L c L c L c L3 0.2 BSC BSC D L ECN: S82110Rev., 1Sep08 DWG: 970 Notes 1. Dimensioning and tolerancing per SME Y1.M Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed mm (0.00") per side. These dimensions are measured at the outmost extremes of the plastic body at datum.. Thermal PD contour optional within dimension E, L1, D1 and E1.. Dimension b1 and c1 apply to base metal only. 6. Datum and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO263B. Document Number: Revision: 1Sep08 1

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