Power MOSFET FEATURES APPLICATIONS. IRFS9N60APbF IRFS9N60ATRRPbF a IRFS9N60ATRLPbF a SiHFS9N60A-E3 SiHFS9N60ATR-E3 a SiHFS9N60ATL-E3 a

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1 Power MOSFET IRFS9N60, SiHFS9N60 PRODUCT SUMMRY V DS (V) 600 R DS(on) () V GS = 0 V 0.75 Q g max. (nc) 49 Q gs (nc) 3 Q gd (nc) 20 Configuration Single D D 2 PK (TO-263) G FETURES Low gate charge Q g results in simple drive requirement vailable Improved gate, avalanche and dynamic dv/dt ruggedness vailable Fully characterized capacitance and avalanche voltage and current Material categorization: for definitions of compliance please see Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-rohs-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. PPLICTIONS G D S S N-Channel MOSFET Switch mode power supply (SMPS) Uninterruptible power supply High speed power switching PPLICBLE OFF LINE SMPS TOPOLOGIES ctive clamped forward Main switch ORDERING INFORMTION Package D 2 PK (TO-263) D 2 PK (TO-263) D 2 PK (TO-263) Lead (Pb)-free and Halogen-free SiHFS9N60-GE3 SiHFS9N60TRR-GE3 a SiHFS9N60TRL-GE3 a Lead (Pb)-free Note a. See device orientation. Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Starting T J = 25 C, L = 6.8 mh, R g = 25, I S = 9.2 (see fig. 2). c. I SD 9.2, di/dt 50 /μs, V DD V DS, T J 50 C. d..6 mm from case. IRFS9N60PbF IRFS9N60TRRPbF a IRFS9N60TRLPbF a SiHFS9N60-E3 SiHFS9N60TR-E3 a SiHFS9N60TL-E3 a BSOLUTE MXIMUM RTINGS (T C = 25 C, unless otherwise noted) PRMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 600 V Gate-Source Voltage V GS ± 30 Continuous Drain Current V GS at 0 V T C = 25 C 9.2 I D T C = 00 C 5.8 Pulsed Drain Current a I DM 37 Linear Derating Factor.3 W/ C Single Pulse valanche Energy b E S 290 mj Repetitive valanche Current a I R 9.2 Repetitive valanche Energy a E R 7 mj Maximum Power Dissipation T C = 25 C P D 70 W Peak Diode Recovery dv/dt c dv/dt 5.0 V/ns Operating Junction and Storage Temperature Range T J, T stg -55 to 50 Soldering Recommendations (Peak temperature) d for 0 s 300 C S Rev. D, 02-May-6 Document Number: 9287 THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

2 IRFS9N60, SiHFS9N60 THERML RESISTNCE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junction-to-mbient R thj - 40 C/W Maximum Junction-to-Case (Drain) R thjc SPECIFICTIONS (T J = 25 C, unless otherwise noted) PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static Drain-Source Breakdown Voltage V DS V GS = 0, I D = 250 μ V V DS Temperature Coefficient V DS /T J Reference to 25 C, I D = m V/ C Gate-Source Threshold Voltage V GS(th) V DS = V GS, I D = 250 μ V Gate-Source Leakage I GSS V GS = ± 30 V - - ± 00 n V DS = 600 V, V GS = 0 V Zero Gate Voltage Drain Current I DSS V DS = 480 V, V GS = 0 V, T J = 25 C μ Drain-Source On-State Resistance R DS(on) V GS = 0 V I D = 5.5 b Forward Transconductance g fs V DS = 25 V, I D = S Dynamic Input Capacitance C iss VGS = 0 V, Output Capacitance C oss V DS = 25 V, Reverse Transfer Capacitance C f =.0 MHz, see fig. 5 rss pf V DS =.0 V, f =.0 MHz Output Capacitance C oss V GS = 0 V V DS = 480 V, f =.0 MHz Effective Output Capacitance C oss eff. V DS = 0 V to 480 V c Total Gate Charge Q g Gate-Source Charge Q gs I V GS = 0 V D = 9.2, V DS = 400 V see fig. 6 and 3 b nc Gate-Drain Charge Q gd Turn-On Delay Time t d(on) Rise Time t V DD = 300 V, I D = 9.2 r R g = 9., R D = 35.5 Turn-Off Delay Time t d(off) see fig. 0 b ns Fall Time t f Gate Input Resistance R g f = MHz, open drain Drain-Source Body Diode Characteristics MOSFET symbol Continuous Source-Drain Diode Current I S showing the D integral reverse G Pulsed Diode Forward Current a I SM p - n junction diode Body Diode Voltage V SD T J = 25 C, I S = 9.2, V GS = 0 V b V Body Diode Reverse Recovery Time t rr ns Body Diode Reverse Recovery Charge Q rr T J = 25 C, I F = 9.2, di/dt = 00 /μs b μc Forward Turn-On Time t on Intrinsic turn-on time is negligible (turn-on is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Pulse width 300 μs; duty cycle 2 %. c. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80 % V DS. S S Rev. D, 02-May-6 2 Document Number: 9287 THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

3 IRFS9N60, SiHFS9N60 TYPICL CHRCTERISTICS (25 C, unless otherwise noted) I D, Drain-to-Source Current () 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.7V 4.7V I D, Drain-to-Source Current () 00 0 T J = 50 C T J = 25 C 20µs PULSE WIDTH 0. T J = 25 C V DS, Drain-to-Source Voltage (V) Fig. - Typical Output Characteristics V DS= 50V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics I D, Drain-to-Source Current () 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.7V 4.7V 20µs PULSE WIDTH T J = 50 C 0 00 V DS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics r DS(on), Drain-to-Source On Resistance (Normalized) I D = 9.2 V GS = 0V T J, Junction Temperature ( C) Fig. 4 - Normalized On-Resistance vs. Temperature S Rev. D, 02-May-6 3 Document Number: 9287 THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

4 IRFS9N60, SiHFS9N60 C, Capacitance (pf) iss oss rss V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd C oss = C ds Cgd I SD, Reverse Drain Current () 00 0 T J = 50 C T J = 25 C V DS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage V GS = 0 V V SD,Source-to-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage V GS, Gate-to-Source Voltage (V) I = D 9.2 V DS = 480V V DS = 300V V DS = 20V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage I D, Drain Current () OPERTION IN THIS RE LIMITED BY R DS(on) 0us 00us ms 0ms TC = 25 C TJ = 50 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig. - Maximum Safe Operating rea S Rev. D, 02-May-6 4 Document Number: 9287 THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

5 IRFS9N60, SiHFS9N V DS R D I D, Drain Current () R g V GS 0 V Pulse width µs Duty factor 0. % D.U.T. - V DD Fig. 0a - Switching Time Test Circuit V DS 90 % T C, Case Temperature ( C) Fig. 8 - Maximum Drain Current vs. Case Temperature 0 % V GS t d(on) t r t d(off) t f Fig. 0b - Switching Time Waveforms Thermal Response (Z thjc ) 0. D = t 0.02 SINGLE PULSE t2 0.0 (THERML RESPONSE) Notes:. Duty factor D = t / t Peak T J = P DM x Z thjc TC t, Rectangular Pulse Duration (sec) PDM Fig. - Maximum Effective Transient Thermal Impedance, Junction-to-Case 5 V V DS t p V DS L Driver R g 20 V t p D.U.T I S 0.0 Ω - V DD I S Fig. 2a - Unclamped Inductive Test Circuit Fig. 2b - Unclamped Inductive Waveforms S Rev. D, 02-May-6 5 Document Number: 9287 THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

6 IRFS9N60, SiHFS9N60 E S, Single Pulse valanche Energy (mj) TOP BOTTOM I D Starting T, Junction Temperature ( J C) Fig. 2c - Maximum valanche Energy vs. Drain Current Current regulator Same type as D.U.T. 0 V Q G 2 V 0.2 µf 50 kω 0.3 µf Q GS Q GD D.U.T. V - DS V G V GS Charge Fig. 3a - Basic Gate Charge Waveform 3 m Fig. 3b - Gate Charge Test Circuit I G I D Current sampling resistors S Rev. D, 02-May-6 6 Document Number: 9287 THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

7 IRFS9N60, SiHFS9N60 Peak Diode Recovery dv/dt Test Circuit D.U.T. - Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer - - R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. - device under test - V DD Driver gate drive P.W. Period D = P.W. Period V GS = 0 V a D.U.T. I SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. V DS waveform Diode recovery dv/dt V DD Re-applied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 4 - For N-Channel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see S Rev. D, 02-May-6 7 Document Number: 9287 THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

8 Package Information TO-263B (HIGH VOLTGE) (Datum ) 3 4 E 4 L 4 D H 2 C 3 C L2 B B 5 Detail c2 B Gauge plane 0 to 8 L3 L L4 Detail Rotated 90 CW scale 8: H B Seating plane 2 x b2 2 x e 2 x b 0.00 M M B Plating 5 b, b3 c ± M B Base metal E D 4 (c) c 5 Lead tip (b, b2) Section B - B and C - C Scale: none E View - 4 MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX D E b E b e 2.54 BSC 0.00 BSC b H b L c L c L c L BSC 0.00 BSC D L ECN: S-820-Rev., 5-Sep-08 DWG: 5970 Notes. Dimensioning and tolerancing per SME Y4.5M Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.27 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum. 4. Thermal PD contour optional within dimension E, L, D and E. 5. Dimension b and c apply to base metal only. 6. Datum and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263B. Document Number: Revision: 5-Sep-08

9 N826 RECOMMENDED MINIMUM PDS FOR D 2 PK: 3-Lead (0.668) (6.29) (9.07) 0.45 (3.683) 0.35 (3.429) (5.080) (.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: pr-05

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