Evaluation Board for the AD8333 I/Q Demodulator AD8333-EVALZ

Transcription

1 Evaluation Board for the AD333 I/Q Demodulator AD333-EVALZ FEATURES Factory tested and ready to use SMA input and output connectors (7) Configurable jumpers for user options Phase select Provision for external reset Includes LNA input amplifier Internal clock buffer Summing amplifier to view sum of both channels or single Channel I and Channel Q outputs Compact surface-mount layout can be applied to user application APPLICATIONS Hands-on testing of the AD333 GENERAL DESCRIPTION The AD333-EVAL evaluation board enables the user to quickly become familiar with the operating characteristics and features of the AD333 dual I/Q demodulator and phase shifter. Jumpers provide a convenient means for exercising the user-selectable features of the AD333. The board is tested prior to shipment and shipped with the phase-encoding bits set to 0000 (no phase shift) for both channels. The LNA is set up for a 0 Ω source, and the VGA sections of the AD332 are disabled. Test points are provided along the signal path to facilitate signal tracing. EVALUATION BOARD Figure. Evaluation Board Actual Size Rev. B Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied as is and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. One Technology Way, P.O. Box 90, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... General Description... Evaluation Board... Revision History... 2 Introduction... 3 Features and Options... 3 Measurement Setup... Evaluation Board Schematic and Artwork... Board Layout...7 Ordering Information...9 Bill of Materials...9 Ordering Guide... 0 ESD Caution... 0 REVISION HISTORY 9/07 Rev. A to Rev. B Changes to Features and Options Section... 3 Changes to Figure 3... Changes to Table... 9 /07 Rev. 0 to Rev. A Changes to Figure... Changes to Figure 2... Changes to Figure... Changes to Figure and Figure Changes to Table... 9 Changes to Ordering Guide... 0 /0 Revision 0: Initial Version Rev. B Page 2 of 2

3 INTRODUCTION The AD333-EVAL evaluation board provides a platform for test and evaluation of the AD333 I/Q demodulator and phase shifter. The board is shipped fully assembled and tested, and the user need only connect appropriate signals to the RF input and flo SMA connectors. An AD332 is included with the board and acts as a buffer and bias supply for the AD333, converting single-ended signals to differential, centered at half the supply. A photograph of the board is shown in Figure and a schematic diagram is shown in Figure 3. The board requires dual V supplies capable of supplying 300 ma or greater. Except for the components shown in grayscale, the board is built and tested using all the components illustrated in Figure 3. FEATURES AND OPTIONS The evaluation board has several features and options that are configurable according to the specific needs of the user. Table lists the jumpers and their functions. Table. Jumper Functions Jumper Function Position ENBL Enable the AD333 Bottom = disable; top = enable PH0 Ch Phase 0 bit Top = 0; bottom = PH Ch Phase bit Top = 0; bottom = PH2 Ch Phase 2 bit Top = 0; bottom = PH3 Ch Phase 3 bit Top = 0; bottom = PH20 Ch 2 Phase 0 bit Top = ; bottom = 0 PH2 Ch 2 Phase bit Top = ; bottom = 0 PH22 Ch 2 Phase 2 bit Top = ; bottom = 0 PH23 Ch 2 Phase 3 bit Top = ; bottom = 0 RST Reset pin Left = reset; right = normal The Phase Bits The phase bits configure the channel for one of sixteen 22. increments from 0 to The increments increase according to a simple binary code from 0000 to embodied in the phase bits from 0 (0x0) to 337. (0xF). Table 2 lists the phase shift and corresponding code for each bit. The bits labeled 0 and correspond to low and high, respectively, on the silkscreen. Jumpers are provided to select the desired state. Enable and Reset Jumpers For normal operation, place a jumper in the upper position of ENBL. To disable the AD333, move the jumper to the lower position. For normal operation, the jumper for RST is in its right position. When the jumper is in the left position, the device counter is held in reset and no mixing occurs. Table 2. Phase Shift Select Codes Ф Shift PHx3 PHx2 PHx PHx Fixed Options Several options can be realized by adding or changing resistors. LNA Input Impedance The shipping configuration of the input impedance of the LNA is 0 Ω to match the output impedance of most signal generators. Input impedances of up to.7 kω are obtained by selection of the values of R9 and R0. Details concerning this circuit feature are found in the AD332 data sheet. For reference, Table 3 lists common values of input impedance and corresponding feedback resistor values. Table 3. LNA External Component Values for Common Source Impedances RIN (Ω) RFB, Nearest STD % Value (Ω) CSH (pf) k k None k None Rev. B Page 3 of 2

4 Current Summing The output transimpedance amplifiers, A through A, are configured as I-to-V converters to convert the output current of the AD333 to a voltage. The low-pass filters formed by the feedback components are designed for single-channel operation with ± V supplies. Optional R and R resistors are provided to sum the two channels. When R and R are installed, R2 and R3 are removed and the sum of the outputs is seen at the I and Q output SMA connectors. If large signal levels are expected, the feedback resistor and capacitor values, 77 Ω and 2.2 nf, can be halved and doubled, respectively, to optimize the output swing. The filter capacitor values can be changed if other frequencies are desired. Reset Input For normal operation, the reset input is high (no reset). To drive the reset with a dynamic signal, provision is made to connect a signal generator at the RST input. A 9.9 Ω, 003 surfacemount resistor can be installed at R to terminate the reset input for pulsed experiments. In this configuration, the jumper at RST is not used and must be removed to avoid loading the power supply. MEASUREMENT SETUP Figure 2 displays the connector and user-selectable jumper locations. A typical board and test equipment setup is shown in Figure. Two signal generators, a power splitter, and a ± V, 300 ma (minimum) power supply are required. Synchronize the signal generators for optimum results. Remember that the flo signal generator frequency is four times that of the nominal frequency of the RF source. For example, to detect signals with a nominal center frequency of MHz, an flo frequency of 20 MHz is applied to the oscillator input. For an applied RF signal of.0 MHz, the mix frequencies are 0 khz and 0.0 MHz. Because of the low-pass active filter of the transconductance amplifiers (A through A), 0 khz is observed at the output. Take care to avoid over driving the LNA input of the AD332. The LNA gain is 9 db (9. ) and the maximum output swing must not be exceeded; 0 dbm suffices for many experiments. The flo input is ac-coupled to a V LVDS buffer to provide an ideal interface to the AD333. The flo level is frequency dependent; consult the AD333 data sheet for minimum signal levels, then adjust the signal generator output level accordingly. f LO INPUT CHANNEL PHASE BITS +V, GND, V ENABLE CH I OUTPUT CH RF INPUT CH Q OUTPUT CH 2 RF INPUT CH 2 I OUTPUT CH 2 Q OUTPUT CHANNEL 2 PHASE BITS Figure 2. Evaluation Board Layout RESET Rev. B Page of 2

5 EVALUATION BOARD SCHEMATIC AND ARTWORK L PH3 H PH PH0 +V VPOS C2 L 20nH FB C 0. µf A AD02 C C27 pf R39 77Ω C2 2.2nF L7 20nHFB R0 77Ω C29 2.2nF R32 0Ω I R 00Ω C7 R3 9.9Ω PH2 PH3 COMM LOP LON LODC PH23 PH PH IN0 DUT AD IPO QPO QNO VNEG COMM PH2 I2NO PH2 PH22 PH23 H +V C RS T RS T Q2NO Q2PO I2PO VPOS H +V C 0. µf C3 0. µf C9 A3 AD02 C0 A AD02 C7 L 20nH FB C30 pf C R2 77Ω Q2 I R9 27Ω TP C TP3 C2 22pF VPS TP2 C C C 0.µ F TP C3 22pF VPS R0 27Ω C VPS R2 20Ω R2 20Ω GND GND2 GND3 GND PH2 + +V C7 0µF 0V V + TP TP L3 20nH FB H V C 0µF 0V ENBL + C VS V LOP ENBV LON VPS INH LMD LMD2 INH2 VPS2 LON2 Z AD332 C COMM VOH VOL VPSV VOL2 VOH2 COMM LOP2 RCLMP Z3 SPARE +V C2 7 NC C VPS IN R 3.kΩ R22 20Ω R23 20Ω C2 Z3 DS 90C0 C9 0. µf +V C3 nf 3 2 LOP R7.kΩ PH20 L TP7 TP L R OPT R OPT R2 0Ω R3 0Ω R OPT + A2 AD02 + C2 C32 2.2nF C2 pf R 77Ω C3 2.2nF VS C33 pf R33 0Ω IN2 VS R3 0Ω R3 0Ω VS Q V COM2 VIP2 VIN2 VCM2 MODE GAIN COM VIP VIN VCM HILO ENBL PH20 PH0 VPOS VPOS RF2P RFIP RF2N VPOS VPOS RSET RFIN ENBL C39 0.0µF C0 0.0µF L 20nH FB L2 20nH FB L 20nH FB Figure 3. Evaluation Board Schematic Rev. B Page of 2

6 TOP: SIGNAL GENERATOR FOR f LO INPUT TYPICAL SETTING: 20MHz SIGNAL V p-p BOTTOM: GENERATOR FOR RF INPUT TYPICAL SETTING:.0MHz POWER SUPPLY SYNCHRONIZE GENERATORS +V V POWER SPLITTER SIGNAL INPUT(S) Figure. Typical Board Test Connections (One Channel Shown) Rev. B Page of 2

7 BOARD LAYOUT AD333-EVALZ The AD333 evaluation board has four layers. The interconnecting circuitry is located on the outer layers with the inner layers dedicated as power and ground planes. Figure through Figure 9 illustrate the copper patterns. Figure. Component Side Copper Figure 7. Component Side Silkscreen Figure. Wiring Side Copper Figure. Ground Plane Rev. B Page 7 of 2

8 Figure 9. Power Plane Rev. B Page of 2

9 ORDERING INFORMATION BILL OF MATERIALS Table. Qty Name Description Reference Designator Mfg. Part Number Manufacturer IC AD02ARZ A to A AD02ARZ Analog Devices, Inc. 23 Capacitor 0. μf, V, 003, X7R C, C, C, C, C9, C, C2, C3, C003C0KRACTU KEMET Corporation C, C7, C2, C3, C, C2, C, C, C, C7, C, C9, C0, C, C2 2 Capacitor 22 pf, 0 V, %, 003 C2, C3 ECJ-VCH220J Panasonic 2 Capacitor 0 μf, 0 V, A size tantalum C7, C T9A0M00AS KEMET Corporation Capacitor 2.2 nf, 0 V, X7R, 0%, 003 C2, C29, C3, C32 ECJ-VBH222K Panasonic Capacitor pf, 0 V, 003 C27, C2, C30, C33 ECJ-VCH00C Panasonic 2 Capacitor 0.0 μf, 0%, 0 V, X7R, 003 C39, C0 003C3KAT2A AVX Corp. Capacitor nf, 00 V, 0%, 003, X7R C3 ECJ-VB2A02K Panasonic IC AD333 I/Q demodulator DUT AD333ACPZ-WP Analog Devices, Inc. 7 Connector SMA female PC mount, RA I, I2, IN, IN2, LOP, Q, Q RFX Amphenol 7 Ferrite Bead 20 nh, 003 L, L2, L3, L, L, L, L7 BLMBA70SND Murata Manufacturing Co. Resistor 00 Ω, %, / W, 003 R ERJ-3EKF000V Panasonic Resistor 0 Ω, %, /0 W, 003 R2, R3, R32, R33, R3, R3 ERJ-2GE0R00X Panasonic Resistor 3. kω, %, /0 W, 003 R ERJ-3EKF3.KV Panasonic Resistor. kω, %, /0 W, 003 R7 ERJ3EKF0V Panasonic 2 Resistor 27 Ω, / W, %, 003 R9, R0 ERJ-3EKF270V Panasonic Resistor 9.9 Ω, %, / W, 003 R3 ERJ-3EKF9R9V Panasonic Resistor 20 Ω, %, /0 W, 003 R22, R23, R2, R2 ERJ3EKF20R0V Panasonic Resistor 77 Ω, / W, %, 003 R39 to R2 ERJ-3EKF770V Panasonic 0 Header 3-pin 0.02" sq., 0." spacing ENBL, PH0, PH, PH2, PH3, Molex, Inc. PH20, PH2, PH22, PH23, RST Test Loop 0.2 diameter, red + V TP Components Corp. Test Loop 0.2 diameter, black GND to GND TP Components Corp. Test Loop 0.2 diameter, blue V TP-0-0-0P Components Corp. Test Loop 0.2 diameter, purple TP to TP, RST TP Components Corp. IC VGA AD332 Z AD332ACPZ Analog Devices, Inc. IC DRV LVDS dual differential Z3 DS90C0M National Semiconductor signal -lead SOIC PC Board 09-A009C Bumper Mount to wiring side of board SJ-7A (black) 3M 0 Jumper Install at ENBL: top, PH0: top, PH: top, PH2: top, PH3: top, PH20: bottom, PH2: bottom, PH22: bottom, PH23: bottom, RST: right; orient when board is in normal viewing position with IN and IN2 SMA connectors at left 7-00 FCI Rev. B Page 9 of 2

10 ORDERING GUIDE Model AD333-EVALZ Description Evaluation Board ESD CAUTION Z = RoHS Compliant Part. Rev. B Page 0 of 2

11 NOTES Rev. B Page of 2

12 NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB03-0-9/07(B) Rev. B Page 2 of 2