Diode-clamped multilevel converters with integrable gate-driver power-supply circuits

Transcription

1 Dioe-lampe Multilevel overters with Itegrable Gate-Driver Power-Supply ircuits S. Busquets-Moge, J. Rocabert, J.-. rebier 2, a J. Peracaula TEHNIAL UNIVERSITY OF ATALONIA Av. Diagoal, Barceloa, Spai Tel.: 34 / (93) Fax: 34 / (93) sergio.busquets@upc.eu URL: 2 GRENOBLE INSTITUTE OF TEHNOLOGY UMR 5529 BP Greoble, Frace Tel.: 04 / (76) Fax: 04 / (76) jea-christophe.crebier@g2elab.ipg.fr URL: Ackowlegemets This work was supporte by the Miisterio e Eucació y iecia, Mari, Spai, uer Grat TE Keywors «Multilevel coverters», «Pulse With Moulatio (PWM)», «Moulatio strategy», «Moolithic power itegratio», «System itegratio». Abstract Recet cotributios i pulse with moulatios (PWM) for multilevel ioe-clampe coverters eable the use of these coverters with passive frot-es, ay umber of levels, a small c-lik capacitors. Highly compact coverters esigs base o these topologies ca be evisioe. However, the esig of the gate-river power-supply for the multiple cotrolle semicouctor evices remais a importat issue to be aresse. This paper focuses o the esig of such circuits a the aalysis of the resultig multilevel coverter performace. A simple circuit coecte across each power switch a moolithically itegrable withi it is selecte. These circuits lea to simple, compact, a efficiet coverter esigs. The mai issues arisig from the operatio of the multilevel coverter with such circuits are aalyze, a both harware a software solutios are propose. I particular, a ew PWM strategy is presete. Experimetal results are provie verifyig the goo performace of all propose solutios. Itrouctio Multilevel coverters have opee a oor for avaces i the electric eergy coversio techology [], [2], ot oly i high power applicatios, but also for meium a low power esigs [3][5], sice they preset the avatages of a lower evice voltage ratig, a lower harmoic istortio, a higher efficiecy compare to covetioal two-level coverters. This paper focuses primarily o meium a low power applicatios. Amog multilevel topologies, ioe-clampe coverters are especially iterestig because of their simplicity (see Fig. ). The multiple voltage levels are obtaie through a series coectio of ietical capacitors. Recet cotributios i PWMs for ioe-clampe coverters [6] have eable the use of these coverters with passive frot-es, ay umber of levels a small c-lik capacitors. This opes the EPE Barceloa ISBN: P.

2 v - S a(22) S a() V c 3 S a S a() a b c v 2 v 2 S a2 S a Fig. : -level ioe-clampe topology with multiple legs. possibility of obtaiig compact coverter esigs base o these topologies. However, i orer to achieve a simple a itegrable coverter esig, oe of the first a most importat issues to aress is the esig of the multiple isolate gate-river power supplies require. There are several optios to geerate a isolate low regulate voltage to fee the active-evices gate rivers: low-power c-c coverters with galvaic isolatio, topologies usig coreless trasformers, charge pump circuits, etc. Fig. 2 shows three possible structures. Fig. 2(a) presets a solutio base o cc coverters with galvaic isolatio extractig the eergy from the c-lik capacitors. Every c-lik capacitor fees two gate rivers. The two c-c coverter outputs are isolate. apacitor sxi stores the eergy ecessary to rive evice S xi. This structure has the beefits of a equally istribute eergy withrawal from the c-lik capacitors. The problem is the ee for galvaic isolatio for all c-c coverters, which usually calls for the itrouctio of high-frequecy trasformers. This solutio is therefore iscare because of its complexity, size a cost. A alterative solutio without the ee of galvaic isolatio is show i Fig. 2(b). This structure is base o the bootstrap charge pump cocept, which has bee alreay applie i multilevel coverters [3], [5]. The sigle low-voltage power supply require by the structure ca be obtaie from the c-lik capacitor, as show i Fig. 2(b). However, these topologies are ot aequate to be moolithically itegrate withi the active evices [7], ca cause electromagetic iterferece problems, a are asymmetric from both the poit of view of topology a operatio. Recetly, other alterative topologies coecte across the power evice a beig fully itegrable withi it have bee propose [7][0]. From these topologies, the structure i Fig. 2(c) is propose. The gate-river power-supply capacitors are fe from the eergy available across the switch whe it turs off. There are several optios to implemet the voltage regulator moules i Fig. 2(c) [7] [0]. These circuits have bee teste i simple buck a flyback c-c coverters. This paper explores whether this cocept ca be applicable to a multilevel ioe-clampe coverter a evaluates the performace of such coverters. Gate-Driver Power-Supply Topology a Operatio Priciple The selecte gate-river power-supply topology is show i Fig. 3 [8]. The eergy to rive the evice is obtaie from the eergy that is otherwise lost urig the mai power switch S tur-off trasitio a, evetually, from the correspoig c-lik capacitor coecte across the switch urig its off state. This eergy is store i capacitor s. The curret chargig capacitor s flows through the auxiliary metal oxie semicouctor fiel effect trasistor (MOSFET) S a. The zeer ioe D z, polarize by resistor R, limits the value of v s a the blockig ioe D b prevets the ischargig of s whe the mai power switch S is o. EPE Barceloa ISBN: P.2

3 - c-c cov. with galvaic isol. S x(22) sx(22) S x(23) sx(23) sx(22) sx(2) S x(22) sx() S x() V c 3 V c sx S x 2 c-c cov. with galvaic isol. sx4 sx3 S x4 S x3 2 sx3 c-c cov. with galvaic isol. (a) sx2 sx S x2 S x Voltage regulator S x(22) sx(22) c-c cov. without galvaic isol. (b) sx2 sx S x2 S x V c Voltage regulator Voltage regulator (c) Fig. 2: Gate-river power-supply structures for coverter leg x{a, b, c} (clampig ioes omitte). (a) Structure base o c-c coverters with galvaic isolatio. (b) Structure 2 base o the bootstrap techique. (c) Structure 3 usig voltage regulators coecte across the active evices. sx2 sx S x2 S x Gate Driver Power Supply R xi S axi otrol Sigal D D zxi D bxi sxi v sxi Gate Driver S xi S v DSxi Fig. 3: Gate-river power-supply circuit (x{a, b, c}, i{, 2,, 22}). EPE Barceloa ISBN: P.3

4 Iitial overter otrol Ajustmet of the Gate-Driver Power-Supply apacity To operate the coverter, the PWM strategy presete i [6] a the capacitor-voltage balacig cotrol presete i [] are iitially selecte. This cotrol scheme presets the beefit of guarateeig the clik capacitor voltage balace i every switchig cycle provie that the aitio of the output leg currets equals zero, a thus, eables the operatio of a -level coverter with low c-lik capacitace values. Fig. 4(a) presets the correspoig leg uty-ratio patter ( xy, correspoig to the leg x uty ratio of coectio to c-lik poit y) for a three-leg coverter at a give moulatio iex value (m[0,] for liear moulatio) over a lie cycle (: ac-sie lie-cycle agle). The ifferet power switch utyratios, Sxi, ca be easily compute from these waveforms. It is importat to ote that the two most ier evices of each coverter leg (S x a S x() ) remai o for 20º itervals every lie cycle sice the correspoig uty-cycle values Sx Sx j 2 - j xj xj () are equal to the uity urig these itervals. This prevets the correspoig capacitor s from beig charge urig this perio. I orer to prevet its ischargig below the miimum voltage value for correct operatio of the gate river, it is require to select a capacitace value s higher tha for other evices, for which the switch uty-ratio is always lower tha the uity a, therefore, the correspoig capacitor s is recharge every switchig cycle. This require value of sx a sx() will epe upo the ac-sie lie-cycle frequecy (f o ). The lower the frequecy is, the higher the require value of these two capacitors per leg. The performace of this cotrol scheme has bee teste i the three-level three-leg coverter prototype show i Fig. 5. The compoets of the gate-river power-supply are outlie i Table I. The coverter is operate i iverter moe with a sigle c power supply coecte to c-lik poits a 3 a a wyecoecte three-phase series R-L loa coecte to the ac sie. The computatio of the six iepeet phase uty-ratios is performe by the embee PowerP of Space DS03. This iformatio is set to a Altera EPF0K70 programmable logic evice i charge of geeratig the twelve switch cotrol sigals x x 0.8 x x (2) x2 = = (2) x() 0.4 (2) x2 = = (2) x() (eg) (eg) (a) (b) Fig. 4: Leg x uty-ratio patter for a -level three-leg coverter (m = 0.75). (a) Origial PWM scheme. (b) Moifie PWM scheme with offset = EPE Barceloa ISBN: P.4

5 3 S a4 S b4 S c4 V c v 2 2 S a3 S b3 S c3 S a2 S b2 S c2 v S a S b S c i a i b v ab i c a b c (a) (b) Fig. 5: Three-level three-leg c-ac coverter. (a) Topology. (b) Prototype usig 50 V MOSFETs as evices S xi. Table I: Gate-river power-supply compoets ompoet Symbol Selecte ompoet S a IRF5802TR (50 V, 0.9 A) D b 0BQ040 (40 V, A) R 0 k D z BZX8522 (22 V) s 330 F, polypropilee Fig. 6 shows the experimetal results obtaie with this cotrol scheme a aig 0 F electrolytic capacitors to sx2 a sx3. It ca be observe that the coverter is operatig correctly at a high moulatio iex value (m = 0.95). Note the footprit of the selecte PWM o the lie-to-lie voltage v ab. We ca also observe that urig a 20º perio over the lie cycle, capacitor sa2 ischarges because the correspoig evice is o. However, the aitio of 0 F capacitors to these ier switch positios prevets the supply voltage from fallig beyo the miimum allowe value. Oce the evice starts switchig o a off i every switchig cycle, the capacitor is quickly recharge. As metioe earlier, the value of the require capacitace epes o the output lie-cycle frequecy. Typically, a relatively high value will be eee, which implies that the rechargig process will take place essetially urig the off state of the mai evice without recyclig tur-off losses a therefore presetig a lower efficiecy. Aitio of a Auxiliary Bootstrap ircuit A alterative solutio to icreasig the value of s for the two most ier evices of each leg is the itrouctio of two ioes per leg to implemet the bootstrap circuit of Fig. 7. This bootstrap circuit ivolves three power evices per leg: S x, S x(), a S x(2). Durig the 20º i which S x() is o, its correspoig gate-river power-supply capacitor is fe from the eergy store i sx(2). Durig the 20º i which S x is o, its correspoig gate-river power-supply capacitor is fe from the eergy store i sx(). EPE Barceloa ISBN: P.5

6 v ab v sa2 i a i b i c v DSa2 Fig. 6: Experimetal results for v ab, i a, i b, i c, v sa2, a v DSa2 i the followig coitios: V c = 50 V, m = 0.95, = 55 F, sx = sx4 = 330 F, sx2 = sx3 = 330 F 0 F (x{a, b, c}), switchig or carrier frequecy f s = 5 khz, a a liear a balace loa with per-phase impeace Z L = º (series R-L loa). D ax2 D ax sx sx() sx(2) S x S x() S x(2) Fig. 7: Auxiliary bootstrap circuit. Fig. 8 shows the experimetal results of this ew cofiguratio with the three-level coverter prototype of Fig. 5 a all gate-river capacitors equal to 330 F. The coverter is operatig correctly. However, ote the voltage rop i v sa2 a v sa3 ue to the couctio voltage rop i the auxiliary ioes D aa a D aa2. Aitioally, these two extra ioes per leg caot be moolithically itegrate withi the power evices. v ab v sa4 v sa3 i a i b i c v sa2 v sa Fig. 8: Experimetal results for v ab, i a, i b, i c, v sa, v sa2, v sa3, a v sa4 i the followig coitios: V c = 50 V, m = 0.95, = 55 F, sx = sx2 = sx3 = sx4 = 330 F (x{a, b, c}), auxiliary ioes D ax a D ax2 N448, switchig or carrier frequecy f s = 5 khz, a a liear a balace loa with per-phase impeace Z L = º (series R-L loa). EPE Barceloa ISBN: P.6

7 Moifie overter otrol The previous coverter cotrol scheme performs satisfactorily, but requires a icrease value of s for the two most ier evices of each leg or the aitio of two ioes per leg to implemet the auxiliary bootstrap circuit of Fig. 7. I orer to be able to operate with the cofiguratio of Fig. 2(c), with the same low s value for all evices, a without the ee of extra ioes, therefore obtaiig a simple moular esig, a ew PWM strategy is propose moifyig the previous oe. The equatios escribig this ew PWM scheme with referece to the origial [6] are ' x x offset ' x x offset ' 2 (2) offset xi xi 2 x a, b, c; i 2, 3,..., where offset is give, i priciple, a small costat value over time. Fig. 4(b) presets the leg uty-ratio patter for offset = It ca be see that the origial uty-ratio waveforms x a x are slightly shifte upwars, so that both leg uty-ratios are always greater tha zero. This is equivalet to employig switchig states a i approximatig the referece vector whe efiig the PWM strategy with the ai of a space vector iagram [6]. This moificatio oes ot affect the switchig-frequecy average voltage waveforms sice a zero average offset is applie to the three coverter leg voltages v x. The propose PWM strategy has bee teste i the prototype of Fig. 5 with s = 330 F for all gate-river power-supply capacitors. Fig. 9 a Fig. 0 preset the experimetal results. It ca be observe that the coverter is performig satisfactorily for both high (Fig. 9(a)) a low (Fig. 9(b)) moulatio iex values. Note the ew footprit of the PWM scheme o the lie-to-lie voltage v ab a that the c-lik capacitor voltages v a v 2 are balace i every switchig cycle. Fig. 0 shows the gate-river powersupply capacitor voltages a rai-to-source voltages of evices S a2 a S a4 (see Fig. 5(a)). A few switchig perios are show correspoig to the 20º regio i Fig. 4(b). apacitor sa2 is correctly recharge every switchig cycle espite the short perio of time evice S a2 is off. The ew PWM scheme allows operatig with the gate-river power-supply structure of Fig. 2(c) a small s capacitors regarless of the output lie-cycle frequecy. However, this avatage is obtaie at the expese of icreasig the umber of switchig trasitios per switchig cycle (a hece, the switchig losses), icreasig the ac-sie voltage harmoic istortio, a reucig the maximum value of the moulatio iex i the liear moulatio rage. First of all, the percetage icrease i per-switchig-cycle switchig trasitios of the moifie PWM strategy with referece to the origial PWM strategy is 2 st 00 %, (3) 3 5 Fig. eploys this percetage icrease as a fuctio of the umber of levels. It ca be see that st ecreases rapily as the umber of levels icreases, a so oes the associate icrease i switchig losses. Therefore, for a value of large eough the icrease i switchig losses might be eeme ot sigificat. EPE Barceloa ISBN: P.7

8 v ab v a v 2 v i a i b i c i a v ab (a) v a v 2 v i a i b i c i a (b) Fig. 9: Experimetal results for v ab, i a, i b, i c, v, v 2, a v a i the followig coitios: V c = 50 V, = 55 F, sx = sx2 = sx3 = sx4 = 330 F (x{a, b, c}), offset = 0.02, f s = 5 khz, a a liear a balace loa with per-phase impeace Z L = º (series R-L loa). (a) m = (b) m = 0.4. v sa4 v DSa4 v sa2 v DSa2 Fig. 0: Experimetal results for v sa2, v sa4, v DSa2, a v DSa4 i the same coitios as i Fig. 9 a m = EPE Barceloa ISBN: P.8

9 st (%) Fig. : Percetage icrease i per-switchig-cycle switchig trasitios of the moifie PWM strategy with referece to the origial PWM strategy, as a fuctio of the umber of levels. Seco, Fig. 2 presets the total harmoic istortio (THD) i the output lie-to-lie voltage of a fivelevel three-leg ioe-clampe coverter as a fuctio of the moulatio iex for both the origial a moifie PWM schemes. It ca be observe that there is a clear icrease of the THD i the ew PWM strategy, especially for high values of m. However, this icrease may ot be sigificat for may applicatios. Fially, sice all uty-ratios must have a value betwee 0 a, the maximum value of the moulatio iex i the liear moulatio rage with the moifie PWM strategy is m max 2 offset (4) I geeral, this ecrease i the maximum value is ot sigificat sice a small value of offset ca be typically selecte. The miimum value of offset is etermie from the river a evice techology. 50 THD (%) Moifie PWM ( offset = 0.02) Origial PWM m Fig. 2: THD i the lie-to-lie voltage of a five-level three-leg ioe-clampe coverter as a fuctio of the moulatio iex m. oitios: f s / f o = 00 a harmoics cosiere up to 40 f s. EPE Barceloa ISBN: P.9

10 oclusio This paper proves the feasibility of itegratig the gate-river power supply i all evices of a multilevel ioe-clampe coverter. These trasformerless circuits avoi the ee of icorporatig covetioal isolate c-c power supplies to fee each evice river a, hece, lea to simple a compact multilevel coverter esigs, more efficiet tha covetioal two-level coverters. The use of existig PWM strategies for operatig the multilevel coverter requires a icrease of two gate-river power-supply capacitaces per leg or the itrouctio of two bootstrap ioes per leg. Alteratively, the ovel PWM strategy presete ca be use i orer to achieve a simple moular esig, iepeet from the output ac voltage frequecy a without the ee of aitioal compoets. This solutio combies the beefits of beig moular a itegrable, a esures that the eergy require to rive the switches is raw homogeously from all c-lik capacitors. The rawbacks from this ew PWM with regar to switchig losses are ot sigificat for a umber of levels large eough. The icrease i ac-sie voltage istortio a the ecrease i maximum moulatio iex may ot be sigificat for may applicatios. Refereces [] J. Roríguez, J. Lai, a F. Peg: Multilevel iverters: a survey of topologies, cotrols a applicatios, IEEE Tras. I. Electro., vol. 49, pp , Aug [2] L. G. Fraquelo, J. Roriguez, J. I. Leo, S. Kouro, R. Portillo, a M. A. M. Prats: The age of multilevel coverters arrives, IEEE I. Electro. Magazie, vol. 2, pp , [3] B. A. Welchko, M. B. e Rossiter orrea, a T. A. Lipo: A three-level MOSFET iverter for low-power rives, IEEE Tras. I. Electro., vol. 5, pp , Jue [4] R. Teichma a S. Beret: A compariso of three-level coverters versus two-level coverters for low-voltage rives, tractio, a utility applicatios, IEEE Tras. I. Applicat., vol. 4, pp , May-Jue [5] S. A. Molepo a H. u T. Mouto: A flyig capacitor multilevel iverter with bootstrap-powere MOSFET gate rive circuits, i Proc. IEEE Power Electroics Specialists of., 2002, pp [6] S. Busquets-Moge, S. Alepuz, J. Rocabert, a J. Boroau: Pulsewith moulatios for the comprehesive capacitor voltage balace of -level ioe-clampe coverters, i Proc. IEEE Power Electroics Specialists of., 2008, pp [7] R. Mitova, J.-. rebier, L. Aubar, a. Schaeffer: Fully itegrate gate rive supply arou power switches, IEEE Tras. Power Electro., vol. 20, pp , May [8] J.-. rebier a N. Rouger: Loss free gate river uipolar power supply for high sie power trasistors, IEEE Tras. Power Electro., vol. 23, pp , May [9] N. Rouger a J.-. rebier: Towar geeric fully itegrate gate river power supplies, IEEE Tras. Power Electro., vol. 23, pp , July [0] N. Rouger, J.-. rebier, H. Tra Mah, a. Schaeffer: Towar itegrate gate river supplies : Practical a aalytical stuies of high-voltage capabilities, i Proc. IEEE Power Electroics Specialists of., 2008, pp [] S. Busquets-Moge, S. Alepuz, J. Boroau, a J. Peracaula: Voltage balacig cotrol of ioe-clampe multilevel coverters with passive frot-es, IEEE Tras. Power Electro., vol. 23, pp , July EPE Barceloa ISBN: P.0