ESD Design & Qualification for Integrated Circuits

Transcription

1 Design & Qualification for Integrated Circuits Vesselin Vassilev, Ph.D. General Chair 2010 EOS/ Symposium October 2-8, 2010, John Ascuaga s Nugget Resort, Sparks (Reno), NV NovoRell 09 10

2 ElectroStatic Discharge is everywhere circuit ~ 100mW power levels pulse ~ 10W ~ times! is a major failure mode for the electronic equipment nowadays 10 Vesselin Vassilev vesselin.vassilev@novorell.com Tutorial

3 10 Vesselin Vassilev Tutorial v dd IC OPERATING REGIONS: 1. Non- operation see figure : boundaries of the design space/soa - depends on technology and structure design Current Circuit safe operation 2.) IN device power to failure v ss ) IC OUT In events, circuit transient IV must be within the SOA region 2 - depends on cell AND protected circuit performance and interactions I LU normal operation non- 1.) circuit transient IV I/O driver failure 1.) V DD V BR, V ox BR Voltage device : ROBUST, GENTLE, FAST and INVISIBLE : deviate the stress from the IC Every clamp = current switch: CLOSED in, OPEN in normal conditions

4 10 Vesselin Vassilev Tutorial PROTECTION CIRCUIT ELEMENTS I(A) BVox 2 1 Forward Diode ~ 5 Ohms SCR latch ~1-2 Ohms RC timed NMOS Lateral NPN Snapback ~ 2-5 Ohms Lateral PNP Snapback ~ Ohms PN Diode Reverse Biased ~ Ohms V(Volts) Any type of clamp must protect the gate oxide with a breakdown of Bvox.

5 design kit Implementation in Analog Artist/CADENCE 10 Vesselin Vassilev Tutorial model parameters components schematic views TLP 200mA The extensions of a given design kit with models allows designers to simulate and optimize the whole circuit

6 Power Pad clamp clamp Optimization of the protection in a digital Output Pad IC Pad Logic V g1 PMOS C dg NMOS Output Pad driver PMOS R iso NMOS V DD V DD I/O V SS I/O V SS I TOTAL I NMOS driver I prot 100p 1n 10n 100n time [s] 10 Vesselin Vassilev vesselin.vassilev@novorell.com Tutorial OUT V g2 2kV Human Body Model stress between OUTPUT and VSS IO Initial design (no gate coupling) I [A] 2,0 1,6 1,2 0,8 0,4 0,0 The protection is too slow and does not activate, the output NMOS takes all the stress not OK I TOTAL I NMOS driver I prot I [A] 100p 1n 10n 100n time [s] Improved design (fixed RC gate coupling The protection activates OK and conducts all the stress current after 10ns The use of simulation enabled PDK allows to optimize and verify the operation of the protection circuit prior design release 2,0 1,6 1,2 0,8 0,4 0,0

7 10 Vesselin Vassilev Tutorial NOVORELL s protection approach for RF I/O s Two possible -for-rf Design Methodologies Plug and Play independent RF and designs; fit (shrink) devices into the available RF design window to meet the RF specs; Limited performance possible -RF Circuits co-design full circuit optimization; structure is part of the RF design space, thus stronger cell can be used. HIGH RF specs can be achieved RF performance spec e.g. Gain, Noise, freq RF front end Depending on the design space and specific RF product spec, different approaches are feasible RF IN design window defined by =(RFspec used RF design space) design space shared with the RF design space (the cell is part of the RF functionality) RF IN RF performance spec e.g. Gain, Noise, freq RF front end RF design space defined by the RF technology & design constraints RF design space defined by the RF technology & design constraints

8 10 Vesselin Vassilev Tutorial Generic common source LNA matching approach V dd V dd L load RF OUT L load RF OUT M 2 M 2 V bi2 V bi2 R S R in ' =R S R eq R S V in R S RF IN R in =R S L g C par M 1 C gs R S V in RF IN match L g C par M 1 C gs A L s A' A a.) b.) L s direct match indirect match The presence of the device imposes an upper limit on the allowable Rin; power match is not always possible R in ( = R ) ᆪ s 1 Cpar 2 ωcpar(1 + ) C gs

9 System level design The PCB board and discrete components act as filters which change in unknown way the input waveform Large Voltage transients can occur inside the PCB board IEC waveform on IC - Not defined! Use discrete components to filter input IEC signal IEC pulse 10 Vesselin Vassilev vesselin.vassilev@novorell.com Tutorial

10 IEC Protection design = IC + PCB co-design! 10 Vesselin Vassilev vesselin.vassilev@novorell.com Tutorial IEC filter PCB IC

11 Cell Level Checks 10 Vesselin Vassilev Tutorial Verify that correct version of the device/design kit/cell/library is being used when using standard library cells or parameterized cells (PCELLs). Verify compliance of individual and multiple cell devices with geometrical rules. Verify protection element between I/O and power (VDD, VSS) rails, including correct device polarity, within I/O cell. Verify power clamp between power rails (VDD, VSS), including correct device polarity, within I/O or supply cell. Verify trigger circuit implementation in transient-triggered designs. Verify termination cell implementation. Verify interface cell implementation. Verify device rating compliance in cell implementation. Verify robustness of metal lines and interconnects along the protection discharge path. Verify compliance of extracted metal resistances of the paths within the cell with allowed design limits. Verify implementation of secondary protection scheme