serial-to-parallel converter

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1 Rapid single ux quantum fast-packet switching element mitry Y. Zinoviev State University of New York, epartment of Physics Stony Brook, New York ABSRAC We present the design of a Rapid Single-Flux Quantum (RSFQ) N N fast-packet M switching element that can be used in AM packet switches. Using simple 3:5? m niobium-trilayer technology, this device would allow the external exchange rate f e = 10 Gb=sec per switched channel at the internal clock frequency f 0 = 40 GHz. he element structure implies that a separate unit provides the address of the destination channel for each packet and resolves packet contentions. Keywords: superconductivity, RSFQ, AM, fast-packet switch. 1. INROUCION Superconducting electronics based on Josephson eect provides powerful means for ultra-high-performance handling of digital data. Presently the development of this eld is focused on the so-called Rapid Single-Flux Quantum devices. 1 In RSFQ, data are represented as a presence or absence of magnetic ux quanta 0 2:07 10?15 W b between two successive clock pulses, and superconductor quantum interferometers are used for data storage and processing. RSFQ logical units can transfer and process data at rates up to hundreds Gb/s. Because the main dierence between an AM switch and a packet switch used in the computer networks is speed, 2 it is natural to use RSFQ devices in the AM switching. A number of attempts has been made to implement telecommunication equipment in various superconducting technologies. 3{5 Yet, this seems to be the rst purely RSFQ architecture of a bus-type fast-packet switching element 6,7 with time-division multiplexing (M). 2. SWICHING ELEMEN OPERAION OVERVIEW clock out N input channels bit concentrator serial-to-parallel converter frequency multiplier "Slow" clock "Fast" clock ata Address input buffers N output channels clock in Figure 1. Overall structure of an N N switching element. In our M switch, the bit concentrator picks up one bit at a time from one of N input buers in the required order and places it into the corresponding slot of the shared communication bus serial-to-parallel converter (see

2 Figure 1). As soon as all (at most N) bits from the incoming channels are pushed to the converter, its contents is read out in parallel into the output channels. he throughput of the converter denes the overall performance of the switch. he switch operation is controlled by three clock signals. External, or \slow" clock runs at frequency f e. It determines the packet arrival rate in each channel. he same clock signal phase-shifted by 2 (log 2 N) =N controls the output serial-to-parallel interface. he internal shared bus operates at the higher frequency f 0 = N f e. he corresponding internal, or \fast" clock, is produced by the frequency multiplier (see section 3.4). "fast" clock "slow" clock address load input buffer pick-up from 1 pick-up from 2 pick-up from 3 pick-up from 4 output buffer Figure 2. Sample operating sequence of a 4 4 switching element. \address" address at any serial line; \load" signal at any \load" line. he following example (Figure 2) illustrates the time sequence of events in a 4 4 switching element. For the sake of simplicity we assume that the packets are head-aligned, i.e. their rst bits arrive at the same clock period. his has not to be the case in real operation mode, when a newly arrived packet can immediately be routed to the destination channel. One can see that each external \slow" clock derives N internal \fast" clocks. he rst log 2 N \slow" time slots are used to accept the physical address bits followed by the \load" signal. uring the next \slow" clock periods incoming packets are read bit-by-bit, so that only one bit (under the contention-free assumption) is taken from the input buer to the concentrating tree and pushed to the FIFO-like serial-to-parallel converter within each \fast" clock period. Lastly, the (N + 1)th \slow" clock ushes the contents of the converter to the outgoing channels. he switch timing is organized in a counterow pipelined manner: the clock and the data always run in the opposite directions. It takes at most (log 2 N + N) \fast" clock periods to advance a bit from an input buer to the destination slot in the output converter, so that the read-out signal should be delivered to the serial-to-parallel converter at the (log 2 N)th \fast" clock period rather than immediately. his delay aects only the latency of the switch, not its throughput. he proposed switching element requires an external unit ACR (address translator and contention resolver, see Figure 3a) which should extract the VCI/VPI or its equivalent from the packet (cell) header, translate it and provide the translated physical address for each channel via a separate line. he physical address has a predetermined length L = log 2 N bits, yet for the sake of simplicity a signal at an additional line (\load" strobe) indicates the end of the address (see also section 3.1). For the same reason the rst proposed design of the switching element does not have internal congestion control. It is implicitly assumed that the ow of incoming packets is contention-free (this condition can be achieved at the ACR stage, say, by keeping track on the used entries in look-up tables). ue to the M nature of the element, it has a certain limitation on the number of switched channels: N f 0 f e ; (1) However, this constraint can be overcome by organizing several elementary N N switches in more complex hierarchical (N 2 N 2, etc.) switching fabrics (see Figure 3b).

3 clock ACR in clock SN N*N inputs N*N outputs address "load" lines strobes a) out clock b) 2*log(N) address lines Figure 3. a) op-level conguration of an AM switch (simplied). ACR address translation and contention resolution module, SN switching network or packet-switching element. b) Building a N 2 N 2 switching network from N N elements INPU BUFFERS 3. SWICH PARS An input buer is associated with each incoming channel. It performs simultaneously buering and routing functions which are controlled by dierent (\slow" and \fast") clock signals. he input buer consists of three major parts (see Figure 4a): a FIFO-type temporary address storage (S2P) organized as a serial-to-parallel converter, a counter 8 modulo N with a loading interface (CN) and a data bit storage buer (BUFF). he temporary address storage sequentially accepts the address from the input A, one address bit per one \slow" clock IS, and ushes it to the counter part whenever the \load" (L) signal arrives. he storage is designed as a shift register built up of RSFQ analogs of the \call" cell 9 rather than of \conventional" RS ip-ops, so that one \reset" branch of each cell is used for transferring bits along the register, and the other is used for parallel read-out. he ACR module assigns a number A to each input channel (and hence each input packet arriving to the input) according its look-up tables: A = O i? 1; i = 1 : : : N; (2) where O i is the number of the destination channel, starting from 1, from left to right (see Figure 1). he \load" signal causes the corresponding binary code A (the least signicant bit placed to the left-most ip-op) to be written to the counting loop CN as its initial state. hus, we can speak about two modes of the input buer: a programming mode and a counting mode. he signal L switches the input buer from the further mode to the latter mode explicitly, while the opposite transmission is implicit and takes place when the last bit of the routed packet leaves the storage. he \fast" clock permanently circulates in the counting loop causing the generation of the \carry" signal each time the contents of all the upper ip-ops change to zero. he period of this \carry" signal is N=f 0 = f e, i.e., it coincides with the period of the \slow" clock, while its initial oset depends on A and, in turn, determines the number of the M slot assigned to the data bit stored in the BUFF ip-op. Note that when in the counting mode, the S2P part of the input buer is idle, and the \slow" clock rolls the empty shift register. Vice versa, in the programming mode both CN and BUFF parts do useless job, namely, the \fast" clock runs trough the counting loop and sends nothing from the I input to the O output. Yet, this little overhead saves a lot of hardware needed otherwise to monitor the activity within the input buers and switch the corresponding clock streams on and o.

4 IS A L IF S2P C C O1 I1 O2 I2 O3 I3 I O a) I CN BUFF O O4 I4 b) Figure 4. a) Input buer for a 8 8 switch. Pins: A serial address line; L \load" line; IF \fast" clock input; IS \slow" clock input; I serial data input; O serial data output. b) Bit concentrator for a 4 4 switch. Pins: I \fast" clock input; O1 : : : 4 \fast" clock outputs; O serial data output; I1 : : : 4 serial data inputs. Parts for both pictures: RSFQ ip-op with positive only and complementary outputs, RSFQ ip-op with programmable initial state, C RSFQ \call" cell BI CONCENRAOR he task of the bit concentrating tree is to synchronously demultiplex packets arriving from dierent input buers into a single M stream. As shown at the Figure 4b, it is a full binary tree with height log 2 N and width N, built-up of RSFQ ip-ops and RSFQ asynchronous mergers (conuence buers). he tree is controlled by the \fast" clock. Each clock signal advances packet bits one stage towards the root. Because of the non-contenting nature of the incoming packet stream, there is at most one valuable data bit in each column of the tree at a time (under certain conditions there may be a number of completely empty columns due to the fact that there may occur empty packets in one or more input streams). Hence, at most cells in the tree are busy at a time, where = log 2N 2 N? 1 : (3) his factor equals 28% for N = 4 and decreases with the growth of N SERIAL-O-PARALLEL CONVERER he serial-to-parallel FIFO-type converter used as the main shared bus of the switching element is very similar in structure to the temporary address storage in the input buers (see section 3.1). It serially accepts intermixed data bits from the input I, one bit per each \fast" clock period (fed from the input IF) and ushes the overall contents of the shift register to the output channels O1 : : : N by the request of the \slow" clock IS (Figure 5). It is worth mentioning that the \call" cells used in the converter may be considered as an \RRS" ip-ops, because they have one \set" input and two independent fully-functional \reset" inputs with the corresponding outputs FREQUENCY MULIPLIER As it has been shown above, the switching element requires three dierent clock streams that dier in the frequency and in the phase, yet it takes only one clock stream from the outside, while the rest are generated in the internal frequency multiplier.

5 O IF I I C C C C OS OF IS τ a) O1 O2 O3 O4 b) OS_L Figure 5. a) Serial-to-parallel converter for a 4 4 switch. Pins: IF \fast" clock input; IS \slow" clock input; O \fast" clock output; I serial data input; O1 : : : 4 data outputs. b) Frequency multiplier for a 8 8 switch. Pins: I \slow" clock input; OS \slow" clock output; OS L \slow" clock shifted by log 2 N; OF \fast" clock output. Parts for both pictures: C RSFQ \call" cell, RSFQ ip-op, RSFQ ip-op, RSFQ inverter, delay line. he frequency multiplier (which serves as a \fast" clock generator) is organized as a delay-loop with the positive feedback and a counting loop that terminates the generation after N \fast" clock signals are derived. he frequency generated by the multiplier is determined by the delay time in the RSFQ inverter inv, which is pretty stable and depends on the nature and the design of the inverter, and the delay time in the transmission lines t which can be adjusted according to our needs so that: 1 f e N < < f 0 : (4) t + inv he multiplier also produces the third clock signal used in the device, namely, the \slow" clock shifted by log 2 N periods relatively to the external clock. his signal OS L is taken from the (log 2 N? 1)th stage of the multiplier, and then its frequency is divided by HARWARE ESIMAIONS he following equation gives a crude estimation of the overall number of Josephson junctions in the N N switching element: n (26 N log 2 N + 7 log 2 N + 28 N) : (5) Even for N = 16 Eq. ( 5) gives n RSFQ circuits of this size can be easily t to a 5 mm5 mm chip. However, according to Eq. (1), large N may signicantly decrease the bit rate in each channel. Using the hierarchical approach, say, composing an N 2 N 2 switch from N N blocks, can signicantly increase (namely, double) the frequency f e, but this gain results in the increasing number of Josephson junctions per switch. Eq. (5) can be extended to a hierarchical case: n (d) 2 d N (1?1=2d ) N 1=2 d log2 N log 2N + 28 N 1=2 d 2 d 2 d! ; (6) where d is the \depth" of hierarchy (d = 0 for a plain N N switch) and is a factor that takes into account the interconnections' overhead. We expect that it is a function of d and increases with the growth of d. As one can see from the able 1 hierarchical architecture with the depth d = 1 should be considered as the optimal one because in comparison with the at architecture it has double throughput and only slightly more complex circuitry. On the other hand, although depth d = 2 hierarchical switch allows even larger arrival rate, the complexity of its interconnections may be tremendous. One of the greatest advantages of RSFQ devices over \traditional" semiconductors is their low power consumption. he estimations of the power dissipated by a switching element on a single chip give as low as P 300 W at frequencies of 40 GHz. he combination of fast speed and low power may justify the usage of RSFQ circuits in practical systems, despite the necessity of their deep refrigeration (to 4 : : : 5 K).

6 able 1. Comparison of dierent at and hierarchical congurations for a switch. External packet arrival rate derived from the Eq. 1, assuming f 0 = 40 GHz. Number of Hierarchy Number of Number of External packet Number of overall switched depth d switching switched channels arrival rate Josephson channels N elements per element N f e, GHz junctions n , x , x , ACKNOWLEGMENS he author would like to thank P. Bunyk, r. V. Semenov and especially Prof. K. Likharev for numerous helpful hints and fruitful discussions. his research has been inspired by r. E. Wikborg, LM Ericsson, Sweden, and supported by o's University Research Initiative (AFOSR Grant #F49620{92{J{0508). REFERENCES 1. K. Likharev and V. Semenov, \RSFQ logic/memory family: a new Josephson junction technology for sub-teraherz clock frequency digital systems," IEEE rans. on Appl. Supercond., vol. 1, pp. 3{28, Mar B. Lee, M. Kang, and J. Lee, Broadband elecommunications echnology. Norwood, USA: Artech House, M. Hosoya,. Nishino, W. Hioe, S. Kominami, and K. akagi, \Superconducting packet switch," IEEE rans. on Appl. Supercond., vol. 5, pp. 3316{3317, June S. ahara, S. Yorozu, and H. Matsuoka, \A superconductive ring-pipelined network system," IEEE rans. on Appl. Supercond., vol. 5, pp. 3164{3167, June A. H. Worsham, J. X. Przybysz, J. Kang, and. L. Miller, \A single ux quantum cross-bar switch and demultiplexer," IEEE rans. on Appl. Supercond., vol. 5, pp. 2996{2999, June R. Handel, M. Huber, and S. Schroder, AM Networks. Concepts, Protocols, Applications. Addison-Wesley, P. Newman, \AM technology for corporate networks," IEEE Communications Magazine, pp. 90{101, Apr J.-C. Lin and V. Semenov, \iming circuits for RSFQ digital systems," Applied Superconductivity, vol. 5, pp. 3472{ 3477, Sept E. Brunvand and R. Sproull, \ranslating concurrent communicating programs into delay-insensitive circuits," tech. rep., School of Computer Science, Carnegie Mellon University, Pittsburg, PA 15213, Apr

Multi-Channel Time Digitizing Systems

454 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 13, NO. 2, JUNE 2003 Multi-Channel Time Digitizing Systems Alex Kirichenko, Saad Sarwana, Deep Gupta, Irwin Rochwarger, and Oleg Mukhanov Abstract