Single Flux Quantum Based Ultrahigh Speed Spiking Neuron

Transcription

1 Single Flux Quantum Based Ultrahigh Speed Spiking Neuron M. Altay Karamuftuoglu, and Ali Bozbey Abstract Neuromorphic computing methods and artificial neurons can improve the possibilities of solving complex problems more efficiently. We present a spiking neuron circuit formed by standard SFQ cells and a somatic circuit. The neuron s soma part consists of a double-junction SQUID interfered with a resistor (threshold loop), a resistor inductor structure (decaying loop), and mutual inductance between threshold loop and decaying loop. Designed artificial neuron has the following main properties: (i) ultra-high-speed operation with minimal power consumption, (ii) compatibility with standard foundry processes that allows fabrication with the available infrastructure, (iii) compatibility with conventional logic gates which enable complicated networks to be designed and implemented. The artificial spiking neurons which cover 40 µm 80 µm on-chip area with different activation functions are fabricated with a commercial foundry service. Spiking neurons have been implemented and demonstrated experimentally. Firing frequency of the neuron s soma is about 25 GHz with about J/spike energy. Index Terms Artificial Neuron, Integrate and Fire Neuron, Leaky IFN, Superconductor, Spiking Neuron T I. INTRODUCTION he scientific community enthralled by understanding the general principles of human brain functions, as a further matter, on how to mimic the abilities by utilizing artificial neurons for more efficient computing. Neuron is considered as fundamental unit of human brain due to the functions, receiving and sending electro-chemical signals to process the data and creating overall behavior [1]. Dendrites receive synaptic inputs from other neuron axons, and they bring information to the cell body. Soma collects all signals from its dendrites and creates relative response that depends on received signals. The axon carries electrical response to the connected neurons. Functionality comes from self-assembly of brain cells, known as nerve cells or neurons. Mathematical neuron models are created with relatively similar components of biological structure [2], [3]. Artificial Neural Network (ANN) is considered as the alternative and effective way to deal with complex problems such as image recognition, decision making, and forecasting while simulating the biological brain [4], [5]. Implementation of the neuron behavior gives opportunity to create neuromorphic computers with the ability of learning events just like the way brain does. Computational software tools connect artificial neurons to each other to create ANN to adopt M. Altay Karamuftuoglu is with the Electrical and Electronics Department, TOBB Economy and Technology University, Ankara, Turkey ( akaramuftuoglu@etu.edu.tr) biological neural network behavior. ANN software tools have gained extensive acceptance for neural network applications because of the learning abilities, and computational power and speed through parallel processing. Even though there are hardware neuron design examples based on CMOS devices [6] [9], CMOS technology is facing its fundamental limits as Moore s law [10], [11] reaches its end, and this motivates the different technology investigations about artificial neuron applications [12] for implementing a neuromorphic computer. Single flux quantum (SFQ) technology [13], [14] is one of the strongest candidates for hardware neuron implementation technologies. Characteristic features of Josephson junctions (JJs) which have ultra-highspeed switching behavior with low power consumption match the properties of biological neurons. The comparison of biological neuron [1] with CMOS Integrate and Fire Neuron (IFN) Model representations [6], [8], [9], [15] and our superconducting IFN Model features is shown in Table 1 which is adapted and extended from [16]. There are several research papers that show the implementation of brain cell characteristics by using SFQ technology [17] [32]. In addition to these studies, designed neuron in this research has characteristic features such as simplified structure, efficient usage of on-chip area, high operation speed, and compatibility with standard Rapid Single Flux Quantum (RSFQ) digital library elements. The compatibility of this neuron enables convenient integration with conventional logic circuits. In RSFQ logic blocks, circuits require a clock signal [13] to achieve an output signal. Also, the design of clock signal tree on circuits takes chip area. However, this circuitry disadvantage can be cleared out with the presented neuron model. Furthermore, pipeline computing will be possible since the network which is created with the model will be capable of executing the data in parallel or in time-sliced fashion. Our model is based on leaky IFN model and it demonstrates effective and robust way of the implementation of a biological brain cell operation. The neuron circuit can trigger the connected following neuron and/or digital SFQ circuit cells in the library without the need for another circuit because of the matching input/output feature. Another main advantage of the designed neuron circuit is its compatibility with the established SFQ foundry processes [33] [36]. Ali Bozbey is with the Electrical and Electronics Department, TOBB Economy and Technology University, Ankara Turkey ( bozbey@etu.edu.tr)

2 TABLE 1 THE COMPARISON OF BIOLOGICAL NEURON [1] WITH CMOS IFN MODEL [6], [8], [9], [15] AND OUR SUPERCONDUCTING IFN MODEL Information Transfer Long distance 'Lossless' Data Transmission 3D Architecture Threshold Tuner (Summation Operation) Biological Neuron CMOS Neuron SFQ Neuron Electro-chemical Electrical Single Flux Quantum [1], [37] [6] [9] Impulse Spike (SFQ) Pulse Axon [1], [37] Membrane, Nucleus, Mitochondria, Ribosomes [38] Active and Passive Semiconducting Elements Semiconducting Metal Layer Stack [7] [9] [39] Soma [1], [37] Spike Integrator Circuit [7] [9] Interconnection Synapse [1], [37] Synapse Circuit [9] Josephson Transmission Line (JTL) Superconducting Metal Layer Stack Threshold & Decaying Loops of JJ-AN Pulse Splitter and Merger Digital Circuits Fault tolerance [38] [6] Firing Frequency (Spike Fire Rate/Second) Energy per spike (Joule/Spike) With-w/o DC power khz [41], [42] khz [6], [8], [43] GHz N/A [6], [44] [6] [13] [13] [40] This Paper [13] This Paper This Paper This paper, [45] II. ARTIFICIAL NEURON CIRCUIT For biological neural network, synaptic strengths define the function of the network, and network provides the same operation if synapses remain unchanged. If the synapse values are steady, biological memory function of network will be achieved [46]. If a person does the action repetitively, related synaptic weight values increase, and this provides recall function of network. Main body of neuron, soma, acts like a temporary storage of inputs to be able to do aggregation function. If enough input pulses arrive to soma from synapses, it fires an axonal (output) pulse and the operation is called somatic operation. However, if the number of inputs is not enough within a certain time, no output pulse will be released. These principles are inherently implemented in JJ based logic circuits, namely SFQ circuits [13], [14] where the logic 1 and 0 is based on SFQ pulses. Thus, it is possible to implement the operation of a biological neuron by JJs and SFQ circuits in an intuitive way. In this research, our circuit implements the mathematical model named McCulloch-Pitts neuron [47] which is mainly composed of a summation function and activation function. In the model, number of inputs and their individual weighs determine the function of the cell. Operation starts with individual multiplication of inputs (X k ) with their weights (W k ) as shown in (1). Input weights represent biological neuron synapses and it simulates chemical transmission of the neuron connection. Negative values of weight have inhibitive effects while positive values of weight are considered as actuator. Then, all values arriving from inputs are added together on summation function. If the sum of multiplication results (u) surpasses the threshold value (θ), activation function provides a single output and pulses will be transmitted to the following neurons via synapses as reported in (2). The combination of summation and activation functions creates the functional cell body of a single neuron and activation function is a control component that adjusts the amplitude of neuron output (Y). N u = X k W k k=0 Y = f(u) = 1 if u θ Y = f(u) = 0 else A. Implementation of The Artificial Neuron Artificial neuron s working principle matches the characteristic features of biological neuron operations as shown in Fig. 1-a,b. Due to the similarities, the designed circuit is a potential candidate for high performance and low power neural network implementations. The neuron circuit basically provides the spatial and temporal integration of SFQ pulses. After the flowing current in proposed circuit reaches the threshold value, a single SFQ pulse will be generated which is similar to the spiking behavior of neuron. The interconnection between neurons is done by SFQ circuits that enable to build complex structures. Artificial neuron consists of artificial soma, axon, dendrite, and synapse circuits. Somatic operation is carried out by Josephson junction (JJ) based Artificial Neuron (JJ-AN) cell. Axon structure is created with Josephson Transmission Line (JTL) circuit and dendrite part is performed by Confluence Buffer (CBU, Merger) circuit. Furthermore, multiple connections between JJ-AN output and the following neuron dendrite are executed with Pulse Splitter (SPL) circuit. Combination of SFQ library cells such as CBU, SPL, and JTL creates the synapse structure. During the generation of the SFQ pulse, JJ switches to voltage state and generates a quantum accurate digital signal in the form of single flux quanta 0 = Wb. Energy per pulse is calculated by (3) where I C is the critical current of the JJs. τ E SFQ = I c Vdt = I c Φ 0 0 (1) (2) (3)

3 Fig. 1. a) Typical biological neuron cell b) SFQ based spiking neuron cell. Biological (artificial) neuron consists of three parts: axon (JTL or SPL cells), dendrites (CBU) and soma (JJ-AN). The synaptic operation occurs between neurons and in this research, this structure is created with SFQ library cells such as CBU and SPL cells. Since the operation is multiplication of SFQ pulses, it is basically a quantization of inputs. c) JJ-AN cell. The circuit contains two main loops that are mutually connected to each other. Threshold loop adjusts the current s limit for excitatory inputs and decaying loop helps to change threshold loop s time constant with the mutual coupling value for the current dissipation. Critical current of the junctions in the neurons of this work is about 250 µa. So, energy per pulse is about Joule for 25 GHz firing rate, excluding DC power. Bias voltage of the neuron cells is about 2.5 mv with a bias current of 350 µa. So, DC power consumption is W. For 25 GHz firing rate, average energy per pulse is Joule including DC Power consumed at the bias and shunt resistors in the circuit [45]. In addition, it is possible to implement the circuits by using e- RSFQ where Josephson junctions and inductors [48] replace the bias resistors to achieve zero static power consumption. 1) Artificial Soma Structure: In order to imitate the somatic operation, we modelled the neuron cell body by using Josephson junctions and passive elements, and the schematic of JJ-AN is shown in Fig. 1-c. The circuit is mainly formed by a threshold loop, decaying loop, and mutual inductance between threshold loop and decaying loop. The loops adjust the fading time of pulses that are held in threshold loop. Various combinations of parameter values can create different threshold values and decaying times on neuron circuit. In JJ-AN design, the activation function which is step function in this research is set to desired number of pulses. The main objective of the loops is to provide either spatial or temporal summation function and activation function of a simple neuron. Threshold loop structure holds the circulating current which is created by SFQ pulses and creates the biological neuron s characteristic feature called neuronal polarity [49]. The consisting elements simply explain how fast a neuron s voltage level decays to its resting state after a current injection. Connection between threshold and decaying loops is achieved by mutual inductances. Decaying loop structure s role is higher sensitivity adjustment with the coupling rate on neuron s voltage change in the circumstances of high number of SFQ pulses and/or small pulse intervals on input signals. Furthermore, it enables to choose the circuit parameters of threshold loop for better parameter margins. To match the impedance of a JJ-AN to an SFQ logic circuit or any desired circuits, we adjust L IN1, L IN2 and L OUT inductances. So, when a JJ-AN fires a pulse, it can be handled directly by the SFQ circuits or vice versa. J 1 and J 2 Josephson junctions determine the threshold value and bias current adjusts the quiescent point of these junctions. R LOOP resistor adjusts the dissipating amount of current from threshold loop. By increasing this resistor, the current dissipates faster, and more input pulses will be required to reach threshold value. Mutual coupling between L LOOP and L TOP inductances is another factor that adjusts the decaying time of loop current. If the mutual coupling value is high, the amount of transferred current to decaying loop will be high and the circulating current in the threshold loop will dissipate faster. On the other hand, when L LOOP value increased, the decay time will be extended, and the threshold loop current will remain in the loop longer due to the increased L/R time constant. The effect of R TOP1 and R TOP2 resistors is same as R LOOP parameter and they enable fine tuning of the timing parameters. In addition, the quiescent point of neuron circuit can be adjusted easily by changing the DC bias current. In summary, it is possible to achieve the threshold values of a neuron by changing the circuit parameters of Fig. 1- c. To achieve optimum values, a design tool has been developed and explained in the following sections. 2) Artificial Axon, Dendrite, and Synapse Structure: For SFQ pulse transmission, JTL circuit can be connected to JJ-AN cell and it will carry the roles of a biological neuron s axon part. Confluence Buffer (CBU) and Splitter (SPL) circuits can be attached to the input and output sides of the JJ-AN circuit to increase the fan-in and fan-out respectively. The structure with JTL, SPL, and CBU library symbols is shown in Fig. 1-b. The connection between axon ending and dendrite is called synapse structure. From axon ending to dendrite, information transferred by chemicals called neurotransmitters in biological neurons. Neurotransmitters has excitatory and inhibitory effects on the process. In this research, we put the presented neuron under test only with excitatory signals due to the transmission of data and the data is carried out by standard SFQ library circuits that work with positive bias current. It is possible to use bidirectional SFQ circuits to implement inhibitory signals [50]. However, such circuits require switching between negative and positive bias currents which limits the operation speed. In this research, we opted to have only excitatory signals and handled this case in the neural network design stage. The process is quantization of weights since the data is transmitted only with SFQ pulses. Neural network with quantized weights and activations is called Quantized Neural Network (QNN) [51] and it can reduce computational cost in ANN. Furthermore, spiking behavior of presented neuron create a possibility of implementations of Spiking Neural Network (SNN) [52] that closely mimic the operation of biological neural network. The synapse structure is designed to adjust the weight of artificial neuron which is shown in Fig. 1-b and explained in section II- B-2. In this research, SFQ wiring cells from the library create synapse circuitry and JJ-AN can work together with those.

4 B. Simulation Results 1) JJ-AN Cell: Every pulse that arrives to JJ-AN circuit is held in threshold loop and the amount of collected current can be observed on L LOOP parameter. Threshold loop mimics the part of human brain cell called soma. Pulses may arrive to the circuit at arbitrary times and the stored amount of current in the threshold loop may increase. In the meantime, the current dissipates as heat in certain periods of time. We added a series of single inductance (L LOAD) and resistance (R LOAD) to output port of neuron as load and provided different input variations to JJ-AN circuit in Fig. 2. All simulations are carried out by using Josephson Simulator (JSIM) [53] and results are shown in Fig. 3. Fig. 2. JJ-AN Simulation Schematic. (L LOAD=1 ph, L IN1=0.3 ph, L IN2=1.6 ph, L LOOP=9.8 ph, L OUT=1 ph, L TOP=9.6 ph, R LOAD=6.1 Ω, R LOOP=1.47 Ω, R TOP1=5 Ω, R TOP2=5 Ω, K=0.5 ph, J 1= 243 µa, J 2= 243 µa, I b=0 µa) to 30 ps (IV). For this situation, the circuit generated three SFQ pulses on output line. After 18ps, the circuit generated the first SFQ pulse and created the next SFQ pulses every 10 ps. As a result, theoretical firing rate of the model without bias current was observed approximately 100 GHz in (IV) situation. Input and output voltage values can be observed on V PULSE and J 2. 2) Individual Synapse Generation: In order to test the individual artificial neuron circuits with various weights, we created different synapse circuits on chip by using SFQ cells. For this purpose, we used SPL and CBU cells as shown in Fig. 4. The synapses generate 1, 2, and 3 pulses with proper timings by using a single external trigger signal. By adjusting the delay paths (A, B, C, D), we can create the certain input patterns for neurons. The number of SPL and CBU cells determines the number of pulses. SPL cell first converts a single SFQ pulse to 2 simultaneous pulses. One of these pulses will be delayed as required and it can be merged to obtain an SFQ pulse train. By combining n SPL and n CBU cells, n+1 paths will be formed for SFQ pulses. Delay time of the paths can be adjusted with JTLs and different type of SFQ circuits if necessary. Pulse path simulations are shown in Fig. 5, and t k denotes the delay for the k th connection. The function of a single quantized weight is achieved by SFQ cells that create opportunity to multiply the number of SFQ pulses. By simply merging these weights with CBU cell, different weights will be assigned to JJ-AN circuit. Fig. 4. Synaptic weight circuits for 1, 2, and 3 pulses. Fig. 3. JJ-AN JSIM result with different input patterns. Voltage units are mv and current units are ma. In this test, input pattern contains spikes and continuous signals to show the importance of different amplitudes, delays, and durations. First, two spikes with 1.2 mv amplitude arrive to circuit (I). Due to insufficient number of spikes and large delay between spikes, JJ-AN cell is unable to fire an output. However, if we increase the number of spikes to five and decrease the delay between neurons to 1 ps, neuron circuit can fire an output after reaching threshold value (II). Likewise, neuron circuit can work under positive continuous signals. We put the neuron circuit under test with the continuous inputs with different amplitudes and duration. First, we provided 0.75 mv continuous signal with 10 ps duration to observe a single output (III). Furthermore, we decreased the next continuous signal s voltage level to 65 mv and increased the total duration of signal Fig. 5. Pulse path simulations. Voltage units are mv. Top plot is the trigger signal. 2 nd, 3 rd, and 4 th plot are the outputs of the circuits shown Fig. 4 for weights of 1, 2, and 3 respectively.

5 Fig. 6. Test Schematic of JJ-AN. (L IN1=0.3 ph, L IN2=1.11 ph, L LOOP =5.32 ph, L OUT =2.94 ph, L TOP=10.76 ph, R LOOP =0.34 Ω, R TOP1=0.31 Ω, R TOP2=0.3 Ω, K=0.21 ph, J 1= 278 µa, J 2= 272 µa, I b=369 µa, Two pulse threshold); (L IN1=0.3 ph, L IN2=1.57 ph, L LOOP =9.42 ph, L OUT =4.59 ph, L TOP=12.34 ph, R LOOP =0.53 Ω, R TOP1=7.23 Ω, R TOP2=3.86 Ω, K=0.34 ph, J 1= 150 µa, J 2= 243 µa, I b=342 µa, Three pulse threshold) Fig. 7. a) Simulation results of the neuron with 2-pulse threshold. The test for this neuron has four different input situations: 1, 2, 4, and 6 pulses. As expected, after each 2 SFQ pulses, JJ-AN fires an SFQ pulse. We set the interval time between two SFQ pulses in every pack of input to 20 ps. Due to this, JJ-AN fires a single output every 40 ps and theoretical firing rate can be observed approximately 25 GHz. b) Simulation results of the neuron with 3-pulse threshold. The test for this neuron has three different input situations: 1, 3, and 3 pulses. As shown, when the number of pulses that arrive with proper timing is equal to the threshold of the JJ-AN, it fires an SFQ pulse. Even if the number of pulses is equal to the threshold, the delay between pulses affects the result of neuron output since the trapped current dissipates in the threshold loop. For the last state, we set the interval time between SFQ pulses to 20 ps. Voltage units are mv and current units are ma. 3) Neuron-SFQ Cell Compatibility: JJ based artificial spiking neuron and biological neuron are analogous to each other and it is possible to implement most of the functionalities of biological neuron with the presented circuit. However, this property alone is not enough for practical applications. For implementing a complicated artificial neural network, many of these cells should be able to reliably fabricated, and neuron circuits should able to be interfaced with conventional logic circuits as well as other neuron circuits for input and output signals. As the conventional logic interface, we aimed to match the JJ-AN s parameters with SFQ logic circuits since the SFQ logic technology is already matured for implementations of high speed and complicated logic circuits [54] [61]. In addition, SFQ circuits and proposed artificial neuron cell body can be fabricated by using the same foundry process on the same chip. So, cost and reliability of fabrication and ability to use available design tools enable convenient scaling of the artificial neural network with the proposed artificial neuron. Fundamentally, a JJ-AN has one input and one output line each of which is compatible with SFQ logic circuits [13], [62], [63]. During the optimization, JJ-AN cell is connected to JTL cells on input and output lines since the impedances of all the cells in the library are the same as a JTL. SFQ test circuit schematics of the JJ-AN together with peripheral circuits is shown in Fig. 6. In this research, we designed two neurons with threshold of two and threshold of three SFQ pulses. For the first design, after obtaining a single input pulse, second pulse should arrive within 65 ps. If it arrives after 65 ps, there will not be enough current in the threshold loop due to the decay of stored current. For a neuron of threshold two, after every two pulses, neuron circuit provides a single pulse as an output and it is ready to obtain next pulse after releasing the output pulse. The neuron of threshold three provides an output after obtaining three pulses and the delay between pulses should be set to maximum 20 ps. Simulation results of the neuron circuits with two and three pulse thresholds are shown in Fig. 7. Input patterns that arrive to the neuron are SFQ pulses from the previous JTL cell. With the arrival of an input pulse, circulating threshold loop current increases and stored current can be observed on L LOOP. If the current reaches the threshold limit of the loop, J 2 switches and fires an output pulse to next stage. 4) Input Pattern Generation for The Test of JJ-AN: It is possible to generate the required spike patterns for each neuron in a neural network configuration. However, to test the individual neurons operation, we used the synapse configurations explained in section II-B-2 to build synapse and axon structure of a single neuron as shown in Fig. 1. In the same chip, we designed five independent neurons with two and three pulse thresholds. Three of them have 2-pulse thresholds and two of them have 3-pulse thresholds. In order to trigger all neurons at the same time, we provide a single pulse which is split into five different pulses to test neuron circuits individually at the same time.

6 Fig. 8. JSIM simulation results with SFQ representation. a) Neuron circuits with 2-pulse threshold. b) Neuron circuits with 3-pulse threshold. Voltage units are mv. For the test of 2-pulse threshold neurons, the circuit generates a single SFQ pulse for neuron 1, two SFQ pulses with 20 ps interval for neuron 2, and three SFQ pulses with 65 ps interval for neuron 3. Since the thresholds of the neurons 1, 2, 3 are two, then Output 1 is 0 while Output 2 and Output 3 are 1 after each input signal. JSIM results of the neuron circuits with 2- pulse threshold are shown in Fig. 8-a. For the test of 3-pulse threshold neurons, the circuit generates two SFQ pulses with 20 ps interval for neuron 4 and three SFQ pulses with 20 ps interval for neuron 5. Since the thresholds of the neuron 4 and 5 are three, Output 4 is 0 while Output 5 is 1 after each input signal. JSIM simulation results of the neuron circuits with 3-pulse threshold are shown in Fig. 8-b. 5) SFQ Neural Network Design Software: The purpose of the software is implementation of a specific computation task with the proposed neuron based on excitatory inputs. It is possible to implement neural networks based on QNN and SNN configurations with standard SFQ library cells since the JJ-AN circuit greatly matches with leaky IFN characteristic features. The further information about designing logic and arithmetic blocks with proposed artificial neuron and inhibitory input cases based on JJ-AN are not reported in this paper since the scope of this paper is about implementation of a single neuron with excitatory inputs. The developed software for JJ-AN cell implementation simply uses supervised learning technique with error-correction learning [64] and it trains the neural network to create desired output as a result of sample inputs. The tool initially connects every neuron to next layer with desired or random weight and threshold values within a defined range of integer values. In addition to input and output layers, it is possible to add hidden layers by simply adding neuron amount of new layer in array which defines the number of layers and neurons in each layer. The tool uses feedforward operation to achieve the neural network output. Firstly, the tool applies input data to input layer and data propagates through the network layer by layer. The difference between desired output and actual output can be counted as error. For error correction, the tool uses gradient descent algorithm [64] and the error on output layer will be redirected to every layer on each training iteration. To minimize the error on output data, a learning rate will help to adjust parameters as a step size for computation. After the completion of weight calculations with the learning rate, their values will be rounded to the near integer value since proposed neuron uses quantized weights. Furthermore, if the individual weight of any neuron reaches upper or lower range limit, the threshold value of that neuron will be adjusted, and new integer value will be assigned to the related weight between neurons. JJ-AN cell s threshold value is time dependent and a related parameter that defines pulse interval time is assigned as 20 ps to simplify calculations. The calculations continue until the output converge to a point. This convergence might bring to local minima or global minima with the learning rate and converging to the global minima will not be guaranteed. After reaching to any minima, the accuracy of result will be compared to the desired accuracy. If the actual accuracy is above the desired value, tool will stop but if it is below desired value, the whole calculation process will restart with new initial values. III. JJ-AN OPTIMIZATION PROCEDURE There are many solutions to reach the desired neuron properties. During the fabrication of circuits, there are some fabrication tolerances in the JJ critical currents, inductances and resistors. In addition, during measurements thermal noise increases the gray zone of comparator-based circuits [65], [66]. Optimization of the neuron is an important process that enables the physical implementation of the circuits after the fabrication by increasing the parameter margins. To optimize circuit, we selected Particle Swarm Optimization (PSO) because it is one of the non-linear optimization methods and its algorithm depends on modelling of particles. Each particle that seeks for the maxima point in a given search-space determines the values based on the objective function of the application. Further information can be found in [54], [67] that was used to develop SFQ logic cells [13], [62], [63] and vortex transitional memory [54]. Optimizer uses a reference of defined input pulse pattern to compare the output pulses that will appear if the circulating current in loop surpasses the threshold. In simulation, it obtains

7 peak points for each of input and output pulses. Input pulse pattern comes from previous digital cell or neuron circuit and neuron circuit was optimized together with them because the circuit must ensure that its impedance matches with SFQ digital library. Reference input and output patterns come from the constructed circuit in schematics and we used commercially available numerical computing environment for the pattern format that we want to obtain on output. We developed a function to integrate the pattern of neuron circuit and an optimization of any circuit with analog input and output patterns. This function checks peak points of input and output lines and it compares the found points to create I/O relation. Optimizer sweeps each parameter with predefined step size to limit points. For this research, step size is set as 1% of parameters design values. Fig. 10. a) JJ-AN with two pulse threshold circuit layout on chip. Bar = 5 µm. b) JJ-AN with three pulse threshold circuit layout on chip. Bar = 5 µm. IV. EXPERIMENTAL RESULTS Fig. 9. Parameter margins of 2-pulse and 3-pulse threshold JJ-ANs. I b value is calculated by division of V b to R b. So, margin range values of V b and R b are shown in the figure instead of I b. We have run the modified optimizer for two circuits defined with different patterns and these circuits are made for STP2 process technology [36] with J c=2.5 ka/cm 2. For each case, we have run the program about 48 hours in an Intel i7 3930K GHz 6 core PC with 5 particles. Step size is set to 1% of parameter values. Values of margin range have been discrete in 1% steps. We have obtained ±23% for 2-pulse threshold JJ-AN circuit with 20 ps input pulse delay and ±7% for 3-pulse threshold neuron circuit with 20 ps delay between pulses. All individual parameter margin ranges are shown in Fig. 9 and the chip photographs are shown in Fig. 10. Another way to design a neuron with larger threshold values is to simply merge the same type JJ-AN cells to each other with CBU. This way, threshold value will be increased, and the structure will have the same pulse interval pattern for inputs. For instance, to create a 4-pulse threshold neuron, the output lines of 2-pulse threshold JJ-ANs can be connected to a CBU cell which will be connected to a new 2-pulse threshold JJ-AN. A. System Setup In this research, all the experiments were completed in a twostage pulse tube cryocooler (Sumitomo RP-062B) with a temperature stability of about 10 mk and excess cooling power of about 100 mw at a temperature of 4.2 K. Coaxial RF cables created input and output signal connections between the room temperature electronics and chip. As DC bias lines, Phosphor- Bronze wires were placed. The equipment always stays in the Faraday cage. A three-layer μ-metal magnetic shield around the chip was used to attenuate the external magnetic field to about 5 nt. The block diagram and photo of the test setup, and JJ-AN package photo are given in Fig. 11 and details of the experimental setup are explained in [68]. B. Test Setup The circuits were fabricated with AIST Standard Process (STP2) [36]. JJ-AN cell covers 40 µm 80 µm on-chip area. As explained in the section II-B-4, a simple design that contains five neurons with different synaptic weights placed on the chip. To trigger the neurons with conventional signal generators, a DC-SFQ circuit and to measure the output of the neurons with an oscilloscope, a SFQ-DC circuit used at the input and output of neurons [13]. With the trigger signal from the generator, the synapse circuits generated the pulse patterns explained in section II-B-2 and we observed outputs of neurons 1-5. Placement of the neurons in the chip is shown in Fig. 12. Experimental neuron outputs which are consistent with the simulation results obtained for JJ-AN circuit and the results are shown in Fig. 13. Neurons 1 and 4 did not give any output as the input weights generated by the synapse circuit are lower

8 than their thresholds and neurons 2, 3, and 5 gave output as the weights are equal or greater than the thresholds. Note that, the trigger signal frequency set to 1 khz due to the limitations of the differential amplifier. However, this time scale is not representation of the firing rate of the neurons. In any case, regardless of the trigger signal frequency, the neurons must respond to the input signals from the synapses which provided in 50 GHz and 15 GHz intervals for 2-pulse and 3- pulse threshold neurons respectively. Fig. 13. Experimental results with DC representation. a) Neuron circuits with two pulse threshold. b) Neuron circuits with three pulse threshold. Voltage units are mv. Fig. 11. a) Block diagram of the test system. b) Test system photo. c) JJ-AN package photo. Fig. 12. JJ-ANs test circuits with individual synapse on chip. Bar = 100 µm. V. CONCLUSION In this work, Josephson junction based artificial neuron (JJ- AN) cells fabricated with AIST Standard Process (STP2) [36] and cover 40 µm 80 µm on-chip area. The design values for the firing rate of the neurons are 50 GHz and 15 GHz for 2- pulse and 3-pulse neurons respectively with an event energy per SFQ pulse of approximately and Joule/spike levels including and excluding DC power consumption at the bias and shunt resistors respectively. Furthermore, e-rsfq implementation can create opportunity to reach zero static power consumption in circuits. Emulating neuronal dynamics directly on chip will enable the creation of neural networks or hybrid circuits for robust/high performance operations and improve the development of neuromorphic computers with complex operations. JJ-AN is amenable to use in processing event-based sensory information and low-power perceptual decision making. The working principles of the circuit closely match to biological neuron in

9 the sense that it operates based on pulsed logic. Proposed artificial neuron analyzed by numerical simulations and correct operations are proven experimentally. JJ-AN cells have a separated bias line that provides opportunity of adjustable threshold levels even after fabrication for quantized inputs. In addition, it is possible to implement the JJ-AN cell to work with inhibitory inputs by using bidirectional RSFQ. For simplicity of circuit design, neuron model put under test with only excitatory signals. However, the neural network design tool that we developed for this specific type of neuron considers only excitatory inputs and designs the network accordingly. In summary, the proposed neuron model has promising characteristics due to its size, I/O speed, compatibility with digital circuits, reliability on fabrication, and power consumption to improve the performances of neuromorphic computing systems. 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