Proposal of a Timing Model for CMOS Logic Gates Driving a CRC Load

Transcription

1 Proposal of a Timing Model for CMOS Logic Gates Driving a CRC Load Akio Hirata, Hidetoshi Onodera and Keikichi Tamaru Department of Communications and Computer Engineering Kyoto University, Sakyo-ku, Kyoto, 66-85, Japan hirata@kuee.kyoto-u.ac.jp Abstract We present a gate delay model of CMOS logic gates driving a CRC load for deep sub-micron technology. Our approach is to replace series-parallel connected MOSFETs to an equivalent MOSFET and calculate the output waveform by an analytically derived formula. We present a MOSFET drain current model improved from the n-th power law MOSFET model to represent the characteristic of the equivalent inverter accurately. The accuracy of our gate delay model is evaluated in several gates under various conditions of input transition time and CRC parameters. The maximum error is less than.3% in the experiments. Our approach will contribute to fast and accurate estimation of circuit speed under various supply voltage, which will enable us to optimize the circuit speed and power dissipation. Introduction Accurate estimation of critical path delay is essential for the design of high performance LSI chips. We can estimate the critical path delay on a small circuit by using numerical simulator (e.g. ). However on a large circuit, computation time becomes quite large. Therefore accurate models of the propagation delay for static logic gates are essential for fast and accurate estimation of the circuit speed. As the minimum feature sizes of LSI technologies have been scaled down, resistive components of interconnects increase. We can no longer ignore the resistance for accurate estimation of critical path delay. In the calculation of the critical path delay, we have to evaluate gate delay and interconnect delay. The gate delay is the propagation time of a signal through the gate. The interconnect delay is the time for the signal to propagate through interconnect wire. For the estimation of the gate delay, we can approximate the interconnect load to a simple equivalent circuit using AWE-based methods. A CRC load is known as an effective driving point model of interconnects[]. At present, LSI CAD tools for synthesis and verification calculate gate delay using two-dimensional look-up tables in terms of output load capacitance C L and transition time of input voltage. If we extend this look-up table based approach to the evaluation of gate delay driving a CRC load, we need four dimensional look-up tables, which cost too much characterization time and data size. Analytical delay model is useful not only because its calculation speed is faster than circuit simulation but also it can be applied to various operating conditions once its parameters are characterized for that fabrication process. Much work has been done to analytically estimate the gate delay in static CMOS technology[2, 3, 4, 5, 6, 7, 8]. However these approaches assume a static capacitance as the output load of a gate, failed to provide an accurate estimation for the design of recent LSI chips. Dartu et al. proposed an empirical gate delay model for gates driving a CRC load[9]. This method pre-characterizes an equivalent resistance of each gate and prepares a two-dimensional look-up table for the waveform of a voltage source which drives the resistance. To calculate output waveform during input transition, effective capacitance is calculated by solving a non-linear equation by referencing the look-up table. This approach provides a good compromise for calculating gate delay under a CRC load using two-dimensional tables. It however requires re-characterization if we change operating conditions such as supply voltage and temperature range. In this paper we present a method for calculating the gate delay for CMOS logic gates driving a CRC load. Our method requires less characterization effort and less computational time by replacing each gate to a simple inverter circuit and calculating the gate delay by analytical formula. The method for replacing series-connected MOSFETs to an equivalent MOSFET is based on that propose by Sakurai []. We improve the modeling method by separating the operating region of the series-connected MOSFET into two and prepare drain current models for each region. Output waveform of an inverter composed of the equivalent MOSFET is derived analytically. 2 Macro model of the gate delay We define a stage as a structure made up of a pmos block and an nmos block which are connected at the output node of the stage(fig. ). The block is a set of series-parallel connected MOSFETs. We can say that a primitive CMOS gate consists of a combination of one or more stages. For example, IN, NAND, NOR gates are made up of one stage, and BUF, AND, OR gates are made up of two or more stages. We can calculate the gate delay for each cell if we calculate the delay for each stage. We present a method to calculate the delay of a stage. The method consists of two steps:. Replacing an nmos block and a pmos block to equivalent MOSFETs respectively for each input-to-output path; that means replacing a stage to an equivalent inverter gate. This method is described in Section Calculating delay of the equivalent inverter gate by an analytical formula. The derivation of the formula is presented in Section 4.

2 a b... pmos Block nmos Block Figure : Definition of a stage. y Replace C GD a C GD b y C pa when input a transients y C pa when input b transients Figure 2: Replacing a stage to an equivalent inverter gate. 3 The method of replacing a stage to an equivalent inverter The method of replacing a stage to an equivalent inverter is made up of two steps. The first step is to replace a pmos block and an nmos block to equivalent MOSFETs which have the same DC-characteristics of each block. Figure 2 shows the model. We need DC-analysis for both of the pmos block and the nmos block and calculate the model parameters of the equivalent MOSFET. The second step is to calculate equivalent parasitic capacitances. We describe the steps in the following subsections respectively. 3. Modeling an equivalent MOSFET Sakurai proposed a method of replacing series-connected MOS- FETs to a MOSFET which is represented by the n-th power law MOSFET model[]. This is a reasonable approach when the drain current is proportional to the n-th power of input(gate) voltage. However, this is not always the case. Figure 3 shows the I- characteristics of a circuit with four series-connected nmosfets which corresponds to the nmos block of a four-input NAND gate. Input(gate) voltage is applied to the gate of the top nmosfet and the other gates are kept to. Similarly in Fig. 4, input(gate) voltage is applied to the bottom nmosfet and the other gates are kept to. In the former example the drain current increases almost linearly to the input voltage. In this case, the n-th power law MOSFET model can represent the characteristics well. However in the latter example, the curve increases sharply in low GS region but saturates in high GS region. The reason is that the operating region of the bottom nmosfet changes from saturation to linear. In this case, the n-th power law MOSFET model cannot represent the characteristics accurately. Therefore we propose an improved modeling method using the n-th power law MOSFET model. We separate the operating region of the series-connected MOSFET into two: low GS region and high GS region. In the low GS region, the drain current is modeled by a single n-th power model. In the high GS region, we superimpose another current component on that of the low GS region. The boundary is GS = T H2. The added component in GS T H2 is also represented by the n-th power model with the threshold voltage of T H2, and hence there is no discontinuity across the boundary. The model equations and parameters are explained below. DSAT = K( GS T H T H ) m I DSAT = ( T H ) n 2 8 >< >: b( GS T H T H ) N : T H GS T H2, b( GS T H ) N b2( GS T H2 T H ) N2 T H : T H2 GS, I DS = ID5 = I DSAT ( + DS ) :DS DSAT I DS = ID5 2 DS DS DSAT : DS < DSAT DSAT where K; m; n; ; T H ; b; b2; N; N2; T H2 are model parameters. Parameter T H is the threshold voltage of a single MOSFET, which is common in that particular process technology. Parameters K; m; n; ; b; b2; N; N2; T H2 should be determined for each block. We will examine how to calculate these parameters. Parameters T H ; K; m; can be calculated in a way similar to the n-th power law MOSFET model[3]. Parameter T H2 represent the point where the drain current curve begins to be off from that represented by the n-th power law MOSFET model for the low GS region. We empirically set T H2 to the middle point between the threshold voltage T H and supply voltage ( T H2 = ( + T H )=2). Parameters n; b; b2; N; N2; T H2 are determined by matching the values of modeled drain current and real drain current at representative operating conditions as explained next. Figure 5 shows a conceptual illustration of the drain current characteristic. The horizontal axis represents input voltage to the gate node of a MOSFET in series-connected MOSFETs (other gates are connected to ) and the vertical axis represents the drain current flowing through the series-connected MOSFETs. We define voltages v; v3 as the middle point between T H and T H2 and that between T H2 and, respectively. Parameters i; i2; i3; i4 represent the values of drain current when the gate voltages are v; v2(= T H2); v3; v4(= ), respectively. Using v to v4 and i to i4, we can calculate parameters b; N; b2; N2 as follows. N = b = N2 = b2 = log( i2 i ) log( v2 T H v T H ) i(v4 T H ) Nn (v T H ) N ( + v4) ; log( i4 ) i3 log( v4v2 ; v3v2 ) i3 (v4 T H ) N2n (v3 v2) N2 ( + v4) ; ; ()

3 I D [ma].8 I D [ma] n-th power law MODEL Our MODEL.6.4 n-th power law MODEL Our MODEL.2.2. ID. ID GS GS GS [] GS [] Figure 3: I- characteristics of series connected MOSFETs with an input voltage( GS) applied to the top of the MOSFETs. Figure 4: I- characteristics of series connected MOSFETs with an input voltage( GS) applied to the bottom of the MOSFETs. where i3 = b( + v4)(v4 T H ) nn (v3 T H ) N i3; i4 = b( + v4)(v4 T H ) n i4: The parameter n is extracted by n = log( i4 i5 ) log( v4 T H v5 T H ) where i5 is the drain current when another supply voltage v5 is applied to all the gates and the output node of the series-connected MOSFETs. 3.2 Calculating equivalent capacitance In this subsection, we describe how to calculate parameters of equivalent capacitances C GD and C pa shown in Fig. 2. The parameter C GD represents the sum of feed-forward capacitances related to the MOSFETs to which input signal is applied. The feedforward capacitance indeed depends on the operating condition of MOSFET. We assume that a turning-on MOSFET operates in the saturation region and turning-off MOSFET operates in the linear region during input transition. Then C GD with rising input is represented by the following equation. C GD = CGDOp + CGDOn + CGp (2) 2 where CGDO is a gate-to-drain overlap capacitance and CG is a gate-to-channel capacitance. Input capacitance C GD with falling input can be obtained by exchanging NMOS parameters with PMOS ones. The parameter C pa represents an equivalent parasitic capacitance. We can calculate the parameter by using analytical methods proposed in [, 2] or a numerical method as follows. First, we calculate a delay of the stage by circuit simulation under a typical condition of and output load. We then search the value of the equivalent capacitance so that the delay calculated by our formula is equal to that obtained by circuit simulation. : I DS D( v4,i4) TH A(v,i) TH + 2 B(v2,i2) C(v3,i3) GS Figure 5: Drain current characteristic of series-connected MOS- FETs. IN I G I S I TOT O n I L R L C L O n2 C L Figure 6: An equivalent inverter circuit driving a CRC load.

4 Output oltage I L [ma].6 TT IN OUT R L = 5 Ω C = O C =.5 pf L.2 DO. R L = k Ω C = O C = pf L TH TH t DO Region (A) (B) (C) Time time[nsec] The time at which input voltage reaches THn Figure 8: Waveforms of the current I L obtained by circuit simulation. Figure 7: Operating regions of a CMOS inverter circuit. I S 4 Analysis of the output waveform In this section, we describe a method to derive the output voltage for the equivalent inverter circuit driving a CRC load. In [3] we have derived the output waveform of an inverter circuit driving a CRC load. Based on the method, we derive a formula for the output waveform which is applicable to an equivalent inverter with new MOSFET model described in Section 3. In the derivation of the formula, we consider the short channel effect during input transition which is neglected in [3] and thereby improve the accuracy over [3]. Figure 6 shows an inverter circuit under consideration. A CRC load (capacitance C O, resistance R L, capacitance C L) is connected to the output node, where the capacitance C O includes the equivalent parasitic capacitance C pa. A gate-to-drain capacitance C GD is connected from the input node to the output node. Now let s consider the case of rising input, which has a ramp shaped waveform and changes from ground to during time. Currents I S, I L and I G represent the currents flowing through the pmosfet, the resistance R L and the gate-to-drain capacitance C GD, respectively. oltages O and L are the voltages across C O and C L respectively. Figure 7 shows operating regions of the CMOS inverter circuit. The derivation of the output waveform formula is separated into two regions: during and after input transition, which will be explained next. 4. Analysis during input transition The differential equations which govern the behavior of the inverter circuit during input transition are written by C O d O dt + I L + IS + IG = ( + n O)ID(t) (3) I L = CL d L dt ; (4) I L = L O R L ; (5) d(s rt O) I G = CGD ; (6) dt I Smax THn DD IN DD THp Figure 9: A short-circuit current waveform assumed in our method. 8 >< I D (t) = >: B(s rt T H ) N : nt t t 2n, B(s rt T H ) N B2(srt T H2) N2 : 2 n t tt, where s r DD, n = T Hn, 2 n = T H2n, B = ( T Hn ) nn b; B2 = ( T Hn ) nn2 b2. Subscripts n and p represent parameters of nmosfets and pmosfets respectively. Equation (3), however, cannot be solved in a strictly analytical way. We therefore introduce some approximations on the waveforms of I L and I S as explained below. We approximate the short-circuit current by a piece-wise linear function, the current flowing through the resistive load by a product of an unknown function and a linear function of time. These assumptions are made from empirical observations by circuit simulation. Figure 8 shows waveforms of the current I L when a rising input of transient time. ns is applied. The waveforms are obtained by simulation. This figure indicates that the current I L increases almost monotonously after the time n at which the input voltage reaches the nmosfet threshold voltage. t (7)

5 Therefore we represent the function of I L by a product of a linear function of time t and an unknown function (t), as follows. I L = (t) (t n ): (8) Figure 9 shows the approximated short-circuit current waveform [3]. The parameter IN is a logical threshold voltage of the inverter circuit which can be calculated analytically, and we define I IN. The parameter I Smax is an unknown parameter to be solved. By using these assumption, the output voltage O is expressed as follows (the detailed solution is shown in [3]). O = DD C eff 2 ( + n )I D (t)dt C GD s r t n n(dd O)ID(t)dt n where C eff is expressed by n I S (t)dt C eff = (t ntt )(C O + CL) + 2RLCLC O (t n ) + 2RLC L : () If the parameter n is very small, the last term in the right-hand side of Eq. (9) can be safely neglected and Eq. (9) is the formula we want to derive. However if the parameter n is large and in addition O becomes far below at the end of region (A), the last term in the right-hand side of Eq. (9) cannot be neglected. In this case, we first obtain an approximate function of O, then substitute the approximate function(o) into the last term in Eq. (9), and finally obtain a formula of the output waveform. The approximate function O is obtained by solving the following equation which is derived from Eq. (9) by neglecting the non-dominant terms of C GD s r t R and t ISdt. O = ( + n)id(t)dt C eff n n(dd O )I D(t)dt () nt Differentiating the above equation by t and solving the differential equation by approximating dc eff dt ', we can derive O. Substituting O into Eq. (9), we derive the output voltage O as follows. O = f + ( + n ) exp( n F )g n + C GD s rt + I Sdt (2) C eff C eff n F = I D(t)dt: (3) C eff n The integration of I D is derived from Eq. (7). Since the unknown parameter I Smax in Fig. 9 is obtained as a closed-form formula by a method similar to [3], the integration of I S is straightforward. The output waveform with falling input can be obtained in a similar way, by exchanging nmosfet parameters with pmosfet ones and subtracting the calculated value from. (9) I DS [ma] DO Figure : MOSFET models. 4.2 Analysis after input transition DS [] BSIM model n-th power law model PWL function Now we describe analysis after input transition. In this region, the turning on MOSFET operates in the saturation region at first and finally in the linear region, which are expressed as Region (B) and (C) respectively in Fig. 7. In these regions we express the MOSFET characteristics by the following piece-wise linear function, which is shown in Fig.. I DS = IDO( + DS) I DS = DS R DS DO DS DO where I DO B(DD T H ) N B2(DD T H ) N2 and R is an equivalent resistance in the linear region of the MOSFET. The derivation of output waveform in this region is the same as that of inverter circuit described in [3]. 4.3 The evaluation of our formula In this section we first evaluate the accuracy of the output waveform formula for a CMOS inverter gate. The process technology assumed is a.6m CMOS. Figure shows the output waveforms ( O in Fig. 6) of a CMOS inverter circuit driving a CRC load under various interconnect resistances(r L=, 5, 5[]). Total capacitive load C total is.pf. C O and C L are set to =6C total and 5=6C total respectively[]. Transition time of the input signal is 2ns. We can see that the output waveforms calculated by our formulas are close to those obtained by. We have compared the gate delay and the output transition time of a CMOS inverter circuit by our formulas with simulation under various conditions in Table. The gate delay is the time from 5% of the input voltage to 5% of the output voltage. The output transition time is calculated by dividing the elapsed time from 8% to 2% of the output voltage by.6. Capacitive loads C O and C L are.2pf and.pf respectively. We can see the influence of resistive load is remarkable on the gate delay. When the load resistance R L is.5k, the gate delay becomes less than half of that obtained when the load is purely capacitive. On the gate delay the error of our formula is less than 4% from in our experiments. We find that the output transition time calculated by our formula tends to have smaller value than those by. One of the reasons is that we express the drain current characteristic of turning-on transistor

6 oltage[] d mq I I2 I4 I5 q ck I3 I6 Eqs. Figure 3: A falling edge triggered DFF. 2.. R L =.5kΩ R L = R L =.5kΩ mq:h I4 mp2 mp H mn mn2 I6 mp5 L mp6 I5 q mp4 mp3 mn time[ns] Figure : Output waveforms of a CMOS inverter driving a CRC load. Equivalent inverter chain ck Shrink mn4 mp5 mp6 q Unactive path Table : Comparison of gate delay and output transition time between our formula and in a CMOS inverter(gate length=.6m, =3.3v,C O=.2pF, C L=pF). Gate delay[ns] Output transition time[ns] tt RL Eqs. Error Eqs. Error [ns] [] [ns] [ns] [%] [ns] [ns] [%] after input transition by a piece-wise linear function which is not accurate enough near segmented boundary. Next we evaluate the proposed modeling method for seriesconnected MOSFETs. Figure 2 compares the gate delay of a 4 input NAND gate obtained by and the gate delay obtained by our formula. In Fig. 2 (a), the n-th power law MOSFET model is used, whereas in Fig. 2 (b) the proposed MOSFET model of Eq. () is applied. The equivalent parasitic capacitance C pa is determined so that the gate delay calculated by our timing model is equal to that obtained by simulation at C L=.5[pF] and =.5[ns]. We can find that the error of the gate delay calculated with the n-th power law MOSFET model tends to become large when the input transition time becomes large. On the other hand, the gate delay calculated with the proposed MOSFET model is close to that obtained by simulation. Figure 4: The method of replacing a DFF to an equivalent inverter chain for the propagation delay estimation from the clock input ck to the output q. 5 Application to a DFF cell Our gate delay model can be applied to various CMOS logic gates that do not include path transistors. In this section we examine the case that a cell includes feedback loops in the structure. Figure 3 shows a falling edge triggered D type flip-flop including some clocked inverters. The propagation delay from the clock input ck to the output q is examined. Let s consider the case that the output q rises when the clock ck falls. We assume that the initial states of the input d, the internal node mq and the output node q are high, high, and low, respectively. In this case, the pmos block of the clocked inverter I4 and the nmos block of I6 are not active from the beginning to the end (See Fig. 4). We can therefore obtain an equivalent inverter chain of the DFF by replacing the nmos block of I4 and the pmos block of I6 to equivalent MOSFETs as shown in Fig. 4. Then we can calculate the gate delay of the DFF. Now we are studying for calculating timing constraints such as setup time and hold time. One possible method is to calculate them as the difference between the propagation time from data input to a certain internal node latching the data and that from clock node to another node. 6 Discussion Figure 5 shows an overview of the gate delay calculation by the proposed approach. The process consists of two steps: characterization step and evaluation step. In the characterization step, we calculate parameters K; m; n; B; B2; N; N2,; C pa; C GD for each input-to-output path in each stage. Only DC-analysis is required for the calculation if we use an analytical method[, 2]

7 [ns].4.35 Using n-th power law MODEL [ns].4.35 Using proposed MODEL.3 =.[ns].3 =.[ns].25 =.5[ns].25 =.5[ns].2.2 =2.[ns] =2.[ns] Output load capacitance [pf] (a) Using the n-th power law MOSFET model [pf] Output load capacitance (b) Using the proposed MOSFET model Figure 2: Comparison of the gate delay of a 4 input NAND gate(r L = ). for the derivation of C pa. If we choose to derive C pa by circuit simulation, we need several transient analysis additionally. In the evaluation step for gate delay calculation, we first need to derive an equivalent output load in a form of CRC circuit from actual RC interconnect network. This can be done by a model reduction method such as AWE. Given a CRC load, we are ready to evaluate the gate delay by our formula. We can calculate the output waveform in various operation conditions including different supply voltages without any re-characterization. Figure 6 shows the gate delay of a NAND4 gate with a rising input under various supply voltages. With a single set of model parameters, the accuracy of our gate delay model does not degrade over wide range of supply voltages. We applied our gate delay model to logic gates made up of a single or multiple stages. Table 2 shows the maximum and average error of our model for all the input-to-output paths in each gate under various operating conditions listed in Table 3. The error is less than % from in the experiment. The error tends to become large when the stage of the gate is larger than two. One possible reason is the approximation of the waveform at an internal node to a ramp-shaped one. To extend our method to a gate with a skewed input waveform is our future work. Table 4 shows the comparison of CPU time between a circuit simulator() and our timing model. We can see our timing model can calculate the gate delay and the output transition time about times faster than circuit simulation. 7 Conclusion We have proposed a gate delay model of CMOS logic gates driving a CRC load. Our timing model can calculate the gate delay about three-order faster than a simulation based approach within the errors of less than %. Moreover our timing model can calculate the gate delay under various supply voltage without recharacterization, which will enable us to optimize the circuit speed and power dissipation in ASIC design. Characterization For each process: TH of nmos and pmos CELL A: Each path c to y b to y a to y parameters K m n B B2 N N2 λ C pa C GD of nmos block and pmos block number of the stage Cell B: Cell C: Circuit AWE a b A... c Calculate Gate delay using analytical formula In various, gate delay driving point analysis and C,R,C load parameters. Figure 5: Overview of the gate delay calculation.... Acknowledgment The authors would like to thank Tomokazu Kondo for his valuable discussion and contribution to experiments.

8 Gate delay [ns] Our gate delay model =.ns, C total =2pF =.5ns, C total =.5pF.5 =2.ns, C total =.pf Supply voltage[] Figure 6: The gate delay of a 4 input NAND gate in various supply voltage (R L = ). Table 2: The error of our gate delay model in several gates. Gate name Ave. error Max. error Ave. error Max. error rise rise fall fall Single stage cells IN NAND NOR AOI AOI OAI OAI Multiple stage cells BUF AND OR DFF Table 3: Parameters used for the evaluation shown in Table 2. parameter values.,.2,.5,., 2. [ns] C total.,.2,.5,., 2. [ps] R L, 48, 24, 48 [] C O = 6 Ctotal and CL = 5 Ctotal. 6 Table 4: Comparison of CPU time for calculating the gate delay and the output transition time under patterns of skew and loading conditions. Cell No. of Proposed method Ratio MOSs [sec] [sec] IN :4 2 2 DFF :4 2 3 References [] P. R. O Brien and Thomas L. Savarino, Modeling the Driving- Point Characteristic of Resistive Interconnect for Accurate Delay Estimation, Proc. of ICCAD 89, pp , Nov [2] N. Hedenstierna and K.O. Jeppson, CMOS Circuit Speed and Buffer Optimization, IEEE Trans. Computer-Aided Design, ol. CAD-6, No. 2, pp , Mar [3] T. Sakurai, and A. R. Newton, A simple MOSFET model for circuit analysis, IEEE Trans. Electron Devices, vol. 38, no. 4, pp , Apr. 99. [4] K. O. Jeppson, Modeling the Influence of the Transistor Gain Ratio and the Input-to-Output Coupling Capacitance on the CMOS Inverter Delay, IEEE J. of Solid-State Circuits, vol. 29, no. 6, pp , Jun [5] S.H.K. Embabi, Delay Models for CMOS, BiCMOS, and BiNMOS Circuits and Their Applications for Timing Simulations, IEEE Trans. Computer-Aided Design, pp , Sep [6] Pasquale Cocchini, Gianluca Piccinini, and Maurizio Zamboni, A Comprehensive Submicrometer MOST Delay Model and Its Application to CMOS Buffers, IEEE J. of Solid-State Circuits, vol. 32, no. 8, Aug [7] Cristiano Forzan, Bruno Franzini and Carlo Guardiani, Accurate and Efficient Macromodel of Submicron Digital Standard Cells, Proc. of ACM/IEEE Design Automation Conference, 997. [8] A. Hirata, H. Onodera, K. Tamaru, Estimation of Short- Circuit Power Dissipation and its Influence on Propagation Delay for Static CMOS Gates, Proc. of ISCAS 96, ol. 4, pp , May 996. [9] Florentin Dartu, Noel Menezes, Jessica Qian, and Lawrence T. Pillage, A Gate-Delay Model for High-Speed CMOS Circuits, Proc. ACM/IEEE Design Automation Conference, pp , 994. [] T. Sakurai, Delay analysis of series-connected MOSFET circuits, IEEE J. Solid-State Circuits, vol. SC-26, no.2, pp. 22-3, Feb. 99. [] Hau-Yung Chen and Santanu Dutta, A Timing Model for Static CMOS Gates, Proc. of ICCAD 89, pp , Nov [2] A. Nabavi-Lishi and N.C. Rumin, Inverter Models of CMOS Gates for Supply Current and Delay Evaluation, IEEE Trans. Computer-Aided Design, pp , Oct [3] A. Hirata, H. Onodera, K. Tamaru, Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC Load, IEICE Trans. Fundamentals of Electronics, ol. E8-A, no. 3, pp , 998.