GaN HEMT EiceDRIVER TM 1EDi product family

Transcription

1 GaN HEMT EiceDRIVER TM 1EDi product family Single-channel functional and reinforced isolated gate-driver for enhancement mode GaN HEMTs Features dedicated gate driver for GaN power switches with non-isolated gate (CoolGaN, GIT) supports all switch-specific requirements low driving impedance (on-resistance 0.85 source, 0.35 sink) resistor programmable gate current (typ. 10mA) in steady on -state programmable negative gate voltage to completely avoid spurious turn-on single output supply voltage (typ. 8 V, floating) no duty-cycle dependence of switching behaviour (2 off -voltage levels) differential concept ensures negative gate drive voltage under any condition fast input-to-output propagation (37 ns) with excellent matching (+7/-6 ns) input-to-output isolation based on coreless transformer (CT) technology Common mode transient immunity (CMTI) > 150 V/ns 2 package versions 1EDF5673K: 13-pin LGA (PG-TFLGA-13-1) with functional isolation (1.5 kv) 1EDS5663H: 16-pin P-DSO (300mil, PG-DSO-16-30) with safe isolation (6 kv) qualified for industrial applications according to JESD47 and related standards Application Description CoolGaN and related power switches require a continuous gate current of a few ma in their on state. Besides, due to low threshold voltage and extremely fast switching transients, a negative off -voltage level might be needed. The widely used concept of a standard RC-coupled gate driver fulfils these requirements, however it suffers from two drawbacks: a duty-cycle dependence of switching dynamics and the lack of negative gate drive in specific situations (see ch. 1.1) Infineon s 1EDi EiceDrivers solve this issues with very low effort. The additional two switches shown in Fig.1 enable a second off -level (0V) to eliminate the described duty-cycle dependence. And the differential topology can always provide a negative gate drive voltage without a permanent negative supply voltage. The concept requires a floating supply voltage (commonly used with GaN switches due to their Kelvin Source connection); besides, it is not possible to generate the high-side supply in a half-bridge topology via bootstrapping. Figure 1 Typical Application Preliminary Datasheet Please read the Important Notice and Warnings at the end of this document V1.0 page 1 of 16

2 Potential Applications High-voltage AC/DC conversion High-voltage DC/DC conversion Server Telecom Isolation and Safety Approval 1EDS5663H with reinforced isolation: certification planned by VDE, UL, CSA, CQC according to DIN V VDE V ( ) with V IOTM = 8 kv pk, V IOSM = 6.25 kv pk (tested at 10kVpk) UL1577 (Ed. 5) opto-coupler component isolation standard with VISO = 5700 V RMS IEC60950 and IEC system standards and corresponding CQC certificates 1EDF5673K with functional isolation: production test with 1.5 kv for 10 ms Product Versions In accordance with the isolation classification for primary and secondary side control, 1EDi is available in different package versions Table 1 GaN HEMT EiceDRIVER TM 1-EDi product family overview Part Number Package source/sink output resistance UVLO Isolation Class Input-to-output isolation Rating Surge testing Safety Certification 1) 1EDF5673K LGA13 5mm* 5mm 0.85Ω / 0.35Ω 5V functional V IO = 1.5 kv DC n.a. n.a. 1EDS5663H WB- DSO16 10mm* 6mm 0.85Ω / 0.35Ω 5V reinforced (safe iso.) V IOTM = 8 kv pk (VDE ) V ISO=5,7 kv RMS (UL1577) V IOSM >10 kv pk (IEC60065) VDE ; UL1577; IEC60950, (CQC) 1) certifications planned Preliminary Datasheet 2 of 16 V1.0

3 Table of contents Table of contents Pin Configuration and Description Driving HV GaN Transistors with 1EDi: Motivation and System Description Block Diagram Functional Description 1EDi Isolation Power Supply Input Supply Voltage VDDI Output Supply Voltage VDDS/G Driver outputs Undervoltage Lockout (UVLO) CT Communication and Data Transmission Characteristics Absolute Maximum Ratings Thermal Characteristics Operating Range Electrical Characteristics Timing Diagrams Revision history Preliminary Datasheet 3 of 16 V1.0

4 1 Pin Configuration and Description DSO-16 (300 mil) PWM 1 16 VDDS LGA-13 (5 x 5 mm) N.C OUTS GNDI 1 13 VDDS VDDI 3 14 GNDS PWM 2 12 OUTS GNDI DISABLE 4 5 1EDS5663H N.C. N.C. N.C. SLDO 3 4 1EDF5673K 11 GNDS TNEG 6 11 VDDG DISABLE 5 10 VDDG N.C OUTG TNEG 6 9 OUTG SLDO 8 9 GNDG VDDI 7 8 GNDG Figure 2 Table 2 Pin Configuration for DSO-16 and LGA-13 package, top view Pin Description Pin DSO Pin LGA Symbol Description 1 2 PWM Input signal (default state Low) Controls switching sequence at OUTG and OUTS 2 3 N.C. Not connected 3 7 VDDI Supply voltage input chip (+ 3.3V) 4 1 GNDI GND input chip 5 5 Disable 6 6 TNEG Input signal (default state Low) Logic High sets both outputs to low state Resistor programmable input to control the duration t 1 of negative off level (Fig. 5); t 1 = R t1 * 2pF 7 7 N.C. Not connected 8 4 SLDO Connected to VDDI: VDDI directly supplies input chip Connected to GNDI: Internal shunt regulator activated 9 8 GNDG Ground for OUTG 10 9 OUTG Output connected to GaN gate VDDG Positive supply voltage for gate connected switch 12 - N.C. Not connected 13 - N.C. Not connected GNDS Ground for OUTS (has to be connected with GNDG) OUTS Output connected to GaN source VDDS N.C. pins should be kept floating Positive supply voltage for source connected switch (has to be connected with VDDG) Preliminary Datasheet 4 of 16 V1.0

5 1.1 Driving HV GaN Transistors with 1EDi: Motivation and System Description Certain types of gallium nitride (GaN) transistors differ significantly from MOSFETs as their gate is not isolated from the channel, but behaves like a diode with a forward voltage V F of 3 to 4V. Equivalent circuit and typical gate input characteristic are given in Fig. 3. In the steady on state a continuous gate current of is required to achieve stable operating conditions. The switch is normally-off, but the threshold voltage V th is rather low (~ +1V). This is why in certain applications a negative gate voltage -V N instead of 0 is required to safely keep the switch off (Fig. 3b). Figure 3 Equivalent circuit (a) and gate input characteristics (b) of typical normally-off GaN HEMT Obviously the transistor in Fig. 3 cannot be driven like a conventional MOSFET due to the steady-state on current I ss and the eventually needed negative off voltage V N. While an I ss of a few ma is sufficient, fast switching transients require gate charging currents I on and I off in the 1A range. To avoid a dedicated driver with 2 separate on paths and bipolar supply voltage, the solution depicted in Fig. 4 is usually chosen, combining a standard gate driver with a passive RC circuit to achieve the intended behavior. The high-current paths containing the small gate resistors R on and R off, resp., are connected to the gate via a coupling capacitance C C. C C is chosen to have no significant effect on the dynamic gate currents I on and I off. In parallel to the high-current charging path the much larger resistor R ss forms a direct gate connection to continuously deliver the small steady-state gate current I ss. In addition, C C can be used to generate a negative gate voltage. Obviously, in the on -state C C is charged to the difference of driver supply V P and diode voltage V F. When switching to the off state this charge is redistributed between C C and C GS and causes a negative V GS of value V N = C C (V P V F ) Q Gtot C C + C GS immediately after switching off. During the off state V N decreases by discharging C C via R SS. The associated time constant cannot be chosen independently, but is related to the steady-state current and is typically in the 1s range. The negative gate voltage at the end of the off phase (V Nf in Fig. 4d) thus depends on the duration of the off phase. It lowers the driver voltage V P for the following switching on event, resulting in a dependence of switching dynamics on frequency and duty cycle as one drawback of this solution. A second problem might happen if two switches are used alternately in a halfbridge configuration. In normal operation always one of the switches is on, and before switching on the other one, it has to be switched off, thereby generating the negative gate voltage V N. The usually short period with both switches off (dead time t d ) does not cause a significant reduction of V N. If, however, there is by any reason a longer period with both switches in off -state (e.g. during system start-up, burst mode operation etc.), both capacitors C C will be discharged. That means, for the first switching pulse after such an extended non-switching period no negative voltage is available. This could lead to increased transistor stress due to spurious turn-on effects in halfbridge topologies. Preliminary Datasheet 5 of 16 V1.0

6 Figure 4 Equivalent circuit of GaN switch with RC gate drive (a), gate charge curve (b) and time dependence of gate current I G (c) and gate-to-source voltage V GS (d) To solve the problems described above a shape of V GS like that in Fig. 5b) would be required rather than the one in 5a) that results from the simple RC circuit. As explained, a negative V GS might be needed for safe off states during the switching transients, but it should be as low as possible. This is due to the lack of a physical body diode causing any negative V GS to add to the voltage drop of a GaN transistor in reverse polarity (diode operation) and by that increase conduction losses during dead time. Thus in the idealized waveform of Fig. 5b) V GS is switched to the minimum required V N for a constant time t 1 longer than the system dead time t d. After that V GS is switched back to zero to ensure identical conditions for the next switch on event and to minimize losses from diode operation. If, however, an off state lasts for a time t 2 significantly longer than a normal switching period 1/f sw (e.g. several s), V GS should be switched again to V N to avoid any kind of first pulse problem in half-bridge operation. Figure 5 V GS voltage with RC circuit (a), improved (b) and modified shape (c) Preliminary Datasheet 6 of 16 V1.0

7 The conceptual goal of 1EDi is to provide the gate voltage of Fig. 5b) or a functionally equivalent one with the lowest possible effort. This is achieved by slightly modifying the gate drive waveform as depicted in Fig. 5c. The off level after a long deadtime need not be the optimized negative voltage V N, it could also be the more negative level V P. As these first pulse situation happens very rarely compared with regular switching cycles, the resulting higher reverse voltage drop has negligible effect on switching losses. Although going from the 3-level signal of Fig. 5b) to the 4 levels of Fig. 5c) seems to increase complexity at first sight, this is finally not true. Waveform 5c) can be realized in a very convenient way, if V N is generated by the RC network as described before. Then the differential driver concept of Fig. 6a) with switch control signals as given in Fig. 6b) is able to fulfil all discussed requirements with least effort: a single supply voltage, 4 switches and 4 connection pins are sufficient. As mentioned, utilizing V P instead of V N only during extended off -phases has no impact on switching losses. However, care has to be taken when switching on again, because C C is fully charged to V P in this first pulse situation and no current flow is possible via the capacitive path. With the standard switching-on scheme (open S 1 / close S 2 ) the transient current thus would be limited to the small steady-state current. To achieve a faster turn-on, C GS will be discharged prior to the on -transient by switching on S 3 for a short time t 3 before initiating the actual on -transient via S 1 and S 2. A t 3 -duration of typically 20ns is sufficient. R ss PWM t 2 >> 1/f sw S 1 R tr C C S 2 + S 1 S 3 S 3 t 1 t 3 V P S 4 S 2 S 4 V GS -V N -V P Figure 6 a) 1EDi (a) and switch control signals (b) b) In the topology of Fig. 6a) a single resistor R tr is responsible for setting the maximum transient charging and discharging current. This is often acceptable. If it is not, an additional resistor R off with series diode in parallel with R tr can be used to realize different impedances for on and off transients, resp. All relevant driving parameters are thus easily programmable by choosing V P, R ss, R tr, R off and C C according to the relations V N = C C (V P V F ) Q Gtot C C + C GS (1) I ss = V P V d R ss, I on = V P V th R tr, I off = V th + V N R off Preliminary Datasheet 7 of 16 V1.0

8 Input-to-output isolation 1.2 Block Diagram A simplified functional block diagram is given in Fig. 7. The 4 output switches are placed on 2 separate dies. Isolation between input and outputs is achieved by means of two coreless transformer structures (CT) situated on the input die. VDDI UVLO in UVLO outs VDDS SLDO SLDO TX RX Control Logic OUTS PWM GNDI Control Logic GNDS UVLO outg VDDG DISABLE GNDI TX RX Control Logic OUTG TNEG Delay t 1 GNDI GNDG Figure 7 Block Diagram Preliminary Datasheet 8 of 16 V1.0

9 2 Functional Description 1EDi 2.1 Isolation 1EDi is available in two versions according to different classes of input-to-output isolation voltage requirements 1EDF5673K in LGA-13 5*5 mm 2 package for functional isolation (1.5kV) 1EDS5663H in DSO-16 wide-body package for reinforced safe isolation (6kV) In SMPS functional isolation is typical for high-voltage systems that are controlled from their primary side, whereas HV switches controlled from the secondary side require safe isolation. The safe isolation version 1EDS5663H is tested according to VDE / IEC standards to fulfil the lifetime requirements for the isolation barrier (37.5 years). As the CT forming this barrier is placed on the input chip, a true fail-safe isolation is achieved, i.e. even in case of a destruction of the power switch the driver input remains safely isolated from the output. 2.2 Power Supply Due to the isolation between input and output side, 1EDi-G1 requires two power domains with independent power management. Undervoltage Lockout (UVLO) functions for both input and output chips ensure a defined start-up and robust functionality under all operating conditions Input Supply Voltage VDDI The input chip is supplied via VDDI with a nominal voltage of 3.3 V. Power comsumption to some extent depends on switching frequency, as the input signal is converted into a train of repetitive current pulses to drive the CT. Due to the chosen robust encoding scheme the average repetition rate of these pulses depends on the switching frequency f sw (for f sw < 500kHz this effect is very small). 1EDi can be operated also with input supply voltages higher than 3.3 V. Then a shunt LDO voltage regulator (SLDO) is enabled by connecting pin SLDO to GND. The SLDO regulates the current through an external resistor R VDDI connected between the external supply voltage V DD and pin VDDI as depicted in Figure 1 to generate the required voltage drop. For proper operation it has to be ensured that the current through R VDDI always exceeds the maximum supply current I VDDI of the input chip. As the shunted current difference is limited to 8mA, R VDDI has to fulfil V DD 3.3V 8mA + I VDDI,max < R VDDI < V DD 3.3V I VDDI,max A typical choice for V DD = 5 V could be R VDDI = 470, resulting in sufficient margin between resistor current and maximum operating current. Dynamic current peaks are provided by a blocking cap (10 to 22 nf) between VDDI and GNDI Output Supply Voltage VDDS/G Both output chips and the respective switch halfbridges are supplied by a common voltage of typically 7 to 8 V between pins VDDS/G and GNDS/G. A ceramic bypass capacitance of 10 to 22 nf is recommended. The output supply must be floating with respect to the input supply system. This is not only required by the Kelvin source connection of the GaN switch (results in inductive voltage peaks between input and output ground during switching transient), but also by the differential driving concept of 1 EDi as explained in chapter 2. Again the minimum operating supply voltage is set by an undervoltage lockout function (UVLO out ), operating independently of the input UVLO function. Preliminary Datasheet 9 of 16 V1.0

10 2.3 Driver outputs The rail-to-rail driver output stage realized with complementary MOS transistors is able to provide a typical 4 A sourcing and 8 A sinking current. Although these current levels are neither needed nor reached when driving GaN HEMTs (due to their low gate charge of only a few nc), the low on-resistance coming together with high driving current is nevertheless beneficial. With an R on of 0.85 for the sourcing pmos and 0.35 for the sinking nmos transistor the driver can be considered as a nearly ideal switch. The gate drive parameters can thus be determined easily and accurately by the external components as described in chapter 2. The p-channel sourcing transistor allows real rail-to-rail behavior without suffering from a source follower's voltage drop. 2.4 Undervoltage Lockout (UVLO) The Undervoltage Lockout function ensures that the outputs can be switched only, if both input and output supply voltages exceed the corresponding UVLO threshold voltages. Thus it can be guaranteed, that the switch transistors are not operated if the driving voltage is too low for complete and fast switching on, thereby avoiding excessive power dissipation. The UVLO levels for the output supplies are set to a typical on value of 4.5 and 5.5 V (with 0.3 V hysteresis) for VDDG and VDDS, resp., whereas UVLO in for VDDI is set to 2.85 V with 0.15 V hysteresis. The different UVLO levels for OUTG and OUTS help to safely avoid any erroneous turn-on of the GaN switch despite the low GaN threshold voltage. Special attention has been paid to cover all possible operating conditions, like start-up or arbitrary supply voltage situations - if VDDI drops below UVLO in, a switch-to-low command is sent to output OUTG, whereas OUTS is switched to high - for VDDS and/or VDDG lower than the respective UVLO levels, an effective clamping concept has been realized by means of 100 k resistors connecting the outputs to the respective gates of the sourcing pmos transistors in the output stage As the result, the 1EDi concept is able to guarantee safe operation of a GaN switch under any circumstances. 2.5 CT Communication and Data Transmission A Coreless Transformer (CT) based communication module is used for PWM signal transfer between input and output chips. A proven high-resolution pulse repetition scheme in the transmitter combined with a watchdog timeout at the receiver side enables recovery from communication fails and ensures safe system shut-down in failure cases. Besides, the repetition scheme is also used to signal a first pulse situation (Fig. 6). If an off state lasts longer than 32 µs, the repetition rate of the CT pulses is reduced to a value that causes the watchdog on the output chip to wake up and initiate a change in the off state acc. to Fig. 6 (switch S3 to off and S4 to on state). Preliminary Datasheet 10 of 16 V1.0

11 3 Characteristics 3.1 Absolute Maximum Ratings The absolute maximum ratings are listed in Table 3. Stresses beyond these values may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3 Absolute Maximum Ratings Parameter Symbol Values Unit Remarks Min. Max. Supply voltage input chip VDDI V Supply voltage output chips VDDS/G V Voltage at pins PWM and DISABLE V IN V Voltage at pins TNEG and SLDO V INPUT V Voltage at pins OUTS, OUTG V OUT -0.3 VDD V Junction temperature T J C Storage temperature T S C Soldering temperature 260 C reflow soldering 1 Soldering temperature 260 C wave soldering ESD capability V ESD_HBM 2 kv Human Body Model 2 V ESD_CDM 0.5 kv Charged Device Model 3.2 Thermal Characteristics Table 4 Thermal Characteristics Parameter Symbol Typ. value Unit Remarks Thermal resistance Junction-Ambient R thja K/W PG-DSO-16, wide body, T A =25 C Thermal resistance Junction-Case R thjp25 44 K/W PG-DSO-16, wide body, T A =25 C Thermal resistance Junction-Ambient R thja25 59 K/W PG-LGA-13, 5 x 5 mm, T A =25 C Thermal resistance Junction-Case R thja25 32 K/W PG-LGA-13, 5 x 5 mm, T A =25 C 1 According to JESD22A111 2 According to EIA/JESD22-A114-B (discharging 100pF capacitor through 1.5k resistor) Preliminary Datasheet 11 of 16 V1.0

12 3.3 Operating Range Table 5 Operating Range Parameter Symbol Values Unit Remarks Min. Typ. Max. Supply voltage input chip VDDI V if operated directly without SLDO Supply voltage output chips VDDS/G V min. defined by UVLO out VDDI blocking capacitance C VDDI 22 nf SLDO active Logic input voltage at pins PWM and DISABLE V IN V Voltage at pins TNEG and SLDO V INPUT V Ambient temperature T A C Junction temperature T J C 3.4 Electrical Characteristics Unless otherwise noted, min./max. values of characteristics are the lower and upper limits, resp. They are valid within the full operating range. Typical values are given at T J = 25 C with V DDI = 3.3V and V DDS/G = 7V. Table 6 Power Supply Parameter Symbol Values Unit Remarks Min. Typ. Max. VDDI quiescent current I VDDIqu 1.4 ma f sw < 500kHz VDDS/G quiescent current I VDDSG 1.3 ma no switching; total current for both outputs Undervoltage Lockout input (UVLO in ) turn on threshold UVLO in V UVLO in turn off threshold UVLO in V UVLO in threshold hysteresis UVLO in V Undervoltage Lockout outputs (UVLO outg/s ) turn on threshold UVLO out turn off thresholds UVLO outg UVLO outs UVLO outg- UVLO outs V V - V V UVLO out threshold hysteresis UVLO outg/s V 1 not recommended for egan switches 2 continuous operation above 125 C may reduce lifetime Preliminary Datasheet 12 of 16 V1.0

13 Table 7 Logic Inputs PWM and DISABLE Parameter Symbol Values Unit Remarks Min. Typ. Max. Input voltage threshold for transition LH V INL 2.1 V independent of VDDI Input voltage threshold for transition HL V INH 1.1 V independent of VDDI Input pull down resistor R IN 100 k Table 8 Static Output Characteristics Parameter Symbol Values Unit Remarks Min. Typ. Max. High level (Sourcing) output resistance R on 0.85 T J = 25 C 1.6 T J = 150 C Peak sourcing output current I src,pk 4 A actively limited to 5A Low level (Sinking) output resistance R off 0.35 T J = 25 C 0.75 T J = 150 C Peak sinking output current I snk,pk -8 A actively limited to -10A Table 9 Dynamic Characteristics (see Fig. 8, 9) Parameter Symbol Values Unit Remarks PWM to OUTS propagation delay PWM to OUTG propagation delay t PDonS t PDoffS t PDonG t PDoffG 31 DISABLE to OUTS propagation delay t PD_DIS_ON, t PD_DIS_OFF Min. Typ. Max t PDoffG + 4 t PDonS + t ns ns ns load between OUTS and GNDS C LS = 1.8nF load between OUTG and GNDG Z LG = 1.8nF//20 65 ns C LS = 1.8nF Rise time OUTS/OUTG t rise ns C LS = C LG = 1.8nF, 10% to 90% Fall time OUTS t fall ns C LS = 1.8nF, 90% to 10% Minimum input pulse width that changes output state Duration of negative gate off voltage Minimum off time before entering first pulse mode t PW 18 ns t ns R t1 = 100k t 2 32 µs Discharging time in first pulse mode t 3 20 ns Preliminary Datasheet 13 of 16 V1.0

14 3.5 Timing Diagrams Figure 8 depicts rise, fall and delay times as observed at the capacitively loaded outputs OUTS and OUTG, resp. As OUTG is not actively switched to low, a resistor in parallel with the load capacitance has to be used for testing. In addition to the signal propagation delay t PDon, the rising edge of OUTG is delayed by a time t 1 defining the duration of negative V GS. t 1 can be controlled via the resistor R t1 connected to input TNEG (t 1 = R t1 * 2pF). PWM V INH V INL 90% 90% OUTS 10% 10% t PDon t PDoffS t rise 90% t fall Figure 8 t PDoffG 10% OUTG 10% Propagation delay, rise and fall time t 1 t rise Figure 9 illustrates a complete switching sequence of the four switches forming the two output stages of 1EDi (delay, rise and fall times not shown). The sequence in the left part of Fig. 9 corresponds to the normal switching operation, whereas in the right part the first pulse situation is depicted. This situation is assumed to happen whenever there is no switching action for an extended period t 2. Clearly t 2 must be significantly longer than a regular switching period. A typical duration of 32 µs has been chosen, as GaN switches usually operate at switching frequencies significantly above 50 khz (switching period below 20 µs). on normal operation off first pulse PWM t 2 >> 1/f sw S 1 S 2 S 3 t 1 t 3 S 4 V GS -V N -V P Figure 9 Input signal, output switch sequence and resulting V GS for normal operation and first pulse situation Preliminary Datasheet 14 of 16 V1.0

15 Revision history Document version Date of release Description of changes V st version Preliminary Datasheet 15 of 16 V1.0

16 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition Published by Infineon Technologies AG Munich, Germany 2018 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? erratum@infineon.com Document reference ifx1 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ( Beschaffenheitsgarantie ). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.