SERDES High-Speed I/O Implementation
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- Kelley Patterson
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1 SERDES High-Speed I/O Implementation FTF-NET-F0141 Jon Burnett Digital Networking Hardware A R P External Use
2 Overview SerDes Background TX Equalization RX Equalization TX/RX Equalization optimization Printed Circuit Board and System Design Considerations Simulation Model IBIS-AMI Channel simulations using IBIS-AMI model External Use 1
3 Agenda TX Equalization RX Equalization PCB and Systems Design Considerations IBIS-AMI Simulation Examples Summary External Use 2
4 High-Speed Serial Channel Analysis Serializer/Deserializer (SerDes) Transmitter (TX) uses equalization, de-emphasis Receiver (RX) uses equalization, like Feed Forward Equalization (FFE), Decision Feedback Equalization (DFE) and Continuous Time Linear Equalization (CTLE) Often proprietary designs External Use 3
5 Highlights Higher Speed SerDes busses operate with a closed eye at the pin of the Receiver in some cases RX EQ will help open the eye But RX EQ is producing a signal that is not seen at the pin How to model what is happening inside the die to offset the losses in the channel and the closed eye that they produce? IBIS-AMI modeling finer details: TX EQ effects with RX EQ Lighter/less TX EQ may help with some RX settings PCB Design at 10Gbps Every detail matters on complex channels Simpler direct connect channels less of an issue Manage Return Loss External Use 4
6 SerDes: Differential Signaling On occasion, there is confusion about the differential peak-to-peak voltage. External Use 5
7 SerDes: Differential Signaling (Continued) Note the difference between the 500 mv VDIFFp vs the 1000 mv VDIFFp-p. External Use 6
8 SerDes: Differential Signaling Example Amplitude for Blue and Green: 0 to 580 mv Transition Bit: Green Blue = = -580 mv And = 580 mv Non-Transition Bit: Green Blue = = -433 mv And = 433 mv Vdiffp: Transition Bit: 580 mv Non-Transition Bit: 433 mv Vdiffp-p: Transition Bit: 2 x 580 = 1160 mv Non-Transition Bit: 2 x 433= 866 mv Red Signal: +/- 580, +/- 433 mv External Use 7
9 SerDes Transmitter and Receiver, Simplified Generally, the SerDes TX and RX will be operating as 50 ohm single ended drivers/receivers and 100 ohm differential drivers/receivers. External Use 8
10 SerDes TX: PCI Express Gen 2.0 HW Specs list the TX Amplitude (VTX-DIFFp-p) and the TX differential impedance. In some protocols, the de-emphasis value is listed External Use 9
11 SerDes RX: PCI Express Gen 2.0 RX Specs: For Pre RX EQ SerDes, list a minimum eye opening amplitude (VRX_DIFFp-p). Also list the RX impedance External Use 10
12 Equalization Related Parameters in Freescale Documents External Use 11
13 TX EQ Parameters Listed in Reference Manual Basic TX Controls: Amplitude of the TX (Differential peak to peak) What type of TX Equalization Options for de-emphasis De-emphasis levels TX EQ Controls: AMP_RED: Amplitude of the signal TEQ_TYPE: Number of bits of Equalization Emphasis Pre-cursor: Values for Pre-cursor bit Post-cursor: Value for Post-cursor bit External Use 12
14 TX EQ in Reference Manual External Use 13
15 TX EQ in Reference Manual External Use 14
16 Background on Electrical Data External Use 15
17 Data Eye, Bit Time and Unit Interval Note: GHz vs Gbps Clock: 4 GHz Rising Edge to Rising Edge: 250 ps Bit Time: 125 ps Data Rate: 1/Bit Time or 1/UI= 1/125ps or 8 GHz So Data Rate is 2x Clock But Nyquist frequency is Clock Rate or 4 GHz External Use 16
18 Example: De-emphasis, Transition, Non-Transition Bits External Use 17
19 Example: De-emphasis, Transition, Non-Transition Bits Examine Transition (TX_DIFF_PP) vs. Non-Transition (TX_DE_EMPH_PP) Ratio log 10 * -20 (db) External Use 18
20 Example De-Emphasis Requirements for TX Model 3-tap De-emphasis: Pre-cursor Post-cursor External Use 19
21 10G SerDes 3-Tap TX Equalization External Use 20
22 Data Presentation Data usually presented at a target BER Often BER 1e-12 Can be plotted in contour plot, bathtub curve, eye density plots Automated reports list eye height and eye width at BER External Use 21
23 Equalizer Frequency Response Channel Loss: Boosted by EQ EQ targets region where channel loss is critical External Use 22
24 IBIS AMI Background External Use 23
25 IBIS-AMI: How to Gain Post RX EQ Visibility in Simulations TX EQ RX EQ IO Buffer (IBIS) IO Buffer (IBIS) Standard IBIS for two tap TX EQ or IBIS-AMI or miscellaneous models IBIS-AMI or miscellaneous models External Use 24
26 Pre- and Post-RX EQ Waveform Probing Locations Probe Here for Pre RX or No RX AMI EQ Waveform Probe Here for Post RX EQ Waveform TX EQ RX EQ IO Buffer (IBIS) IO Buffer (IBIS) Standard IBIS for two tap TX EQ or IBIS-AMI or misc models IBIS-AMI or misc models External Use 25
27 IBIS 5.0 IBIS-AMI Introduced IBIS-AMI IBIS 5.0 Release in 2008 added IBIS-AMI IBIS Algorithmic Modeling Interface (AMI) Expands IBIS Standard to include methods to model the algorithmic content in the SerDes TX and RX circuits Used especially for RX EQ IBIS IO Buffer Interface Specification (IBIS) IBIS Specification 1.0: April 1993 Used extensively for PCI bus modeling Subsequent key versions: 2.1: December : September : August Being reviewed now; substantial addition of resolution documents External Use 26
28 Example of IBIS-AMI Usage in EDA Tool External Use 27
29 Example of IBIS-AMI Usage in EDA Tool External Use 28
30 IBIS-AMI Model Sections IBIS-AMI model Top Level is.ibs file, like standard IBIS Has pin listing, signal to model name mapping, diff pair listing, etc. Uses standard analog modeling for driver impedance, capacitive loading, edge rates, etc. Parameter file.ami file Text file that is readable by user Sets values to be used in DLL model file DLL Where algorithms are modeled in AMI language Compiled to protect the proprietary TX and RX model information IBIS 5.0 compliant allows it to run in multiple tools External Use 29
31 IBIS-AMI Example Data View of.ibs,.ami and DLL/SO file listing.ibs file header.ami file listing DLL/SO files External Use 30
32 Freescale TX IBIS-AMI Model Background External Use 31
33 SerDes IBIS-AMI Model TX Model includes EQ (TEQ_TYPE) No Tap 2-Tap 3-Tap 4-Tap TX Model includes Amplitude Adjustment Matches to protocol TX Model: De-emphasis levels Ranges from: 0 to 2-3x RX Model: Includes Adaptive EQ May have ability to communicate with TX External Use 32
34 SerDes TX AMI Model Settings (1) (TEQ_TYPE (List )(Usage In)(Type Integer)(Default 1) (Labels "00: No TX Equalization" "01: 2 level of TX Equalization" "10: 3 levels of TX Equalization" "11: Reserved") (Description "Transmitter Equalization type selection")) (AMP_RED (List )(Usage In)(Type Integer)(Default 0) (Labels " (d32): X Full Swing" " (d0): X Full Swing" " (d1): X Full Swing" " (d3): X Full Swing" " (d2): X Full Swing" " (d6): X Full Swing" " (d7): X Full Swing" " (d16): X Full Swing" " (d17): X Full Swing" " (d19): X Full Swing" " (d18): X Full Swing" " (d22): X Full Swing" " (d23): X Full Swing" " (d31): X Full Swing") (Description "Transmitter Output Amplitude Control")) External Use 33
35 SerDes TX AMI Model Settings (2) (RATIO_PREQ (List )(Usage In)(Type Integer)(Default 0) (Labels "0000 (d0): No equalization" "0001 (d1): 1.04 X relative amplitude" "0010 (d2): 1.09 X relative amplitude" "0011 (d3): 1.14 X relative amplitude" "0100 (d4): 1.20 X relative amplitude" "0101 (d5): 1.26 X relative amplitude" "0110 (d6): 1.33 X relative amplitude" "0111 (d7): 1.40 X relative amplitude" "1000 (d8): 1.50 X relative amplitude" "1001 (d9): 1.60 X relative amplitude" "1010 (d10): 1.71 X relative amplitude" "1011 (d11): 1.84 X relative amplitude" "1100 (d12): 2.00 X relative amplitude") (Description "Transmitter Pre-Cursor Control")) (SGN_PREQ (List 0 1)(Usage In)(Type Integer)(Default 1) (Labels "0 = Negative" "1 = Positive") (Description "Transmitter Pre-Cursor Polarity")) External Use 34
36 SerDes TX AMI Model Settings (3) (RATIO_PST1Q (List )(Usage In)(Type Integer)(Default 12) (Labels " (d0): No equalization" " (d1): 1.04 X relative amplitude" " (d2): 1.09 X relative amplitude" " (d3): 1.14 X relative amplitude" " (d4): 1.20 X relative amplitude" " (d5): 1.26 X relative amplitude" " (d6): 1.33 X relative amplitude" " (d7): 1.40 X relative amplitude" " (d8): 1.50 X relative amplitude" " (d9): 1.60 X relative amplitude" " (d10): 1.71 X relative amplitude" " (d11): 1.84 X relative amplitude" " (d12): 2.00 X relative amplitude" " (d13): 2.18 X relative amplitude" " (d14): 2.40 X relative amplitude" " (d15): 2.66 X relative amplitude" " (d16): 3.00 X relative amplitude") (Description "Transmitter Post-Cursor Control")) (SGN_POST1Q (List 0 1)(Usage In)(Type Integer)(Default 1) (Labels "0 = Negative" "1 = Positive") (Description "Transmitter Post-Cursor Polarity")) External Use 35
37 TX EQ in Reference Manual External Use 36
38 TX EQ in Reference Manual External Use 37
39 SerDes 10G TX: 3-tap EQ External Use 38
40 Freescale RX IBIS-AMI Model Background External Use 39
41 Simulate to Optimize RX EQ RX EQ Simulation to provide visibility at Post RX EQ Typically where data eye recovery takes place EQ Types FFE DFE CTLE Freescale SerDes 10G is custom circuit Often Adaptive May have over-rides Freescale is adaptive (finds best values for its RX EQ parameters) Instructive to look at data eye before/after RX EQ in some cases External Use 40
42 Density Comment: 5G Post RX EQ ~65-80% UI with +/- 320 to +/- 450 mv amplitude External Use time, psec
43 IBIS-AMI Model Correlation External Use 42
44 SerDes 5G IBIS AMI Correlation 95+% Figure of Merit between SiSoft Simulation Freescale Internal SPICE simulation External Use 43
45 SerDes 26 IBIS AMI Correlation 95+% Figure of Merit between SiSoft Simulation Freescale Internal SPICE simulation External Use 44
46 TX EQ Simulations External Use 45
47 10G TX Driving 1x Etch 8G TX AMI Only Compare Voltage vs. Time De-Emphasis Plots See how de-emphasis levels change non-transition bits External Use 46
48 SerDes 10G TX IBIS-AMI: Vary TX EQ Post1Q External Use 47
49 SerDes 10G TX IBIS-AMI: Vary Post1Q Small TX EQ External Use 48
50 SerDes 10G TX IBIS-AMI: Vary Post1Q, Large TX EQ - Note smaller outer eye; larger inner eye External Use 49
51 SerDes 10G TX IBIS-AMI: Vary Post1Q External Use 50
52 SerDes TX EQ Example: TX EQ 2 Tap 1.5X (3.5dB) External Use 51
53 SerDes TX EQ Example: TX EQ 2 Tap 1.5X (3.5dB) External Use 52
54 SerDes TX EQ Example: TX EQ 2 Tap 2X (6dB) External Use 53
55 SerDes TX EQ Example: TX EQ 2 Tap 2X (6dB) External Use 54
56 SerDes TX EQ Example: Compare Contours External Use 55
57 Big Improvement: Add RX EQ External Use 56
58 RX EQ Simulations External Use 57
59 Alter 5G Single Bit; Can See Some Change in Single Bits External Use 58
60 Compare Eyes for RXEQ 5G: Top 0,0; Bottom 15,0 External Use 59
61 Alter 10G Single Bit; Some Cases Don t Work External Use 60
62 Compare Eyes for RXEQ 10G: Top 8,0; Bottom 15,0 External Use 61
63 Alter RXEQ: Waveform Shifts External Use 62
64 Alter RXEQ External Use 63
65 RX EQ Parameters: Watch Them Adapt to Find Settings External Use 64
66 RXEQ Settings: Helps in Some Cases - Off for top - On for middle - On vs. off for contour plot at bottom External Use 65
67 Comments on TX and RX EQ Parameters TX EQ Amplitude and De-emphasis map into typical usage Slower speeds, without RX EQ, then TX EQ helps RX EQ: Adaptive Design is very useful Very thankful we have that Runs automatically in silicon Not needing to set RXEQ values External Use 66
68 How to Categorize a Channel External Use 67
69 PCB Trace Losses PCB Interconnect losses due to traces can be seen in S parameter data. Insertion Loss (S12, S21) The PCB dielectric materials and traces have losses that increase with the frequency of the signal. As the SerDes bus speeds increase, the PCB losses become a larger factor in signal degradation Return Loss (S11, S22) Signal losses are also caused by mismatches in impedance. Impedance mismatches occur in packages, PCB traces, vias, connectors, and sockets External Use 68
70 IEEE Spec Document: 10GBase-KR External Use 69
71 Channel Analysis and Printed Circuit Board Considerations External Use 70
72 SerDes Channel: Device to Device, Same Board Device to Device: BGA Breakout BGA Vias: Stubs, Micro Vias PCB Trace BGA Breakout and Vias External Use 71
73 SerDes Channel: Board to Board Board to Board: BGA Breakout BGA Vias: Stubs, Micro Vias PCB Trace Connector Vias: Stubs Daughtercard Traces and Vias External Use 72
74 SerDes Channel: Board to Board with Cable Board to Board, to Cable, Board to Board: BGA Breakout BGA Vias: Stubs, Micro Vias PCB Trace Connector Vias: Stubs Daughtercard Traces and Vias Cable Motherboard Daughtercard Path a second time External Use 73
75 Design Considerations BGA Breakout How many lanes? How many layers available? Pad size Via design PCB Stackup Trace width Material: Lost Tangent, Dissipation Factor Dielectric Constant Impedance PCB Routing Trace Length Trace Separation (Crosstalk) Connector Impedance Crosstalk External Use 74
76 PCB Cross Section/Materials External Use 75
77 PCB Trace Material At higher speeds, have to consider surface roughness and plating Surface Roughness Profiles Electrodeposited Reverse Treated Low Profile Rolled Plating Nickel Silver Soldermask External Use 76
78 Foil Type and Surface Roughness (Rogers) External Use 77
79 BGA Breakout Breakout on which layer? Top Layer Bottom Layer Internal Layers Stripline with short via stub Stripline with micro via or back drilled via Trace Width Management Neckdowns? Dog Bones? External Use 78
80 BGA Breakout Note Dog Bone Break Out Note Via Stub External Use 79
81 AC Capacitor Pad AC Capacitor Pads (or any pad) Consider cutting out plane under pad Shown here are AC cap pads on PCB Pads are cut out to match pad width Also, Connector Pads are cut out External Use 80
82 PCB Vias PCB Vias (diff pair) generally will be < 100 ohms Consider creating larger antipad for planes in the stackup to reduce capacitance and raise impedance Diff pair Vias from board with antipad cutouts shown External Use 81
83 Other Forms of Impedance Discontinuities: Mid Bus Probe, Test Points Test Point at Right 20 mils: would be 24 ohms (SE) Mid Bus Probe ohm discontinuity External Use 82
84 Other Forms of Insertion Loss: Cables and MUX s Multiplexer Devices Considerable loss for > 5 Gbps operation 8 db loss at 5 GHz Large (-40 db) loss at GHz Cable Considerable Loss 1-2 db loss at 5 GHz 6-8 db loss at 15 GHz External Use 83
85 Measured TDR (Top) vs. First Pass Simulated TDR (Bottom) BGA, 24 mil pad, 36 ohm Dog bone Mid Bus Via Stub AC Caps and Vias PCIe Connector Pads External Use 84
86 PCB Losses: Conductor External Use 85
87 PCB Routing: Trace Width Trace Width affects the loss of the SerDes channel Narrower traces produce more loss due to skin effect Increases at Square Root of Frequency Frequency Dependent Skin Effect Loss a o f / t w t w = trace width (worse with narrow traces) External Use 86
88 PCB Trace Width Examples PCB Trace Widths to be examined: 4 mils 6 mils 8 mils 10 mils 12 mils Data eyes for narrower trace widths have a smaller amplitude and smaller UI due to conductor loss External Use 87
89 Example Channel: Simulated at 5Gbps without EQ PCB Trace: - 20 inches - Dielectric Constant: Loss Tangent: Vary Trace Width: - 4, 6, 8, 10, 12 mils External Use 88
90 PCB Trace Width Examples: Insertion Loss - Up to a 3.2 db change due to trace width External Use 89
91 Attenuation: Blue (total), Red (conductor), Green (dielectric) 4 mil 6 mil 8 mil 10 mil External Use 90
92 PCB Trace Width Results: 4 Mils External Use 91
93 PCB Trace Width Results: 8 Mils External Use 92
94 PCB Trace Width Results No EQ: Compare External Use 93
95 PCB Trace Width Results No EQ: Compare Contour Plots Trace Width (mils) Eye Ht (mv) Eye Width (ps) External Use 94
96 PCB Losses: Dielectric External Use 95
97 PCB Routing: PCB Material PCB Dielectric Material includes a loss tangent value Higher loss tangent values produce greater loss in the SerDes Channel Increases Proportionally to Frequency Frequency Dependent Dielectric Loss a = 2.3 (f ) tan(q) e r tan(q) = loss tangent, (better with low loss tangent) External Use 96
98 Example Channel: Simulated at 5Gpbs No EQ PCB Trace: - 20 inches - Trace Width: 6 mils - Vary PCB Materials - Dielectric Constant and Loss Tangent and and and and External Use 97
99 PCB Material Examples Common PCB materials to be examined: Dielectric Constant (Er, Dk) = 4.2, Loss Tangent/Dissipation Factor (Df) = 0.02 Dielectric Constant (Er, Dk) = 3.7, Loss Tangent/Dissipation Factor (Df) = Dielectric Constant (Er, Dk) = 3.5, Loss Tangent/Dissipation Factor (Df) = Dielectric Constant (Er, Dk) = 3.0, Loss Tangent/Dissipation Factor (Df) = Data eyes for higher loss tangent dielectrics generally have a smaller amplitude and smaller UI due to dielectric loss External Use 98
100 PCB Materials Results: Compare External Use 99
101 PCB Materials Results: Compare 1e-12 Contour Plot Material Eye Ht (mv) Eye Width (ps) Er 4.2, Er 3.7, Er 3.5, Er 3.0, External Use 100
102 Summary Data on PCB Trace Width and Materials (1) Trace width: Use wider traces (+) Improves skin-effect loss (+) No increase in material cost (-) Uses more routing area (-) Increases PCB thickness to maintain impedance targets Use of wider traces on internal layers may be limited due to board thickness requirements External Use 101
103 Summary Data on PCB Trace Width and Materials (2) PCB materials: Use high-speed FR4 (+) Lower loss tangent lowers dielectric loss Loss tangent can be cut in half with modified FR4 materials Some boards using FR408HR, Megtron6 Other boards using Rogers RO3003, Megtron6, Rogers RO4350 Use smooth copper (+) Lower conductor loss (-) Caution! Peel strength is reduced External Use 102
104 Conductor Loss vs. Dielectric Loss External Use 103
105 Conductor Loss vs. Dielectric Loss Plots from 2D models of PCB loss over frequency help to show conductor vs. dielectric loss for different PCB materials Examine FR4, FR408HR, Rogers 4350, Rogers 3003 External Use 104
106 Conductor Loss (red), Dielectric Loss (green), Total Loss (blue) (All plots for conductor loss are for 1 inch diff pair) FR4 FR408HR R4350 R3003 External Use 105
107 Conductor Loss FR4 External Use 106
108 Conductor Loss FR408HR External Use 107
109 Conductor Loss Rogers 4350 External Use 108
110 Conductor Loss Rogers 3003 External Use 109
111 Conductor Loss Rogers 3003 (10 mil) with Wider Trace External Use 110
112 Conductor Loss Rogers 3003 (5 mil) to 100 GHz 1 db total loss at ~57 GHz; FR4 1 db total loss at ~10 GHz External Use 111
113 S21 vs. SDD21 Data External Use 112
114 SDD21 vs. S21 Data Consider external layer routing (Microstrip configuration) Simulations and measurements show that the amount of singleended insertion loss (S21) is more than the amount of the differential insertion loss (SDD21) at the Nyquist Frequency of the 10Gbps signals A March 2013 blog by Eric Bogatin discusses this exact item One conclusion it brings forth is that a tightly coupled microstrip differential pair should not be judged by its single-ended insertion loss alone. Differential insertion loss may look good when the single-ended insertion loss is questionable Key item is to track the deliberate far-end crosstalk (FEXT) in a microstrip diff pair External Use 113
115 Measured Test Trace: SDD21 (in Green) External Use 114
116 From Eric Bogatin Blog March 26, 2013: S21 External Use 115
117 From Eric Bogatin Blog March 26, 2013: SDD21 External Use 116
118 PCB Only SDD21 (Yellow) vs. S21 (Purple) and S41 (Red) S41 FEXT rises S21 insertion loss dips External Use 117
119 Package SDD21 (Yellow) vs S21 (Purple) and S41 (Red) S21 insertion loss dips S21 insertion loss dips S41 FEXT rises S41 FEXT rises External Use 118
120 Connector SDD21 (Yellow) vs. S21 (Purple) and S41 (Red) S21 insertion loss dips S21 insertion loss dips S21 insertion loss dips S41 FEXT rises S41 FEXT rises S41 FEXT rises External Use 119
121 Test Traces with Cables and Connectors: S21 (Red) vs. SDD21 (Yellow) simulated to 20 GHz External Use 120
122 Compare Tightly/Loosely Coupled Diff Pairs SDD21 (Yellow), S21 (Purple), S41 (Red) Trace Separation=0.5 *Trace Width Trace Separation= 1.0 * Trace Width Trace Separation=2.0 *Trace Width Trace Separation= 5.0 * Trace Width External Use 121
123 Tightly Coupled (Sep=0.5*TW) SDD21, S21, S41: Large difference in insertion loss at 5GHz (purple vs. yellow) ( Sep is Trace Separation; TW is Trace Width) 5 GHz External Use 122
124 Tightly Coupled (Sep=TW) SDD21, S21, S41 5 GHz External Use 123
125 Tightly-Loosely Coupled (Sep=2*TW) SDD21, S21, S41 5 GHz External Use 124
126 Loosely Coupled (Sep=3*TW) SDD21, S21, S41 5 GHz External Use 125
127 Loosely Coupled (Sep=5*TW) SDD21, S21, S41: Note small difference in insertion loss at 5GHz 5 GHz External Use 126
128 Uncoupled (Sep=10*TW) SDD21, S21, S41 SDD21 is overlaid with S21 5 GHz External Use 127
129 Internal Stripline Tightly Coupled (Sep=0.8*TW) SDD21, S21, S41 SDD21 is overlaid with S21 (No/Little FEXT) External Use 128
130 Measured S21 vs. SDD21 test trace with vias S21 test trace with vias SDD21 External Use 129
131 Tightly/Loosely Coupled Diff Pairs: Return Loss SDD22 (Yellow), SD22 (Purple): Similar for loosely coupled Trace Separation=0.5 *Trace Width Trace Separation= 1.0 * Trace Width Trace Separation=2.0 *Trace Width Trace Separation= 5.0 * Trace Width External Use 130
132 Channel Simulations with AMI Models External Use 131
133 Multi-Board 8G: No TX EQ, No RX EQ Closed External Use 132
134 Multi-Board 8G: TX EQ, No RX EQ Almost Open External Use 133
135 Multi-Board 8G: TX No EQ, RX EQ Open External Use 134
136 Multi-Board 8G: TX EQ, RX EQ Open External Use 135
137 Compare Multi-Board Schemes 8G External Use 136
138 Sweep TX to Find Better Eye? External Use 137
139 10G TX Driving 1x Etch 8G Insertion Loss External Use 138
140 10G TX Driving 1x Etch 8G TX AMI Only: Compare Voltage vs. Time De-Emphasis Plots See how de-emphasis levels change non-transition bits External Use 139
141 10G TX Driving 1x Etch 8G TX AMI Only; 1.0x No TX EQ, Note Full Swing External Use 140
142 10G TX Driving 1x Etch 8G TX AMI Only; 1.2x min TX EQ; Note Smaller Swing and More Open Eye External Use 141
143 10G TX Driving 1x Etch 8G TX AMI Only; 1.5x Moderate TX EQ; Swing Smaller; Eye More Open External Use 142
144 10G TX Driving 1x Etch 8G TX AMI Only; 2.0x Strong TX EQ; Swing Smaller; Eye Open; Too Much TX EQ? External Use 143
145 10G TX Driving 1x Etch 8G TX AMI Only; 3.0x Max TX EQ; Swing Smaller; Eye Open; Too Much TX EQ External Use 144
146 10G TX Driving 1x Etch 8G TX AMI Only: Compare Contour Plots 2.0x, 1.5x, 1.2x Produce Biggest Eyes External Use 145
147 10G TX Driving 1x Etch 8G TX AMI and RX AMI; 1.0x No TX EQ with RX EQ; Eye Open External Use 146
148 10G TX Driving 1x Etch 8G TX AMI and RX AMI; 1.2x Min TX EQ with RX EQ; Eye Open Less than 1.0x External Use 147
149 10G TX Driving 1x Etch 8G TX AMI and RX AMI; 1.5x Moderate TX EQ with RX EQ; Eye Open Less than 1.2x External Use 148
150 10G TX Driving 1x Etch 8G TX AMI and RX AMI; 2.0x Strong TX EQ with RX EQ; Eye Open Less than 1.5x External Use 149
151 10G TX Driving 1x Etch 8G TX AMI and RX AMI; 3.0x Max TX EQ with RX EQ; Eye Open Less than 2.0x External Use 150
152 10G TX Driving 1x Etch 8G TX AMI and RX AMI: Compare Contour Plots: Best Settings Are Less TX EQ External Use 151
153 1x Etch: Summary of Eye Height and Eye Width from TX EQ Sweep For this Channel, RX EQ Works Best with Minimum to No TX EQ TX EQ RX AMI Eye Height (V) Eye Width (ps) 0 No x No x No x No x No Yes x Yes x Yes x Yes x Yes External Use 152
154 10G TX Driving 3x Etch 8G Insertion Loss (Compared to Prior Channel Insertion Loss ~3x More Loss) External Use 153
155 10G TX Driving 3x Etch 8G Pulse, Step Response (25%) External Use 154
156 10G TX Driving 3x Etch 8G TX AMI Only; 1.0x External Use 155
157 10G TX Driving 3x Etch 8G TX AMI Only; 1.2x External Use 156
158 10G TX Driving 3x Etch 8G TX AMI Only; 1.5x External Use 157
159 10G TX Driving 3x Etch 8G TX AMI Only; 2.0x External Use 158
160 10G TX Driving 3x Etch 8G TX AMI Only; 3.0x - Almost opens the eye; notice how amplitude shrinks with stronger TX EQ External Use 159
161 10G TX Driving 3x Etch 8G TX AMI Only: Compare Contour Plots: Only TX EQ 3.0x Gives a Small Open Contour External Use 160
162 10G TX Driving 3x Etch 8G TX AMI Only: Voltage vs. Time Plots 1.0x See Blue Waveform Not Driving through 0V Consistently External Use 161
163 10G TX Driving 3x Etch 8G TX AMI Only: Voltage vs Time Plots 1.5x See Blue Waveform Not Driving through 0V Consistently Either External Use 162
164 10G TX Driving 3x Etch 8G TX AMI Only: Voltage vs. Time Plots 3.0x See Blue Waveform Barely Drives through 0V Consistently Also Note that RX Signal Swing is Less Due to TX De-emphasis External Use 163
165 10G TX Driving 3x Etch 8G TX AMI and RX AMI; 1.0x No TX EQ; RX EQ Opens Eye External Use 164
166 10G TX Driving 3x Etch 8G TX AMI and RX AMI; 1.2x Min TX EQ; RX EQ Opens Eye External Use 165
167 10G TX Driving 3x Etch 8G TX AMI and RX AMI; 1.5x Moderate TX EQ; RX EQ Opens Eye Better with this Setting External Use 166
168 10G TX Driving 3x Etch 8G TX AMI and RX AMI; 2.0x Strong TX EQ; RX EQ Opens Eye External Use 167
169 10G TX Driving 3x Etch 8G TX AMI and RX AMI; 3.0x Max TX EQ; RX EQ Opens Eye External Use 168
170 10G TX Driving 3x Etch 8G TX AMI and RX AMI: Compare Contour Plots: 1.5x, 1.2x, 3.0x are Best Settings for TX EQ External Use 169
171 3x Etch: Summary of Eye Height and Eye Width from TX EQ Sweep TX EQ RX AMI Eye Height (V) Eye Width (ps) 0 No x No x No x No x No Yes x Yes x Yes x Yes x Yes External Use 170
172 Summary of IBIS-AMI Benefits TX EQ modeling 2 tap, 3 tap, 4 tap TX EQ RX EQ modeling Multiple types of RX EQ Proprietary Circuits can be modeled AMI Model can be tailored specifically for a device s design IBIS-AMI based simulation tools permit effective sweeping of TX and RX parameters to determine optimal settings EDA tools are building in GUI-based means to sweep parameters easily Good for tool usage that is not running models adaptively TX EQ and RX EQ can be significant tools for improving SerDes channel response May permit design using lower cost materials and narrower traces Translates to << $$ and << board space External Use 171
173 Questions and Answers Thanks! External Use 172
174 References Ambiguous Influences Affecting Insertion Loss of Microwave Printed Circuit Boards, Rogers Corp. Eric Bogatin Blog March 26, External Use 173
175 Introducing The QorIQ LS2 Family Breakthrough, software-defined approach to advance the world s new virtualized networks New, high-performance architecture built with ease-of-use in mind Groundbreaking, flexible architecture that abstracts hardware complexity and enables customers to focus their resources on innovation at the application level Optimized for software-defined networking applications Balanced integration of CPU performance with network I/O and C-programmable datapath acceleration that is right-sized (power/performance/cost) to deliver advanced SoC technology for the SDN era Extending the industry s broadest portfolio of 64-bit multicore SoCs Built on the ARM Cortex -A57 architecture with integrated L2 switch enabling interconnect and peripherals to provide a complete system-on-chip solution External Use 174
176 QorIQ LS2 Family Key Features SDN/NFV Switching Data Center Wireless Access Unprecedented performance and ease of use for smarter, more capable networks High performance cores with leading interconnect and memory bandwidth 8x ARM Cortex-A57 cores, 2.0GHz, 4MB L2 cache, w Neon SIMD 1MB L3 platform cache w/ecc 2x 64b DDR4 up to 2.4GT/s A high performance datapath designed with software developers in mind New datapath hardware and abstracted acceleration that is called via standard Linux objects 40 Gbps Packet processing performance with 20Gbps acceleration (crypto, Pattern Match/RegEx, Data Compression) Management complex provides all init/setup/teardown tasks Leading network I/O integration 8x1/10GbE + 8x1G, MACSec on up to 4x 1/10GbE Integrated L2 switching capability for cost savings 4 PCIe Gen3 controllers, 1 with SR-IOV support 2 x SATA 3.0, 2 x USB 3.0 with PHY External Use 175
177 See the LS2 Family First in the Tech Lab! 4 new demos built on QorIQ LS2 processors: Performance Analysis Made Easy Leave the Packet Processing To Us Combining Ease of Use with Performance Tools for Every Step of Your Design External Use 176
178 Freescale Semiconductor, Inc. External Use
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