GENLINX II GS9032 Digital Video Serializer

Transcription

1 GENLINX II G932 Digital Video erializer PRELIMINARY DATA HEET FEATURE fully compliant with MPTE 259M serializes 8-bit or 1-bit data beyond 54 Mb/s autostandard, adjustment free operation minimal external components (no loop filter components required) isolated, quad output, adjustable cable driver power saving secondary cable driver disable 3.3 V and 5 V CMO/TTL compatible inputs lock detect indication MPTE scramble and NRZI coding bypass option 44 pin TQFP package EDH support with G91, G921 or EDH FPGA code APPLICATION MPTE 259M and 54 Mb/s parallel to serial interfaces for video cameras, VTRs, signal generators Generic parallel to serial conversion DECRIPTION The G932 is designed to encode and serialize MPTE 125M and 244M bit parallel digital video signals as well as other 8 bit or 1 bit parallel formats. This device performs the functions of sync detection, parallel to serial conversion, data scrambling (using the X 9 +X 4 +1 algorithm), 1x parallel clock multiplication and conversion of NRZ to NRZI serial data. The G932 features auto standard and adjustment free operation for data rates to 54 Mb/s with a single VCO resistor. Other features include a lock detect output, NRZI encoding and MPTE scrambler bypass and a sync detect disable. The G932 also features an isolated quad output cable driver suitable for driving 75 Ω loads. The complimentary cable driving output swings can be adjusted independently or the secondary differential cable driver can be powered down. The device requires a single +5 volt or -5 volt supply and typically consumes 72 mw of power while driving four 75 Ω loads. ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE G932-CVM 44 TQFP C to 7 C G932-CTM 44 TQFP Tape C to 7 C YNC DETECT DIABLE (YNC DI) BYPA 1 DATA IN (PD-PD9) INPUT LATCH 1 YNC DETECT 8 2 MPTE CRAMBLER 1 BYPA PARALLEL to ERIAL CONVERTER & NRZ to NRZI ERIAL DIGITAL OUTPUT CLK /1 CLK P LOAD PARALLEL CLOCK INPUT (PCLKIN) AUTO/MANUAL ELECT (AUTO/MAN) LOOP BANDWIDTH CONTROL (LBWC) DATA RATE ELECT [2:] 3 PLL MUTE DO1 ENABLE LOCK DETECT (LOCK DET) G932 R VCO + RVCO - FUNCTIONAL BLOCK DIAGRAM Document No GENNUM CORPORATION P.O. Box 489, tn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (95) fax. +1 (95) Web ite: info@gennum.com

2 ABOLUTE MAXIMUM RATING PIN CONNECTION PARAMETER upply Voltage (V = - ) Input Voltage Range (any input) VALUE/UNIT 5.5 V <V IN < YNC DI LF- LF+ LBWC R VCO - C BG R VCO DC Input Current (any one input) 5 ma Power Dissipation ( =5.25V) 12 mw Maximum Die Temperature 125 C PD9 PD AUTO/MAN Operating Temperature Range C T A 7 C PD BYPA torage Temperature Range -65 C T 15 C PD6 4 3 RET1 Lead Temperature (soldering, 1 seconds) 26 C PD5 PD4 PD3 PD G TQFP DO1 DO1 PD DO PD 1 24 DO PCLKIN C OC DO1 ENABLE LOCK DET O RET G932 DC ELECTRICAL CHARACTERITIC = 5. V, = V, T A = C to 7 C unless otherwise specified. PARAMETER YMBOL CONDITION MIN TYP MAX UNIT NOTE TET LEVEL Positive upply Voltage Operating Range V 3 Power (ystem Power) P =5.V, T=25 C (4 Outputs) mw upply Current I =5.25V, T=7 C (4 Outputs) ma - I =5.V, T=25 C (4 Outputs) ma 1 I =5.25V, T=7 C (2 Outputs) ma - I =5.V, T=25 C (2 Outputs) ma 1 Data & Clock Inputs t su etup Time ns 1 t H Hold Time ns 1 t r,t f Rise/FallTime - - ps 4 Logic Input Levels V IH Logic Input High (wrt to ) V 1 (Auto/Man, [2:] Bypass, ) V IL Logic Input Low (wrt to ) V 1 I L Input Current µa 1 Lock Detect Output V OL inking µa V

3 G932 AC ELECTRICAL CHARACTERITIC = 5.V, = V T A = C to 7 C unless otherwise specified. PARAMETER YMBOL CONDITION MIN TYP MAX UNIT NOTE TET LEVEL erial Data Bit Rate BR DO Mb/s MPTE 259M Mb/s Mb/s 4 Data Outputs V DO ignal wing, (R LOAD =37.5Ω) mvp-p 1 V DOMIN Min wing (adjusted), (R LOAD =75Ω) mvp-p 2 V DOMAX Max wing (adjusted), (R LOAD =37.5Ω) mvp-p 2 t r,t f Rise/Fall Times, 2-8% 4-7 ps 4 Overshoot / Undershoot % 4 O RL Output Return Loss at 54MHz db 4 Lock Time t LOCK Worst case ms 2 Min Loop Bandwidth BW MIN.1dB Peaking, khz 27Mb/s LBWC Grounded 1 BW MIN Typ Loop Bandwidth BW TYP.1dB Peaking, MHz 27Mb/s LBWC Floating 1 BW MIN Max Loop Bandwidth BW MAX.1dB Peaking, MHz 27Mb/s LBWC to Jitter 143 Mb/s UIp-p 1 6 σ Intrinsic Jitter 177 Mb/s UIp-p 1 27 Mb/s Max LB (LBWC Grounded) UIp-p 1 36 Mb/s UIp-p 1 54 Mb/s UIp-p 1 Test Levels: 1. 1% tested at 25 C 3. Correlated or inferred value 2. Guaranteed by design 4. Measured with Gennum Evaluation Board (EB932)

4 PIN DECRIPTION PIN NO. YMBOL TYPE DECRIPTION 1-1 PD9-PD I CMO or TTL compatible parallel data inputs. PD is the LB and PD9 is the MB. 11 PCLKIN I CMO or TTL compatible parallel clock input. 14 C OC I Master Timer Capacity. A capacitor should be added to decrease the system clock frequency when an external capacitor is used across LF+ and LF-. (NC if not used). 15, 16, 21 2, 1, I Data rate selection when in manual mode. These pins are not used in auto mode. 2 LOCK DET O TTL level which is high when the internal PLL is locked. 31 BYPA I When high, the MPTE crambler and NRZ encoder are bypassed. 22 RET I External resistor used to set the data output amplitude for DO and DO. 24, 25 DO, DO O Primary, current mode, 75Ω cable driving output (true and inverse). 27, 28 DO1, DO1 O econdary, current mode, 75Ω cable driving output (true and inverse) 3 RET1 I External resistor used to set the data output amplitude for DO1 and DO1. 19 DO1 ENABLE I Enable pin for the secondary cable driver (DO1 and DO1). Connect to most negative power supply to enable. 32 AUTO/MAN I Autostandard or manual mode selectable operation. 33 I Resets the scrambler when asserted. 36, 38 R VCO +,R VCO - I Differential VCO current setting resistor that sets the VCO frequency. 37 C BG I VCO bandgap capacitor for noise filtering in noisy applications to improve jitter (NC if not used). 4 LBWC I TTL level loop bandwidth control that adjusts the PLL bandwidth to optimize for lowest jitter. If the pin is set to ground the loop bandwidth is BW MIN. If the pin is left floating, the loop bandwidth is 1 BW MIN, if the pin is tied to the loop bandwidth is 1BW MIN. 41, 42 LF- I Differential loop filter pins to optimize loop transfer performance at low loop bandwidths. LF+ (NC if not used) 44 YNC DI I ync detect disable. Logic high disables sync detection. Logic low allows 8 bit operation by mapping -3 to and 3FC-3FF to 3FF I Most positive power supply connection for parallel data and clock inputs I Most negative power supply connection for parallel data and clock inputs I Most positive power supply connection for internal logic and digital circuits I Most negative power supply connection for internal logic and digital circuits. 23, 26, 29, I Most negative power supply connection for shielding (not connected). 39, 43 I Most negative power supply connection (substrate) I Most positive power supply connection for analog circuits I Most negative power supply connection for analog circuits

5 G932 Digital Video erializer - Detailed Device Description The G932 erializer is a bipolar integrated circuit used to convert parallel data into a serial format according to the MPTE 259M standard. The device encodes both eight and ten bit TTL-compatible parallel signals producing serial data rates up to Mb/s. I operates from a single five volt supply and is packaged in a 28 pin PLCC. Functional blocks within the device include the input latches, sync detector, parallel to serial converter, MPTE scrambler, NRZ to NRZI converter, internal cable driver, PLL for 1 x parallel clock multiplication and lock detect. The parallel data (PD-PD9) and parallel clock (PCLKIN) are applied via pins 3 through 13 respectively. ync Detector The ync Detector looks for the reserved words -3 and 3FC-3FF, in ten bit hexadecimal, or and FF in eight bit hexadecimal, used in the TR-ID sync word. When the occurrence of either all zeros or all ones at inputs PD2-PD9 is detected, the lower two bits PD and PD1 are forced to zeros or ones, respectively. This makes the system compatible with eight or ten bit data. For non - MPTE standard parallel data, a logic input, ync Detect Disable (25) is available to disable this feature. crambler The crambler is a linear feedback shift register used to pseudo-randomize the incoming serial data according to the fixed polynomial (X 9 +X 4 +1). This minimizes the DC component in the output serial data stream. The NRZ to NRZI converter uses another polynomial (X+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. These functions can be disabled by setting the BYPA pin (31) high. Phase Locked Loop The PLL performs parallel clock multiplication and provides the timing signal for the serializer. It is composed of a phase/frequency detector (with no dead zone), charge pump, VCO, a divide-by-ten counter, and a divide by two counter. The phase/frequency detector allows a wider capture range and faster lock time than that can be achieved with a phase discriminator alone. The discrimination of frequency also eliminates harmonic locking. With this type of discriminator, the PLL can be over-damped for good stability without sacrificing lock time. The charge pump delivers a 'charge packet' to the loop filter which is proportional to the system phase error. Internal voltage clamps are used to constrain the loop filter voltage between approximately 1.8 and 3.4 volts. The VCO is a differential low phase noise, factory trimmed design that provides increased immunity to PBC noise and precise control of the VCO center frequency. The VCO can operate in excess of 8 MHz and has a pull range of ±15% about the center frequency. The single external resistor, RVCO, sets the VCO frequency (see Figure 1). VCO Centre Frequency election For a given RVCO value, the VCO can oscillate at one of two frequencies. When = logic 1, the VCO center frequency corresponds to the ƒ L curve. For =logic, the VCO center frequency corresponds to the ƒh curve (ƒ H is approximately 1.5 x ƒ L). VCO Frequency (MHz) f L f H O=1 O= RVCO (Ω) Fig. 1 The recommended RVCO value for auto rate MPTE 259M applications is 374 Ω (R13 in Figure 14). The VCO and an internal divider generate the PLL clock. Divider moduli of 1, 2, and 4 allow the PLL to lock to data rates from 143 Mb/s to 54 Mb/s. The divider modulus is set by the AUTO/MAN, and [2:] pins (see Truth Table section for further details). In addition, a manually selectable modulus 8 divider allows operation at data rates as low as 18 Mb/s when RVCO is increased to 1 ohms. The lock detect circuit mutes the serial data outputs when the loop is not locked. The Lock Detect output is available from pin 2 and is HIGH when the loop is locked. The true and complement serial data, DO and DO are available from pins 24 and 25 and pins 27 and 28. These outputs will drive four 75Ω co-axial cables with MPTE level serial digital video signals. The outputs from pins 27 and 28 (DO1, DO1) can be disabled by removing the resistor connected to the RET1 pin (3) and by floating the DO1 ENABLE pin (19)

6 TYPICAL PERFORMANCE CURVE (V = 5V, T A = 25 C unless otherwise shown). (Guard band tested to 7 C only) RIE / FALL TIME (ps) Rise 4.75 Fall 4.75 Rise 5. Rise 5.25 Fall 5. Fall CURRENT (ma) Fig. 2 Rise / Fall Times vs Temperature Fig. 3 upply Current vs Temperature (DO & DO1 ON) OUTPUT WING (V) OUTPUT WING (V) Fig. 4a Output wing vs Temperature (1mV) Fig. 4b Output wing vs Temperature (8mV) t CLKL = t CLKH 4ƒ sc DATA TREAM T R ACTIVE VIDEO & H BLANKING T R ACTIVE VIDEO & H BLANKING T R YNC DETECT PARALLEL CLOCK PLCK PARALLEL DATA PDn 5% 4:2:2 DATA TREAM YNC DETECT E A V H BLNK A V ACTIVE VIDEO E A V H BLNK A V t U t HOLD Fig. 5 Waveforms PCLK IN PDN YNC DETECT XXX 3FF XXX XXX 3FF XXX Fig. 6 Timing Diagram

7 TYPICAL PERFORMANCE CURVE (V = 5V, T A = 25 C unless otherwise shown). (Guard band tested to 7 C only) LF+ LF- (mv) LF+ LF- (mv) Fig. 7a Loop Filter Voltage vs Temperature (36 Mode) Fig. 7b Loop Filter Voltage vs Temperature (54 Mode) LOOP BANDWIDTH (khz) LBWC to VCC LBWC FLOATING LBWC GROUNDED JITTER p-p (ps) For a Data Rate of 27Mb/s GROUNDED FLOATING VCC DATA RATE (Mb/s) LOOP BANDWIDTH CONTROL (LBWC) Fig. 8 Loop Bandwidth vs Data Rate Fig. 9 Output Jitter vs LBWC JITTER p-p (ps) DATA RATE (Mb/s) Fig. 1 Output Jitter vs Data Rate (Optimum LBW etting) Fig. 11 Output Eye diagram (27 Mb/s)

8 TYPICAL PERFORMANCE CURVE (V = 5V, T A = 25 C unless otherwise shown) Fig. 12 Output Eye Diagram (54 Mb/s) Fig. 13 Output Eye Diagram (622 Mb/s) VCC J1 YNC DI LBWC R C6 1n PD_IN PCLKIN * ee Truth Table for settings PD9 2 PD8 A/M PD7 BYPA_EN 4 3 PD6 U1 AMP PD5 G PD4 DO1 7 PD3 8 PD2 9 PD1 1 PD 11 PCLK DO1 DO DO YNC_DI LF+ LF- LBWC Rvco NC (Cbg) Rvco+ VCC 3 VCC3 NC (Cosc) 2 1 VCC2 2 DO1_EN LOCK AMP C8 1n 2* 1* C7 1n R1 4 * R15 1k R A/M BYPA_EN R R17 75 C1 1n R16 22 LOCK R18 75 R1 75 R11 75 C5 1n L1 C12 R22 1µ L3 C13 R23 1µ L2 C14 R24 1µ L4 C15 R25 1µ L1 - L4 = 8.2 NH R22 - R25 = 75Ω J4 J4 J4 J4 Fig. 14 Application Circuit TRUTH TABLE DATA RATE 2 1 DIVIDER VCO (Mb/s) MODULI FREQUENCY ƒ H ƒ L ƒ H ƒ L ƒ H ƒ L ƒ H

9 PACKAGE DIMENION PIN TYP 12 TYP.8 MIN. RADIU.2 MIN.2 MIN MIN.6 ±.15.2 MAX RADIU 7 MAX MIN pin TQFP Dimensions in millimetres CAUTION ELECTROTATIC ENITIVE DEVICE DO NOT OPEN PACKAGE OR HANDLE EXCEPT AT A TATIC-FREE WORKTATION DOCUMENT IDENTIFICATION: PRELIMINARY DATA HEET The product is in a preproduction phase and specifications are subject to change without notice. GENNUM CORPORATION MAILING ADDRE: P.O. Box 489, tn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (95) Fax +1 (95) HIPPING ADDRE: 97 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 REVIION NOTE: GENNUM JAPAN CORPORATION C-11, Miyamae Village, Miyamae, uginami-ku, Tokyo , Japan Tel. +81 (3) Fax: +81 (3) GENNUM UK LIMITED Centaur House, Ancells Business Park, Ancells Road, Fleet, Hampshire, UK GU13 8UJ Tel. +44 (1252) Fax +44 (1252) Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. Copyright May 1998 Gennum Corporation. All rights reserved. Printed in Canada