SCG4540 Synchronous Clock Generators

Transcription

1 SCG4540 Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois Phone: Fax: Features Phase Locked Output Frequency Control Intrinsically Low Jitter Crystal Oscillator LVPECL Outputs with Disable Function Dual 10 khz Input References LOR & LOL combined alarm output Force Free Run Function Automatic Free Run operation on loss of both References A & B Input Duty Cycle Tolerant 3.3V dc Power Supply Bulletin SG053 Page 1 of 16 Revision P01 Date 5 AUG 02 Issued By MBatts Small Size: 1 Square Inch

2 General Description The SCG4540 is a mixed-signal phase locked loop generating LVPECL outputs from an intrinsically low jitter, voltage controlled, crystal oscillator. The LVPECL outputs may be disabled. The SCG4540 can lock to one of two 10 khz, external references, which is selectable using the SEL AB input select pin. The unit has a fast acquisition time of about 1 second and it is tolerant of different reference duty cycles. The SCG4540 includes an alarm output that indicates deviations from normal operation. If a Lossof-Reference (LOR) or Loss-of-Lock (LOL) is detected the alarm with indicate the need for a reference rearrangement. If both references A and B are absent the module will enter Free Run operation. The FR status pin will indicate that the module is in Free Run operation. Frequency stability during Free Run operation is guaranteed to ±20 ppm. Additionally the Free Run mode may be entered manually. The package dimensions are 1 x x.45 on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloys, 180 C surface mount reflow processes. Maximum Dimension Package Outline Figure 1 Block Diagram Figure 2 FORCE FREE RUN FREE RUN STATUS ALARM REFA REFB PHASE ALIGNER DPFD ANALOG FILTER LOW JITTER VCXO Q QN SEL AB 1 / N ENABLE/ TRI-STATE OPTIONAL REFERENCE OUTPUT Table 1 Model Comparison Table Dual Max LVPECL Model Input Duty Oscillator Output Notes Ref Freq Cycle (Pins 16 & 18) SCG khz/8 khz 40/ MHz, MHz,125 MHz Basic Model SCG MHz/1.544 MHz 40/ MHz SCG MHz/19.44 MHz 40/ MHz, MHz SCG khz/10 khz 40/ MHz *Features which differentiate a model from the base model (SCG4500) are highlighted in boldface color and in the notes column. Preliminary Data Sheet #: SG053 Page 2 of 16 Rev: P01 Date: 08/05/02

3 Table 2 Absolute Maximum Rating Symbol Parameter Minimum Nominal Maximum Units Notes V cc Power Supply Voltage Volts 1.0 V i Input Voltage Volts 1.0 T s Storage Temperature C 1.0 Table 3 Parameter Input Reference Frequency Available Output Frequencies Optional Reference Output Frequencies Input and Output Frequencies Frequency Dual 10 khz MHz Not Available Operating Specifications Table 4 Symbol Parameter Minimum Nominal Maximum Units Notes V cc Power Supply Voltage Volts 2.0 I cc Power Supply Current ma 5.0 T o Temperature Range 0-70 C F fr Free Run Frequency ppm F cap Capture/pull-in range ppm F bw Jitter Filter Bandwidth Hz 3.0 T jtol Input Jitter Tolerance µs (Input Jitter Frequencies 10 Hz) T aq Acquisition Time s 4.0 T rf Output Rise and Fall Time (20% 80%) ps 5.0 DC Output Duty Cycle % MTIE sr MTIE at Synchronization Rearrangement GR-253-CORE.1999 R , 7.0 Table 5 Output Jitter Specifications Jitter BW 10 Hz - 1 MHz SONET Jitter BW 12 khz - 20 MHz Frequency (MHz) ps (RMS) m UI ps (RMS) m UI Typ Typ. 1 Max Max. NOTES: 1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. 2.0 Requires external regulation and supply decoupling. (22 uf, 330 pf) 3.0 3db loop response. 4.0 From a 20 PPM step in reference frequency at V ohm load biased to 1.3 volts. 6.0 Entry into Free Run doesn t meet requirement for initial 2.33 seconds of self-timing. 7.0 If the selected reference is removed system response to the ALARM must be less than 100ns. Preliminary Data Sheet #: SG053 Page 3 of 16 Rev: P01 Date: 08/05/02

4 Table 6 Input And Output Characteristics Symbol Parameter Minimum Nominal Maximum Units Notes CMOS Input and Output Characteristics V ih High Level Input Voltage V V il Low Level Input Voltage V T io I/O to Output Valid ns C l Output Capacitance pf V oh High Level Output Voltage V V ol Low Level Output Voltage V T ir Input Reference Pulse Width ns PECL Output Characteristics V oh High Level PECL Voltage V V ol Low Level PECL Voltage V C l Output Capacitance pf T skew Differential Output Skew ps Table 7 Input Selection / Output Response INPUTS OUTPUTS NOTE RESET ENABLE SEL AB REF A REF B FR FR status ALARM Q QN 1 0 X X X X 1 X X X FR X 1 X X X X X X X X X 1 1 X X X FR A A X X RA A A X X RB NA A X X U NA A X X RB A NA X X U A NA X X RA 0 0 X NA NA X X FR NOTES: A Active FR Free Run Mode NA Not Active RA Locked to Reference A RB Locked to Reference B U Unstable (due to conditions shown, switch to active reference or Free Run) X Don t care Preliminary Data Sheet #: SG053 Page 4 of 16 Rev: P01 Date: 08/05/02

5 Pin Description Table 8 Pin # Pin Name Pin Information Note 1 ENABLE/TRI-STATE VCXO Enable. (Enable = 0, Disable = 1 = CMOS Outputs Tri-stated) TCK No Connection, Internal Factory Programming Input TDO No Connection, Internal Factory Programming Input REF A 10 khz, TTL/CMOS Reference Frequency Input. 5 SEL AB Input Reference Select Pin. (REFA = 0, REFB = 1) RESET RESET. (RESET = 1) REF B 10 khz, TTL/ CMOS Reference Frequency Input. 8 V ee Ground. 9 FR status Free Run Status. (FR = 1) 10 V cc Supply Voltage relative to ground. 11 N/C No Connection. (Optional Reference Output Available) 8.0, ALARM Loss of Reference / Lock alarm. ( = 1) 13 FR Force Free Run. (Phase Lock = 0, Free Run = 1) TDI No Connection, Internal Factory Programming Input TMS No Connection, Internal Factory Programming Input QN LVPECL Complementary Output. 17 V ee Ground. 18 Q LVPECL Output. NOTES 8.0 Do not connect pin 8.1 Contact a Sales Representative for availibilty and use of optional reference output 9.0 Input pulled to ground Circuit Board Footprint & Keepout Recommendations Figure [21.97 mm] [1.65 mm] [26.42 mm] [21.34 mm] Keep Out Area [2.54 mm] [2.54 mm] [27.18 mm] [0.89 mm] Preliminary Data Sheet #: SG053 Page 5 of 16 Rev: P01 Date: 08/05/02

6 Loss of Reference Condition Timing Figure 4 Start-up Region Output (LOR + LOL) LOR (Internal Signal) 4 LOL (Internal Signal) Phase Detector (Internal Signal) External Reference (Selected Input A or B) Internal Reference (Internal Signal) Timing Legend Use for all alarm timing diagrams Table 9 Start-up Region 10 khz Reference Input 1 < 1 µsec 2 1 µsec 3 > 1 µsec µsec(min) to 374 µsec(max) after LOL 5 Minimum pulse width = 2 µs During Start-up, The LOL will pulse during the few seconds of operation Preliminary Data Sheet #: SG053 Page 6 of 16 Rev: P01 Date: 08/05/02

7 Loss of Lock Condition Timing Figure 5 Output (LOR + LOL) LOR (Internal Signal) LOL (Internal Signal) 5 Phase Detector (Internal Signal) External Reference (Selected Input A or B) Internal Reference (Internal Signal) Preliminary Data Sheet #: SG053 Page 7 of 16 Rev: P01 Date: 08/05/02

8 Switch from A to B when both are good signals Figure 6 Ref A Ref B LOL portion of is Blanked 0.5 sec Sel A/B New Reference Qualification time Switch from A to B when Reference B is lost Figure 7 Ref A Ref B ~8ns Sel A/B Preliminary Data Sheet #: SG053 Page 8 of 16 Rev: P01 Date: 08/05/02

9 Switch from A to B after Reference A is lost Figure 8 Ref A Ref B Blanked Sel A/B µs (8 khz Ref units) 126µs (19.44 MHz Ref units) New Reference Qualification time Switch from A to B when A is out of range Figure 9 Ref A Ref B Out of Range In Range Blanked Sel A/B New Reference Qualification time Preliminary Data Sheet #: SG053 Page 9 of 16 Rev: P01 Date: 08/05/02

10 Switch from A to B when B is out of range Figure 10 Switch from A to B when B is out of range Ref A Ref B In Range Out of Range Blanked SEL A/B New Reference Qualification Time 0.5 sec. Switch from A to B after auto Free Run due to loss of both references Figure 11 Ref A Ref B Blanked Sel A/B Free Run Status New Reference Qualification time Preliminary Data Sheet #: SG053 Page 10 of 16 Rev: P01 Date: 08/05/02

11 Typical MTIE Measurement Figure 12 Typical TDEV Measurement Figure 13 Preliminary Data Sheet #: SG053 Page 11 of 16 Rev: P01 Date: 08/05/02

12 Recommended PECL Termination Figure VDC 3.3 VDC 3.3 VDC Vcc SCGxxx LVPECL OUTPUT Q 50 OHM Transmission Line D Vcc LVPECL INPUT GND QN 50 OHM Transmission Line DN GND 3.3 VDC 3.3 VDC Vcc - 2 VDC 3.3 VDC 50 Vcc SCGxxx LVPECL OUTPUT Q 50 OHM Transmis sion Line D Vcc LVPECL INPUT GND QN 50 OHM Transmission Line 50 DN GND Vcc - 2 VDC 3.3 VDC 3.3 VDC 150 Vcc SCGxxx LVPECL OUTPUT Q OHM Transmission Line 100 D Vcc LVPECL INPUT GND QN OHM Transmission Line DN GND If PECL outputs do not drive a long line (< 0.5 ), a single 150Ω termination resistor to ground may be used for each pin. Preliminary Data Sheet #: SG053 Page 12 of 16 Rev: P01 Date: 08/05/02

13 Tape and Reel Packaging Figure 15 Preliminary Data Sheet #: SG053 Page 13 of 16 Rev: P01 Date: 08/05/02

14 Solder Profile Figure Temp (C ) Time(minutes) Recommended Reflow Profile Peak Temp:217C MaxRiseSlope:1.5C /Sec Time Above150C :100Sec Ordering Information SCG{XXXX}-{FFF.FFF}{M} XXXX equals a specific model (4540) FFF.FFF equals the Oscillator Output frequency ( MHz) M equals MHZ and is added to all part numbers Example: To order an SCG4540 with an Oscillator Output of MHz, Order part number M Please contact Connor-Winfield for other frequencies that may be available. Preliminary Data Sheet #: SG053 Page 14 of 16 Rev: P01 Date: 08/05/02

15 Preliminary Data Sheet #: SG053 Page 15 of 16 Rev: P01 Date: 08/05/02

16 Revision Revision Date Note P00 07/08/02 Preliminary informational release P01 08/05/02 Advanced to Ver 3