GENLINX GS9000C Serial Digital Decoder

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1 GENLINX erial Digital Decoder HEET FEATURE fully compatible with MPTE 2M decodes and 0 bit serial digital signals for data rates to 30Mb/s pin and function compatible with G000, G000 and G000B 32mW power dissipation at 20MHz clock rates incorporates an automatic standards selection function with the G00A Receiver or G0A Reclocker operates from single + or volt supply enables an adjustmentfree Deserializer system when used with G00A and G00A or G0A 2 pin PLCC packaging APPLICATION 4ƒ C, 4:2:2 and 30Mb/s serial digital interfaces Automatic standards select controller for serial routing and distribution applications using G00A Receiver or G0A Reclocker DEICE DECRIPTION The is a CMO integrated circuit specifically designed to deserialize MPTE 2M serial digital signals at data rates to 30Mb/s. The device incorporates a descrambler, serial to parallel convertor, sync processing unit, sync warning unit and automatic standards select circuitry. Differential pseudoecl inputs for both serial clock and data are internally level shifted to CMO levels. Digital outputs such as parallel data, parallel clock, HYNC, ync Warning and tandard elect are all TTL compatible. The is designed to directly interface with the G00A Reclocking Receiver to form a complete MPTEserialin to CMO level parallelout deserializer. The may also be used with the G00A and the G00A to form an adjustmentfree receiving system which automatically adapts to all serial digital data rates. The G0A can replace the G00A in applications where cable equalization is not required. The is packaged in a 2 pin PLCC and operates from a single volt, ± % power supply. ERIAL IN ERIAL IN LEEL HIFT DECRAMBLER 30 BIT HIFT REG P PARALLEL OUT (0 BIT) ERIAL CLOCK IN ERIAL CLOCK IN YNC CORRECTION ENABLE 4 LEEL HIFT CLK YNC DETECT (3FF HEX) ync YNC CORRECTION Word Boundary PARALLEL TIMING GENERATOR PARALLEL CLOCK OUT YNC WARNING CONTROL ync Error YNC WARNING (chmitt Trigger Comparator) HYNC OUTPUT YNC WARNING FLAG TANDARD ELECT CONTROL AUTO TANDARD ELECT OC 2 BIT COUNTER Hsync Reset FUNCTIONAL BLOCK DIAGRAM Revision Date: February 2000 Document No GENNUM CORPORATION P.O. Box 4, tn. A, Burlington, Ontario, Canada LR 3Y3 Tel. + (0) 322 Fax. + (0) info@gennum.com

2 DECODER DC ELECTRICAL CHARACTERITIC =, T A = 0 C to 0 C unless otherwise shown PARAMETER YMBOL CONDITION MIN TYP MAX UNIT NOTE upply oltage Operating Range Power Consumption (outputs unloaded) CMO Input oltage Output oltage Input Leakage Current erial Clock and Data Inputs ignal wing ignal Offset P C IH IL OH OH MIN MAX MIN MAX I IN IN INO ƒ = 43MHz ƒ = 20MHz ƒ = 30MHz T A I OH I OL IN T A = 2 C 3. 4 = 4mA, 2 = 4mA, 2 = DD or = 2 C T A = 2 C, IN C C mw mw mw TET LEEL ± 0 µ A = 00 to 000mpp m pp Centre of swing DECODER AC ELECTRICAL CHARACTERITIC =, T A = 0 C to 0 C unless otherwise shown PARAMETER YMBOL erial Input Clock Frequency ƒ CI erial Input Data Rate erial Data and Clock Inputs: Risetime etup Hold DR t CONDITION Test Level Legend. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test.. Calculated result based on Level, 2, or 3.. Not tested. Guaranteed by design simulations.. Not tested. Based on characterization of nominal parts.. Not tested. Based on existing design/characterization data ABOLUTE MAXIMUM RATING of similar product. PARAMETER ALUE MIN t R t U HOLD T A = 2 C TYP MAX UNIT NOTE TET LEEL 30 MHz 30 Mb/ s Parallel Clock: Jitter tjclk T A = 2 C. 0 ns pp Parallel Data: Risetime and T A = 2 C, 20% to t Falltime RPDn 3 ns = 0pF 0% C L PDn to PCLK Delay Tolerance t D ± 3 ns ps ns ns Rising edge of PCLK to bit period centre ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE CPJ 2 Pin PLCC 0 C to 0 C CTJ 2 Pin PLCC Tape 0 C to 0 C upply oltage ( = ) Input oltage Range (any input) 0.3 to ( + 0.3) DC Input Current (any one input) ±0µA Operating Temperature Range 0 C to 0 C torage Temperature Range C to +0 C Lead Temperature (oldering, 0 seconds) 20 C

3 (MB) WF HYNC PD PD PD 24 PD TOP IEW PD PD4 2 PD PD2 C PD PIN DECRIPTION CE WC PCLK PD0 (LB) Fig. Pin Outs, 2 Pin PLCC Package PIN NO. YMBOL TYPE DECRIPTION HYNC Output Horizontal ync Output. CMO (TTL compatible) output that toggles for each TR detected. 2 Power upply. Most negative power supply connection. 3 WF Output ync Error Warning Flag. CMO (TTL compatible) active high output that indicates the preselected HYNC Error Rate (HER). The HER is set with an RC time constant on the WC input. 4 Power upply. Most negative power supply connection., / Inputs Differential, pseudoecl serial data inputs. ECL voltage levels with offset of 3.0 to 4.0 for operation up to 30MHz. ee AC Electrical Characteristics Table for details., / Inputs Differential, pseudoecl serial clock inputs. ECL voltage levels with offset of 3.0 to 4.0 for operation up to 30MHz. ee AC Electrical Characteristics Table for details.,0 / Output tandard elect Outputs. CMO (TTL compatible) outputs used with the G00A Receiver in order to perform an automatic standards select function. These outputs are generated by a 2 bit internal binary counter which stops cycling when there is no CARRIER present at the G00A Receiver input or when a valid TR is detected by the. C Input tandards elect Control. Analog input used to set a time constant for the standards select hunt period. An external RC sets the time constant. When a G00A Receiver is used, the open collector CARRIER DETECT output also connects to this pin in order to enable or disable the internal 2 bit binary counter which controls the hunting process. 2 Power upply. Most positive power supply connection. 3 Power upply. Most positive power supply connection. 4 CE Input ync Correction Enable. Active high CMO input which enables sync correction by not resetting the s internal parallel timing on the first sync error. If the next incoming sync is in error, internal parallel timing will be reset. This is to guard against spurious HYNC errors. When CE is low, a valid sync will always reset the s parallel timing generator

4 PIN DECRIPTION PIN NO. YMBOL TYPE DECRIPTION WC Input ync Warning Control. Analog input used to set the HYNC Error Rate (HER). This is accomplished by an external RC time constant connected to this pin. PCLK Output Parallel Clock Output. CMO (TTL compatible) clock output where the rising edge of the clock is located at the centre of the parallel data window within a given tolerance. ee Fig.. PD0 Output Parallel Data Output Bit 0 (LB). CMO (TTL compatible) descrambled parallel data output from the serial to parallel convertor representing the least significant bit (LB). Power upply. Most positive power supply connection. 2 PD PD Outputs Parallel Data Outputs Bit to Bit. CMO (TTL compatible) descrambled parallel data outputs from the serial to parallel convertor representing data bit through data bit. 2 Power upply. Most negative power supply connection. 2 PD Output Parallel Data Output. CMO (TTL compatible) descrambled parallel data output from the serial to parallel convertor representing data bit. 2 PD Output Parallel Data Output Bit (MB). CMO (TTL compatible) descrambled data output from the serial to parallel convertor representing the most significant bit (MB). INPUT / OUTPUT CIRCUIT R EXT C CE EXTERNAL COMPONENT Fig. 2 Pin C Fig. 3 Pin 4 CE BIA Fig. 4 Pins

5 DD R EXT WC k C EXT EXTERNAL COMPONENT OUTPUT Fig. Pin WC GND Fig. Pins 3,,, 2, 2, 2 WF, HYNC, I, D, PCLK, PD0 t CLKL = t CLKH /2 T /2 T ERIAL CLOCK () 0% PARALLEL (PDn) ERIAL () PARALLEL CLOCK (PCLK) 0% t U t HOLD t D Fig. Waveforms TET ETUP & APPLICATION INFORMATION Figure shows the test setup for the operating from a supply of + volts. The differential pseudo ECL inputs for and CLOCK (pins,, and ) must be biased between +3.0 and +4.0 volts. In the circuit shown, these inputs with the resistor values shown, can be directly driven from the outputs of the G00A Reclocking Receiver. In other cases, such as true ECL level driver outputs, two biasing resistors are needed on the and CLOCK inputs and the signals must be AC coupled. It is critical that the decoupling capacitors connected to pins 2,3 and be chip types and be located as close as possible to the device pins. In order to maintain very short interconnections when interfacing with the G00A Receiver, the critical high speed inputs such as erial Data (pins and ) and erial Clock (pins and ) are located along one side of the device package. If the automatic standard select function is not used, the tandard elect bits (pins and 0) do not need to be connected, however the control input (pin ) should be grounded

6 TANDARD ELECT BIT TANDARD ELECT BIT 0 + IN IN IN IN 00k 20p 3 x 00n ** 2 3 HYNC PD0 DECODER PDI 20 PD2 2 PD3 PD PD 24 0 PD PD 2 C PD 2 PD µ PCLK CE WC WF ** Locate the three 0.0µF decoupling capacitors as close as possible to the corresponding pins on the. Chip capacitors are recommended. HYNC OUTPUT PARALLEL BIT 0 PARALLEL BIT PARALLEL BIT 2 PARALLEL BIT 3 PARALLEL BIT 4 PARALLEL BIT PARALLEL BIT PARALLEL BIT PARALLEL BIT PARALLEL BIT PARALLEL CLOCK OUT YNC CORRECTION ENABLE 0p 3 x 42Ω YNC WARNING FLAG + 3k All resistors in ohms, all capacitors in farads, unless otherwise specified. Fig. Test etup With correctly synchronized serial data and clock connected to the, the HYNC output (pin ) will toggle for each HYNC detected. The Parallel Data bits PD0 through PD along with the Parallel Clock can be observed on an oscilloscope or fed to a logic analyzer. These outputs can also be fed through a suitable TTL to ECL converter to directly drive parallel inputs to receiving equipment such as monitors or digital to analog converters. In operation, the HYNC output from the decoder toggles on each occurrence of the timing reference signal (TR). The state of the HYNC output is not significant, just the time at which it toggles. 4ƒ C TREAM HYNC OUT 4:2:2 TREAM HYNC OUT T R E A ACTIE IDEO & H BLANKING H BLNK A T R ACTIE IDEO ACTIE IDEO & H BLANKING E A Fig. Operation of HYNC Output H BLNK T R A The HYNC output toggles to indicate the presence of the TR on the falling edge of PCLK, one data symbol prior to the output of the first word in the TR. In the following diagram, data is indicated in 0 bit Hex. PCLK PDN XXX 3FF XXX XXX 3FF XXX HYNC Fig. 0 Operation of HYNC with Respect to PCLK

7 CC + D CC µ 0µ INPUT GND 22n () 4p 4p 3 CC CC 0µ 0µ + ECL INPUT 0 p 0µ 0µ DDI DDI CC2 ƒ/2 EE3 (2) 0n CC CC EE AGC A/D I EE2 CC4 LOOP R CO0 R CO R CO2 EYE OUT R CO3 CC3 0µ CC 0 I G00A 2 DO 24 DO 23 CO 22 CO 2 20 CD 0µ CC CC WF 00 3k PD 24 PD 23 PD 22 PD4 2 PD PD2 PD C D CC D CC 0µ 0µ WF HYNC CE WC PD PD PCLK PDO INPUT ELECTION YNC WARNING FLAG HYNC OUTPUT PARALLEL BIT PARALLEL BIT PARALLEL BIT PARALLEL BIT PARALLEL BIT PARALLEL BIT 4 PARALLEL BIT 3 PARALLEL BIT 2 PARALLEL BIT PARALLEL BIT 0 PARALLEL CLOCK OUT YNC CORRECTION ENABLE k2 CC D CC 0µ k2 (3) 0k k 22n CC TAR ROUTED + µ (2) µ + CC 20 G00A P/N TDT 2 OUT CC 3 IN CD 4 4 COMP HYNC 3 3n3 LF ƒ/2 GND OC 2 0 DLY CC WF FCAP 0.µ 2n CC 00k TANDARD TRUTH TABLE ƒ/2 P/N TANDARD 0µ WF CC 0n (2) 0µ 0 0 4:2: :2: ƒsc NTC 4ƒsc PAL () Typical value for input return loss matching (2) To reduce board space, the two antiseries.µf capacitors (connected across pins 2 and 3 of the G00A) may be replaced with a.0µf nonpolarized capacitor provided that (a) the 0.µF capacitor connected to the OC pin () of the G00A is replaced with a 0.33µF capacitor and (b) the G00A /A Loop Filter Capacitor is 0nF. (3) Remove this potentiometer if P/N function is not required, and ground pin of the G00A. Fig. Application Circuit Adjustment Free Multistandard erial to Parallel Convertor, G00A and G00A INTERCONNECTION Figure shows an application of the in an adjustment free, multistandard serial to parallel convertor. This circuit uses the G00A Automatic Tuning ubsystem IC and a G00A erial Digital Receiver. The G00A may be replaced with a G0A Reclocker IC if cable equalization is not required. The G00A AT eliminates the need to manually set or externally temperature compensate the Receiver or Reclocker CO. The G00A can also determine whether the incoming data stream is 4ƒsc NTC,4ƒsc PAL or component 4:2:2. The G00A includes a ramp generator/oscillator which repeatedly sweeps the Receiver/Reclocker CO frequency over a set range until the system is correctly locked. An automatic fine tuning (AFT) loop maintains the CO control voltage at its centre point through continuous, long term adjustments of the CO centre frequency. During normal operation, the Decoder provides continuous HYNC pulses which disable the ramp/oscillator of the G00A. This maintains the correct Receiver/ Reclocker CO frequency. When an interruption to the incoming data stream is detected by the Receiver/Reclocker, the Carrier Detect goes LOW and tristates the AFT loop in order to maintain the correct CO frequency for a period of about 2 seconds. This allows the Receiver/Reclocker to rapidly relock when the signal is reestablished

8 YNC WARNING FLAG OPERATION Each time HYNC is not correctly detected, the ync Warning Flag output (pin 3 ) will go HIGH. The RC network connected to the ync Warning Control input (pin ) sets the number of sync errors that will cause the WF pin to go HIGH. The component values of the RC network shown in Figure 0 set the WF error rate to approximately one HYNC error in 0 lines. These component values are chosen for optimum performance of the WF pin, and should not be adjusted. Typically, HYNC errors will become visible on a monitor before the WF will provide an indication of HYNC errors. As a result, the WF function can be used in applications where the detection of significant signal degradation is desired. YNC WARNING CONTROL YNC ERROR k COMPARATOR Fig. 0 ync Warning Flag Circuit + 3 YNC WARNING FLAG (WF) A high WF will go low as soon as the input error rate decreases below the set rate. This response time is determined by C, as mentioned earlier. A small amount of hysteris in the comparator ensures noise immunity. CAUTION ELECTROTATIC ENITIE DEICE DO NOT OPEN PACKAGE OR HANDLE EXCEPT AT A TATICFREE WORKTATION DOCUMENT IDENTIFICATION: HEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION MAILING ADDRE: P.O. Box 4, tn. A, Burlington, Ontario, Canada LR 3Y3 Tel. + (0) 322 Fax + (0) 3224 HIPPING ADDRE: 0 Fraser Drive, Burlington, Ontario, Canada LL P REIION NOTE Updated values in Electrical Characteristics tables and added test levels with legend; Updated Figure (Test etup); Changed document from preliminary data sheet to data sheet; tandardized artwork. For the latest product information, visit GENNUM JAPAN CORPORATION C0, Miyamae illage, 2042 Miyamae, uginamiku, Tokyo 00, Japan Tel. + (3) Fax: + (3) 3243 GENNUM UK LIMITED 2 Long Garden Walk, Farnham, urrey, England GU HX Tel. +44 (0) Fax +44 (0) Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. Copyright August Gennum Corporation. All rights reserved. Printed in Canada

GENLINX II GS9032 Digital Video Serializer

GENLINX II GS9032 Digital Video Serializer GENLINX II G932 Digital Video erializer PRELIMINARY DATA HEET FEATURE fully compliant with MPTE 259M serializes 8-bit or 1-bit data beyond 54 Mb/s autostandard, adjustment free operation minimal external