AV9108. CPU Frequency Generator. Integrated Circuit Systems, Inc. General Description. Features. Block Diagram
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- Roderick Barrett
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1 Integrated Circuit Systems, Inc. AV98 CPU Frequency Generator General Description The AV98 offers a tiny footprint solution for generating two simultaneous clocks. One clock, the REFCLK, is a fixed output frequency which is the same as the input reference crystal (or clock). The other clock, CLK, can vary between 2 and 2 MHz, with up to 6 selectable preprogrammed frequencies stored in internal ROM. The ICS98 is ideal for use in a 3.3V system. It can generate a MHz clock at 3.3V. In addition, the ICS98 provides a symmetrical wave form with a worst case duty cycle of 45/55. The ICS98 has very tight edge control between the CPU clock and 2XCPU clock outputs, with a worst case skew of 25ps. The device has advanced features which include on-chip loop filters, tristate outputs, and power-down capability. A minimum of external components - two decoupling capacitors and an optional ferrite bead - are all that are required for jitter-free operation. Standard versions for computer motherboard applications are the AV98-3, AV98-5 and the ICS98-. Custom masked versions, with customized frequencies and features, are available in 6-8 weeks for a small NRE fee. Features Runs up to 8 MHz at 3.3V 5/5 typical duty cycle at 5V ±25ps absolute jitter Generates frequencies from 2 to 4 MHz 2 to 32 MHz input reference frequency Up to 6 frequencies stored internally Patented on-chip Phase Locked Loop with VCO for clock generation Provides reference clock and synthesized clock On-chip loop filter Low power.8µ CMOS technology 8-pin or 4-pin DIP or SOIC package Block Diagram AV98RevB3295
2 AV98 Pin Configuration FS 8 REFCLK GND 2 7 VDD X/ICLK 3 6 CLK X2 4 5 FS AV98-5/- 8-Pin DIP, SOIC FS 4 FS FS2 2 3 REFCLK FS3 3 2 VDD AGND 4 CLK GND 5 OE (CLK) PD 6 9 OE (REFCLK) X/ICLK 7 8 X2 AV98-3/- 4-Pin DIP, SOIC Pin Descriptions for AV98-3, AV98-5 and AV98- PIN NUMBER -5/-/-3-3 PIN NAME TYPE DESCRIPTION 4 FS Input Frequency Select for CLK (-3 has pull-up). 5 FS Input Frequency Select for CLK (-3 has pull-up). 2 FS2 Input Frequency Select 2 for CLK (-3 has pull-up). 3 FS3 Input Frequency Select 3 for CLK (-3 has pull-up). 4 AGND - Analog GROUND. 2 5 GMD - Digital GROUND. 6 PD Input POWER-DOWN. Shuts off chip when low. Internal pull-up. 3 7 X/ICLK Input CRYSTAL OUTPUT or INPUT CLOCK frequency. Typically 4.38 MHz system clock. 4 8 X2 Output CRYSTAL OUTPUT (No Connect when clock used.). 9 OE(REFCLK) Input OUTPUT ENABLE. Tristates REFCLK when low. Pull-up. OE(CLK) Input OUTPUT ENABLE. Tristates CLK when low. Pull-up. 6 CLK Output CLOCK Output (see decoding tables). 7 2 VDD - Digital power supply (+3V DC). 8 3 REFCLK Output REFERENCE CLOCK output. Produces a buffered version of the input clock or crystal frequency (typically 4.38 MHz). 2
3 AV98 Actual Frequencies Decoding Table for AV98-5, 4.38 input FS FS CLK Decoding Table for AV98-3, 4.38 input 4. MHz 5. MHz 66.6 MHz 8. MHz FS3 FS2 FS FS CLK 6. MHz MHz 5. MHz 8. MHz MHz.23 MHz 8.2 MHz 4. MHz 8.2 MHz 2. MHz 25.6 MHz 4. MHz MHz 5. MHz 4. MHz 2.5 MHz Decoding Table for AV98- (in MHz) FS3 FS2 FS FS CLK 6. MHz MHz 5. MHz 8. MHz MHz.23 MHz 6. MHz 4. MHz 8.2 MHz 2.5 MHz 25.6 MHz MHz MHz 5. MHz 3. MHz 4. MHz Decoding Table for AV98-, 4.38 input FS FS CLK MHz MHz 4.6 MHz 5.3 MHz Note: The dash number following ICS98 must be included when ordering product since it specifies the frequency decoding table being ordered. Decoding options can be created by a simple metal mask change. 3
4 AV98 Frequency Accuracy and Calculation The accuracy of the frequencies produced by the ICS98 depends on the input frequency and the desired actual output frequency. The formula for calculating the exact frequency is as follows: A Output Frequency = Input Frequency B where A=2, 3, , and B=2, 3, For example, to calculate the actual output frequency for a video monitor expecting a 44.9 MHz clock and using a 4.38 MHz input clock, the closest A/B ratio is 69/22, which gives an output of MHz (within.2% of the target frequency). Generally, the ICS98 can produce frequencies within.% of the desired output. Allowable Input and Output Frequencies The input frequency should be between 2 and 32 MHz and the A/B ratio should not exceed 24. The output should fall in the range of 2-2 MHz. Output Enable The Output Enable feature tristates the specified output clock pins. This places the selected output pins in a high impedance state to allow for system level diagnostic testing. Power-Down If equipped, the power-down shuts off the specified PLL or entire chip to save current. A few milliseconds are required to reach full functioning speed from a power-down state. Frequency Transitions A key ICS98 feature is the ability to provide glitch-free frequency transitions across its output frequency range. The ICS98 provides smooth transitions between any of the two groups of eight frequencies (when FS3= or FS3=), so that the device will switch glitch-free between 4- MHz and 2-5 MHz. 4
5 AV98 Absolute Maximum Ratings AVDD, VDD referenced to GND V Operating temperature under bias C to +7 C Storage temperature C to +5 C Voltage on I/O pins referenced to GND GND -.5V to VDD +.5V Power dissipation Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 5V (Operating VDD = +4.5V to +5.5V; TA = C to 7 C unless otherwise stated) DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage V IL V Input High Voltage V IH V Input Low Current I IL V IN=V µa Input High Current I IH V IN=V DD µa Output Low Voltage V OL I OL=mA V Output High Voltage, Note V OH I OH=-3mA V Output Low Current, Note I OL V OL=.8V ma Output High Current, Note I OH V OH=2.V ma Supply Current I CC Unload, 5 MHz ma Supply Current I CC Unload, Logic Inputs µa (PD low) Supply Current I CC (PD low) Unload, Logic Inputs µa Pull-up Resistor, Note R pu k ohms AC Characteristics Rise Time.8 to 2.V, Note T r 5pf load ns Fall Time 2. to.8v, Note T f 5pf load -.4. ns Rise Time 2% to 8%, Note T r 5pf load ns Fall Time 8% to 2%, Note T f 5pf load ns Duty Cycle, Note D t 5pf % Jitter, One Sigma, Note T jis From 2 to MHz ps Jitter, One Sigma, Note T jis From 4 to 6 MHz. 2. ps Jitter, One Sigma, Note T jis From 4 to Below.2. % Jitter, Absolute, Note T jab From 2 to MHz ps Jitter, Absolute, Note T jab From 4 to 6 MHz ps Jitter, Absolute, Note T jab From 4 to Below. 3. % Input Frequency, Note F i MHz Output Frequency F o MHz Power-up Time, Note T pu ms Transition Time, Note T ft 8 to 66.6 MHz ms Note : Parameter is guaranteed by design and characterization. Not % tested in production. 5
6 AV98 Electrical Characteristics at 3.3V (Operating VDD = +3.V to +3.7V; TA = C to 7 C unless otherwise stated) DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage V IL - -.2V DD V Input High Voltage V IH.7V DD - - V Input Low Current I IL V IN=V µa Input High Current I IH V IN=V DD µa Output Low Voltage V OL I OL=6mA -.5. V Output High Voltage V OH I OH=-5mA V Output Low Current I OL V OL=.2V DD ma Output High Current I OH V OL=.7V DD ma Supply Current I CC Unloaded, 5 MHz ma Supply Current I CC Unload, Logic Inputs µa (PD low) Supply Current I CC (PD low) Unload, Logic Inputs µa Pull-up Resistor R pu k ohms AC Characteristics Rise Time 2% to 8%, Note T r 5pf load ns Fall Time 8% to 2% T f 5pf load ns Duty Cycle D t 5pf 5% % Jitter, One Sigma T jis From 25 to 85 MHz ps Jitter, One Sigma T jis From 4 to 2 MHz. 2. ps Jitter, One Sigma T jis From 4 to Below.4. % Jitter, Absolute T jab From 25 to 85 MHz ps Jitter, Absolute T jab From 4 to 2 MHz ps Jitter, Absolute T jab From 4 to Below. 3. % Input Frequency F i MHz Output Frequency F o MHz Power-up Time, Note T pu ms Transition Time, Note T ft 8 to 66.6 MHz ms Parameter is guaranteed by design and characterization. 6
7 AV98 8-Pin DIP Package 4-Pin DIP Package Ordering Information Example: AV98-XXCN8, ICS98-XXCN4 XXX XXXX- XX M X#W Lead Count & Package Width Lead Count=, 2 or 3 digits W=.3 SOIC or.6 DIP; None=Standard Width Package Type N=DIP (Plastic) Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 7
8 AV98 8-Pin Plastic SOIC 4-Pin SOIC Package Ordering Information Example: ICS98-XXCS8, IS98-XXCS4 XXX XXXX- XX M X#W Lead Count & Package Width Lead Count=, 2 or 3 digits W=.3 SOIC or.6 DIP; None=Standard Width Package Type S=SOIC Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 8
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