Programmable RS-232/RS-485 Transceiver

Transcription

1 SP334 Programmable RS-3/ Transceiver V Single Supply Operation Software Programmable RS-3 or Selection Three RS-3 Drivers and Five Receivers in RS-3 Mode Two Full-Duplex Transceivers in Mode Full Differential Driver Tri-State (Hi-Z) Control Receiver Output Tri-State Control TI3 TXEN(n/c) TX4(n/c) TX3 VCC TX1 TX C1 V C C1 C V SP TI TI1 RS3/RS4 RI RX RX4 RX3 RX RX1 RI4 RI3 RI RI1 (in RS-3 Mode) DESCRIPTION The SP334 is a programmable RS-3 and/or transceiver IC. The SP334 contains three drivers and five receivers when selected in RS-3 mode; and two drivers and two receivers when selected in mode. The RS-3 transceivers can typically operate at 30kbps while adhering to the RS-3 specifications. The transceivers can operate up to Mbps while adhering to the specifications. The drivers can be disabled (High-Z output) by the TXEN enable pin. The RS-3 and receiver outputs can be disabled by the pin. V TYPICAL APPLICATIONS CIRCUIT 1 C1 C1- C C- VCC SP334 V 14 V- TXEN 7 TI1 1 TI3 1 RX1 T1 T3 R1 TX 7 TX1 6 TX4 3 TX3 4 RI1 1 1 RI 16 1 RI4 1 1 RX3 R3 1 RI RS3/ RS4 V 1

2 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. V CC...7V Input Voltages Logic...-0.V to (0.V) Drivers...-0.V to (0.V) 0mA Driver Outputs.../-1V Maximum Data Rate...Mbps (note 1) Storage Temperature...-6 C to C Power Dissipation -pin WSOIC...00mW Package Derating: -pin WSOIC ø JA...40 C/W Note 1: Exceeding the maximum data rate of Mbps at T A = C may permanently damage the device SPECIFICATIONS Limits are specified at T A = C and V CC =. unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS Logic Inputs V IL 0. Volts V IH.0 Volts LOGIC OUTPUTS V OL 0.4 Volts I OUT = -3.mA V OH.4 Volts I OUT = 1.0mA Output Tri-state Leakage µa 0.4V V OUT.4V RS-3 DRIVER DC Characteristics HIGH Level Output Volts R L = 3kΩ, V IN = 0.V LOW Level Output Volts R L = 3kΩ, V IN =. Open Circuit Voltage -1 1 Volts Short Circuit Current /-0 ma V OUT = Power Off Impedance 300 Ω V CC =, V OUT = /-. AC Characteristics Slew Rate 30 V/µs R L = 3kΩ, C L = 0pF; V CC =., T C Transistion Time 1.6 µs R L = 3KΩ, C L = 00pF; between /-3V, T C Maximum Data Rate 3 kbps R L = 3kΩ, C L = 00pF Propagation Delay t PHL µs Measured from 1.V of V IN to 0% Propagation Delay t PLH µs of V OUT ; R L = 3kΩ RS-3 RECEIVER DC Characteristics HIGH Threshold Volts LOW Threshold Volts Receiver Open Circuit Bias.0 Volts Input Impedance 3 7 kω V IN = 1V to -1V

3 SPECIFICATIONS Limits are specifed at T A = C and V CC =. unless otherwise PARAMETER MIN. TYP. MAX. UNITS CONDITIONS RS-3 RECEIVER (continued) AC Characteristics Maximum Data Rate 3 kbps Propagation Delay t PHL 0. 1 µs Measured from 0% of V IN to 1.V Propagation Delay t PLH 0. 1 µs of V OUT DRIVER DC Characteristics Open circuit Voltage 6.0 Volts Differential Output 1..0 Volts R L = 4Ω, C L = 0pF Balance /-0. Volts V T - V T Common-Mode Output 3.0 Volts Output Current.0 ma R L = 4Ω Short Circuit Current /-0 ma Terminated in -7V to 1 AC Characteristics Maximum Data Rate Mbps R L = 4Ω Maximum Data Rate Mbps R L = 4Ω, T A = C, Note 1 Output Transition Time 30 ns Rise/Fall time, %-0% Propagation Delay t PHL 0 ns See Figures 3 &, R DIFF = 4Ω, Propagation Delay t PLH 0 ns C L1 = C L = 0pF Driver Output Skew 0 ns Per Figure, t SKEW = t DPHL - t DPLH RECEIVER DC Characteristics Common Mode Range Volts Receiver Sensitivity /-0. Volts -7V V CM 1V Input Impedance 1 1 kω -7V V CM 1V AC Characteristics Maximum Data Rate Mbps Maximum Data Rate Mbps T A = C, Note 1 Propagation Delay t PHL 0 00 ns See Figures 3 & 7, R DIFF = 4Ω, Propagation Delay t PLH 0 00 ns C L1 = C L = 0pF Differential Receiver Skew 0 ns t SKEW = t PHL - t PLH, R DIFF = 4Ω, C L1 = C L = 0pF, see Figure ENABLE TIMING DRIVER Enable Time (see Figures 4 and 6) Enable to LOW 0 ns C L = 1pF, S 1 Enable to HIGH 0 ns C L = 1pF, S Note 1: Exceeding the maximum data rate of Mbps at T A = C may damage the device. 3

4 SPECIFICATIONS Limits are specifed at T A = C and V CC =. unless otherwise PARAMETER MIN. TYP. MAX. UNITS CONDITIONS Driver Continued Disable Time (see Figures 4 and 6) Disable from LOW 0 ns C L = 1pF, S 1 Disable from HIGH 0 ns C L = 1pF, S RECEIVER Enable Time (see Figures and ) Enable to LOW 0 ns C L = 1pF, S 1 Enable to HIGH 0 ns C L = 1pF, S Disable Time (see Figures and ) Disable from LOW 0 ns C L = 1pF, S 1 Disable from HIGH 0 ns C L = 1pF, S POWER REQUIREMENTS Supply Voltage V CC 4.7. Volts Supply Current I CC No Load (T X Disabled) 1 0 ma TXEN = No Load (RS-3 Mode) 0 0 ma RS3/RS4 = No Load ( Mode) 1 0 ma RS3/RS4 = V ENVIRONMENTAL Operating Temperature Commercial (_C_) 0 70 ºC Industrial (_E_) -40 ºC Storage Temperature -6 ºC 4

5 RECEIVER INPUT GRAPH RECEIVER 1.0mA -7V -3V 6V 1V -0.6mA 1 Unit Load Maximum Input Current Versus Voltage Test Circuits A R Receiver Test Point Output S 1 1kΩ V CC V OD C RL 1kΩ R V OC B S Figure 1. Driver DC Test Load Circuit Figure. Receiver Timing Test Load Circuit DI A B R L C L1 C L A B RO 1pF Output Under Test C L 00Ω S 1 V CC S Figure 3. Driver/Receiver Timing Test Circuit Figure 4. Driver Timing Test Load # Circuit

6 SWITCHING WAVEFORMS DRIVER INPUT DRIVER OUTPUT DIFFERENTIAL OUTPUT V A V B 3V B A V O V O V O 1/V O f 1MHz; t R ns; t F ns 1.V 1.V t PLH t PHL t DPLH t DPHL t R t F 1/V O t SKEW = t DPLH - t DPHL Figure. Driver Propagation Delays 3V TXEN V A, B.3V V OL f = 1MHz; t R < ns; t F < ns 1.V 1.V t ZL t LZ Output normally LOW 0.V A, B V OH.3V t ZH Output normally HIGH 0.V t HZ Figure 6. Driver Enable and Disable Times f = 1MHz; t R ns; t V F ns OD A B V INPUT OD V OH RECEIVER OUT 1.V OUTPUT 1.V V OL t PHL t PLH Figure 7. Receiver Propagation Delays 6

7 3V 1.V f = 1MHz; t 1.V R ns; t F ns t ZL t LZ V RECEIVER OUT 1.V Output normally LOW V 0.V IL V IH RECEIVER OUT 1.V t ZH Output normally HIGH 0.V t HZ t SKEW = t PHL - t PLH Figure. Receiver Enable and Disable Times TTL Input TTL INPUT Driver Output A Driver Output B DRIVER OUTPUT Differential Output VA - VB Figure. Typical RS-3 Driver Output Figure. Typical Driver Output TI3 TXEN(n/c) TX4(n/c) TX3 VCC TX1 TX C1 V C C1 C V SP334 (in RS-3 Mode) TI TI1 RS3/RS4 RI RX RX4 RX3 RX RX1 RI4 RI3 RI RI1 Figure. SP334 Pinout 7

8 V VCC SP334 RS3/RS4 V V C1 1 C1- C C- C1 C1- C C- V VCC SP334 V 14 V- N/C 7 TI1 TI 1 TI3 1 RX1 T1 T T3 R1 TX1 TX TX3 RI N/C RS-3 RS-3 RS-3 RS-3 7 TI1 1 TXEN TI3 1 RX1 T1 T3 R1 TX 7 TX1 6 TX4 3 TX3 4 RI1 1 1 RI RX 1 RX3 RX4 3 RX R R3 R4 R RI 16 RI3 17 RI4 1 RI 4 RS-3 RS-3 RS-3 RS-3 1 RX3 6 R3 1 RI RS3/ RS4 MDDE RI4 1 V 6 RS-3 MODE Figure 1. Typical Operating Circuit Theory of Operation The SP334 is made up of four separate circuit blocks the charge pump, drivers, receivers, and decoder. Each of these circuit blocks is described in more detail below. ChargePump The charge pump is a Exarpatented design (U.S.,306,4) and uses a unique approach compared to older less efficient designs. The charge pump still requires four external capacitors, but uses a fourphase voltage shifting technique to attain symmetrical 1 power supplies. Figure 17(a) shows the waveform found on the positive side of capacitor C, and Figure 17(b) shows the negative side of capacitor C. There is a freerunning oscillator that controls the four phases of the voltage shifting. A description of each phase follows. C 1 is transferred to C. Since C is connected to V, the voltage potential across capacitor C is now 1. Phase V SS transfer Phase two of the clock connects the negative terminal of C to the V SS storage capacitor and the positive terminal of C to ground, and transfers the generated l to C 3. Simultaneously, the positive side of capacitor C 1 is switched to V and the negative side is connected to ground. Phase 3 V DD charge storage The third phase of the clock is identical to the first phase the charge transferred in C 1 produces V in the negative terminal of C 1, which is applied to the negative side of capacitor C. Since C is at V, the voltage potential across C is l. Phase 1 V SS charge storage During this phase of the clock cycle, the positive side of capacitors Phase 4 C 1 and C are initially charged to V. C 1 is V DD transfer The fourth phase of the then switched to ground and charge on clock connects the negative terminal of C

9 to ground and transfers the generated l across C to C 4, the V DD storage capacitor. Again, simultaneously with this, the positive side of capacitor C 1 is switched to V and the negative side is connected to ground, and the cycle begins again. Since both V and V are separately generated from V CC in a noload condition, V and V will be symmetrical. Older charge pump approaches that generate V from V will show a decrease in the magnitude of V compared to V due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 1kHz. The external capacitors must be a minimum of with a 16V breakdown rating. External Power Supplies For applications that do not require V only, external supplies can be applied at the V and V pins. The value of the external supply voltages must be no greater than ±l. The current drain for the ±1 supplies is used for RS-3. For the RS-3 driver the current requirement will be 3.mA per driver. The external power supplies should provide a power supply sequence of :l, then V, followed by l. V CC = V V C 1 C V V V CC = V C 1 C 1 C 4 Figure. Charge Pump Phase 1. V CC = V V C 1 C V V C 3 C 4 Figure 14. Charge Pump Phase. V CC = V 1 C 3 C 4 Figure 1. Charge Pump Phase 3. C 1 C C 3 C 4 V DD Storage Capacitor V SS Storage Capacitor V DD Storage Capacitor V SS Storage Capacitor V DD Storage Capacitor V SS Storage Capacitor V DD Storage Capacitor V SS Storage Capacitor C 3 Figure 16. Charge Pump Phase 4. 1 a) C b) C- -1 Figure 17. Charge Pump Waveforms

10 Drivers The SP334 has three independent RS-3 single-ended drivers and two differential RS- 4 drivers. Control for the mode selection is done by the RS3/RS4 select pin. The drivers are pre-arranged such that for each mode of operation the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line signal levels. Unused driver inputs can be left floating; however, to ensure a desired state with no input signal, pullup resistors to V or pulldown resistors to ground are suggested. Since the driver inputs are both TTL or CMOS compatible, any value resistor less than 0kΩ will suffice. When in RS-3 mode, the single-ended RS-3 drivers produce compliant RS-3E and ITU V. signals. Each of the three drivers output single-ended bipolar signals in access of ±V with a full load of 3kΩ and 00pF applied as specified. These drivers can also operate at least kbps. When programmed to mode, the differential drivers produce complaint signals. Each driver outputs a unipolar signal on each output pin with a magnitude of at least 1.V while loaded with a worst case of 4Ω between the driver's two output pins. The signal levels and drive capability of the drivers allow the drivers to also comply with RS-4 levels. The transmission rate for the differential drivers is Mbps. Receivers The SP334 has five single-ended receivers when programmed for RS-3 mode and two differential receivers when programmed for mode. output, a pullup resistor of 0kΩ to V should be connected to the inverting input for a logic low, or the noninverting input for a logic high. For single-ended receivers, a pulldown resistor to ground of kω is internally connected, which will ensure a logic high output. The RS-3 receiver has a singleended input with a threshold of 0.V to.4v. The RS-3 receiver has an operating voltage range of ±1V and can receive signals up to kbps. RS-3 receivers are used in RS-3 mode for all signal types include data, clock, and control lines of the RS-3 serial port. The differential receiver has an input impedance of 1kΩ and a differential threshold of ±00mV. Since the characteristics of an RS-4 receiver are actually subsets of, the receivers for RS-4 requirements are identical to the receivers. All of the differential receivers can receive data up to Mbps. Enable Pins The SP334 drivers can be enabled by use of the TXEN pin. A logic HIGH will enable the driver outputs and a logic LOW will tristate the outputs. The drivers can only be tri-stated in mode. The drivers are always active in RS-3 mode. The Receiver outputs can also be tri-stated by the use of the pin. A logic LOW will enable the receiver outputs and a logic HIGH will tri-state the outputs.. The receiver tri-state capability is offered for both RS-3 and modes. The input impedance of the receivers during tri-state is at least 1kΩ. Applications The SP334 allows the user flexibility in having a RS-3 or serial port without using two different discrete active IC's. Figure 1 shows a connection to a standard DB- RS-3 connector. In mode, the SP334 is a full duplex transceiver, however, a half duplex configuration can be made by connecting the driver outputs to receiver inputs. Control for the mode selection is done by the same select pin as the drivers. As the operating mode of the receivers is changed, the electrical characteristics will change to support the requirements of the appropriate serial standard. Unused receiver inputs can be left floating without causing oscillation. To ensure a desired state of the receiver

11 V C1 1 C1- C C- VCC SP334 V V- 14 RS3/RS4 TxD 7 TI1 T1 TX1 6 RTS DTR TI 1 TI3 T T3 TX TX DCD DSR RxD 6 RxD CTS DSR DCD RI 1 RX1 0 RX 1 RX3 RX4 3 RX R1 R R3 R4 R RI1 1 RI 16 RI3 17 RI4 1 RI 4 RTS TxD CTS DTR RI SG 6 Figure 1. SP334 Configuration to a DB- Serial Port

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13 ORDERING INFORMATION Model Temperature Range Package Types SP334CT-L... 0 C to 70 C...-pin WSOIC SP334CT-L/TR... 0 C to 70 C...-pin WSOIC SP334ET-L C to C...-pin WSOIC SP334ET-L/TR C to C...-pin WSOIC Note: /TR = Tape and Reel revision history DATE REVISION DESCRIPTION 000 SP334/ Legacy Sipex Datasheet 0/0/ Convert to Exar Format. Add typical application circuit to page 1 and Revision History table. Remove EOL part numbers and update ordering information per PDN Change revision to Add Maximum Data Rate to Absolute Maximum Ratings. Add Driver and Receiver data rate column for Mbps maximum at Tmax and add Note 1. Notice EXAR Corporation reserves the right to make changes to any products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writting, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 00 EXAR Corporation Datasheet August 00 Send your Interface technical inquiry with technical details to: uarttechsupport@exar.com Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.