Board-level Timing Analysis in a High-speed Design Flow

Transcription

1 TECHNICAL PUBLICATION Board-level Timing Analysis in a High-speed Design Flow Matthew Hogan senior Coprorate Applications Engineer Mentor Graphics Corporation Novemeber

2 Abstract As timing margins shrink due to faster clock speeds, board level timing analysis becomes essential to maintain manufacturing yields and system reliability. This paper explores how systemtiming problems often occur as a result of timing variations. Timing variations in FPGA routing, board routing, clock skews between components and signal integrity effects, such as reflections and crosstalk, are addressed, as well as the modeling requirements for board level timing verification. Mentor Graphics system design tools, including the symbolic timing analysis tool Tau, are used to demonstrate this verification process. 1. Introduction The design of high-speed digital circuits has led to the necessary adoption of verification and analysis software tools. Designers at the forefront of PCB design have been using analysis and verification tools for some time. Quite often, these tools have only concerned themselves with the analog side of the problem, that of signal integrity. The digital side, timing, is often overlooked or preformed by hand calculations. Complete verification of circuit performance consists of both signal integrity and timing analysis. This paper refers extensively to device manufacturers' data sheets [2][3][4][5]. It is advisable the reader obtain copies of these published works and refer to them as needed. 2. Benefits of Board Level Timing Verification As device switching speeds increase, so too has the desire to design system products that take advantage of these faster devices. The timing margins that we once had are no longer available and more demands are being placed on validation of reliable system operation. Validation is becoming more difficult as designs include complex devices with multiple functional profiles, and timing variations. In today's design environment, time to market and development windows are of paramount importance. It becomes more crucial to locate and resolve timing problems as early in the design process as possible. Designers need to be able to use the most effective combination of devices without sacrificing performance. This also requires adherence to strict financial budgets. To ensure robust system operation, designers need to assess timing margins for extreme conditions. The performance expectations that are set for circuit and board designers require a full view of the timing problem. The circuit designer needs an accurate representation of the timing margins involved in order to Total Parts % 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% select the correct combination of parts; the board designer needs timing budgets in order to drive the physical design tools and to provide an accurate guide for component placement and routing constraints. As is often the case, prototypes are built to prove design decisions. Devices used in these prototypes are often purchased from a single vendor, and often represent a single manufacturing run of components. These devices will not exhibit the broad spectrum of component delay variations normally seen over the product life cycle. Figure 1 shows such a device spread Field Manuf Figure 1: Component Delay Variation Prototype Delay Variation (ns) Figure 1 shows that parametric windows of timing delay variations during the prototype stage represent a very small sampling of devices. As the product goes into manufacturing, a larger sampling of devices is seen. Over time, as the product matures and is in the field, we see the full timing view of all devices. Parametric windows within a distribution of delay variations do not have to be centered. This distribution can be in the upper quartile, for example, and still result in timing problems. Ensuring a design will operate over the distribution of timing delay variations requires designers to consider the timing variations throughout the design process. During the design phase of a product, designers must proactively design for timing variations. Informal, or manual methods, such as using Excel Spreadsheets, require extensive programming to ensure that they evaluate the full range of devices. Often, the results of these informal methods are difficult to validate and provide little or no opportunity for reuse with other designs. Static timing analysis which IC designers use to verify the correct timing operation of ICs and FPGAs, lends itself well to organized, and repeated synchronous circuits, often operating with a single clock source. Static timing analysis typically produces a large number of false timing paths. False timing paths are paths that violate timing requirements, but occur in modes or operating conditions that are not present in the device during operation. Another timing validation method is use of a functional simulator. While producing exceptionally accurate results, this method of PAGE 2

3 validation requires extensive runtime, and complex, fully functional device models. Often, functional simulators permit software to be run on the virtual devices they are testing. This allows functional simulators to exercise many conditions, but only gives the designer a parametric view of timing. An exceptional tool, functional simulators are best used when a design is near completion, and detailed functional modes of device behavior are known. The end of the product development life cycle is too late to influence change, or to provide feedback on the fundamental design of a PCB. The disparity between the two traditional analysis methods, static timing analysis and functional simulation, leads to the conclusion that board level timing requires a method that reduces the large number of false timing path errors reported by static timing analysis tools, and reduces the time and test vector overhead of a functional simulator. This solution is available to circuit and board designers in the form of symbolic timing analysis. 3. Symbolic Timing Analysis with Tau Tau provides the static timing verification required for simple synchronous circuits, and adds asynchronous verification without producing false timing errors. Tau accomplishes this by looking at the full timing spread of devices a design uses, and recognizing functionality that alters or differentiates timing. Tau uses a combination of netlist and models to provide an accurate representation of component variations and presents the designer with a concise list of relevant timing equations. The designer is not presented with volumes of false timing errors that require individual assessment and elimination. Tau enables designers to have the best of both worlds - accurate timing analysis, without the false timing paths of static timing or the overhead of fully functional simulations. Tau accomplishes this task by performing three fundamental types of analysis: Clock Tree Analysis, Synchronous verification, and Asynchronous verification. 4. Using Tau in a Design Flow From the first schematic entry session, to the final routed traces on a PCB, Tau provides board level timing analysis and verification at every stage of the design process. Schematic-based interfaces, including EDIF, allow extraction of netlist data for timing verification. Tau is able to drive the layout process by communicating interconnect delay requirements to the board layout system. This is accomplished with a bi-directional.board pathway which enables Tau to produce SDF files for board layout tools; board layout tools can export SDF files for Tau. Placement files can also be used to approximate expected delays. Accurate SDF files from the board Design Creation Design Architect Design View EDIF layout tools contains physical phenomenon, such as timing pull-in, or push-out due to crosstalk with other nets and the actual interconnect delay calculated. Figure 2 illustrates how Tau fits into a high-speed design flow. Tau Tau Models SDF Figure 2: Tau in high-speed design flow One of the most daunting tasks faced by today's board designers is the expedient verification of FPGAs. Versatile at solving many design problems, FPGAs pose a unique dilemma for timing verification. Each turn of an FPGA has slight timing differences. Verifying this timing with confidence, and in a short time, can be a daunting task. STAMP models from FPGA vendor tools offer integration into the design process by being able to easily incorporate FPGA timing into the design. You can validate different place and route runs from an FPGA design within the board design context with reproducible results. 5. Understanding Tau Models Interconnect Delay Estimation Interconnect Delay Calculation Placement File Board Layout IBIS Models Symbolic timing models are used in conjunction with Tau to facilitate timing verification. These models contain timing delays, timing constraints, and sufficient functionality to eliminate false timing errors. Tau models are created using the Tau Library Editor. Tau models consist of three sections: Cells, Finite State Machines (FSMs), and Delay Correlation. Cells define the structure of a component and consist of device pin names, called Ports. These are usually the pin names manufactures use in their data sheets. For convenience, Tau bundles similar pins together to form a BusPort. Pins that are candidates for this bundling include address pins, data pins, or multiple control lines that have the same functionality. The multiple RAS and CAS lines found on some memory and memory controllers are candidates for this type of bundling. BusPorts that contains a single signal, have a signal width of 1, while BusPorts that contain multiple signals, have a width of the number of signals the bundle contains. Figure 3 shows a typical Cell Structure in Tau. PAGE 3

4 Figure 3: Cell Structure for MC100LVELT22 Timing characteristics for Cells are read into the Tau Library Editor from STAMP files, or entered by hand from manufacturer data sheets. The spreadsheet like interface of both Tau, and the Tau Library Editor make the one-time task of entering these parameters intuitive and expedient. Other electronic formats are also available for import of timing characteristics. Once the Cell Structure and Cell Timing are defined, the functional part of the model is defined. The functionality within a Tau model is expressed as a Finite State Machine (FSM). FSMs afford a great deal of flexibility for the definition of Tau models without complicating the modeling process. FSMs are defined as either synchronous or asynchronous. FSMs that form part of a clock tree structure are asynchronous for propagation of the clock signal. Depending upon the complexity of the device you model, Tau automates all FSM creation except for the most complex asynchronous models. The command within the Tau Library Editor that automates the FSM creation process is Cell>Create FSM from Timing. It is important to specify your timing characteristics correctly to ensure that the FSM automatically created from timing is correct. It is quite conceivable that a device may have different regions of functionality. Each of these different functioning areas would have separate FSMs, and in doing so, it is possible to have both synchronous and asynchronous FSMs describing the behavior of the different sections of a single device. Output pin skew relationships are defined by specifying a Delay Correlation for the pin, or groups of pins in question. The different sections that form a Tau model are entered through a spreadsheet interface on five separate sheets: Cell Structure, Cell Timing, FSM Signals, FSM Behavior, and Delay Correlation. 5.1 Modeling Clock Trees One of the most common timing problems in synchronous circuits is clock skew [1]. Clock tree analysis is an important and integral part of the timing verification offered by Tau. In general, there are two types of clock propagation devices. The first simply regenerates the clock signal and provides the fastest path through the device. Sometimes, a true and complement signal pair are presented as outputs, but the primary behavior is to propagate the clock with little, or no change. The second is a complex clock device. Often employing a Phased Lock Loop (PLL), clock multiplication or division, these devices have outputs that are relative to the input clock and are altered by more than just a propagation delay through the device. Both types of devices are easily modeled within Tau. Figure 4 shows a typical clock tree. Clock tree analysis focuses on skew and phase shift as a clock signal propagates from its source to its clocking points. A clock tree has a single source, which is the output of a PLL driver or a crystal oscillator. From this source, the clock signal is distributed to different clocking points (clock sinks) on a circuit. The circuitry in the clock tree typically consists of buffers and frequency dividers [7]. PAGE 4

5 source 1 clk1 clk1 2 clk2 3 skew phase shift 4 5 clk2 Figure 4: A Typical Clock Tree Modeling of simple and complex clock propagation devices will be addressed in the following example. The devices chosen are from Motorola [2][3], and serve as good vehicles to demonstrate the modeling of typical clock devices. Many of these devices have signals that are taken directly from crystals or other oscillating devices. To identify the nets coming from these devices are the source of the clock tree, two properties are added to the net with a value of TRUE. The two properties that signify the top of a clock tree are ICX_CLOCK_NET and ICX_SOURCE_NET. The addition of these two properties ensures that Tau can identify the top of the clock tree LVTL/LVCMOS to Differential LVPECL Translator, MC100LVELT22 [2] Although not strictly a clock regeneration or propagation device, this clock to differential clock driver demonstrates how to readily model an entire family of similar devices. It contains two halves, a D0 to Q0 and nq0 half, and a D1 to Q1 and nq1 half Getting the Timing Right There are very few timing characteristics associated with this device; all are listed in [2], second page, AC Characteristics section. See Figure 5 for their representation in the Tau Library Editor. Since this device has two duplicate halves, we are able to bundle like pins to form a BusPort (of width 2) and then concern ourselves with just D, Q and nq. See Figure 3. The AC Characteristics [2] lists four different characteristics. The first is propagation delay (tplh). The Timing Links in Figure 5 are uniquely named so that Tau can track these separately. Each of the Timing Links is shown relative to another signal, the signal that the delay is measured against. In this case, D. Note that the values in Figure 5 for the Min Delay, and Max Delay are in ns, while the values listed in the data sheet are in ps. Other entries in AC Characteristics [2] include Skew (tskew), Output Rise/Fall Time (tr/tf) and Maximum Input Frequency (fmax). Modeling this device in Tau requires only two characteristics, that of propagation delay (tplh), and Skew (tskew). The other characteristics, although Figure 5: Cell Timing for MC100LVET22 PAGE 5

6 Figure 6: Delay Correlation for MC100LVET22 interesting, are not of concern for this Tau model. The Output Rise/Fall Time (tr/tf) describes how quickly the device switches from low to high, or high to low. This is invaluable information for a Signal Integrity analysis, but not used for timing analysis. The Maximum Input Frequency (fmax) is an equally interesting characteristic of the device, but does not lend itself for inclusion. One possible constraint that could be applied for this characteristic is the Period Constraint, the fastest period that can be defined for an input clock signal. This constraint is only applicable for clock nets, and is inappropriate in this example as the device does not have an input clock signal, it is asynchronous by definition. Propagation delay (tplh) is entered in the Cell Timing sheet, with a unique timing link name. The name of the links can be anything, but are generally chosen to match the data sheet so as not to be a source of confusion when verifying characteristics. The other characteristic of interest, Skew (tskew), is entered in the Delay Correlation sheet shown in Figure 6. The output pin numbers that need to be tracked are grouped together in a Correlation Class called "outputs". The value from the data sheet of 100ps is assigned. The skew that these outputs exhibit is relative to themselves, so the Relative-To Class is also set to "outputs". All other pins are placed in an unused Correlation Class named (by default) after the largest unused pin number, in this example 7. Figure 7: FSM Signals for MC100LVELT22 PAGE 6

7 Figure 8: FSM Behavior for MC100LVELT Modeling the Functionality As seen from the data sheet for the MC100LVELT22 [2], this device operates in one mode, and is asynchronous. With the timing characteristics specified correctly, the Tau Library Editor is able to create the FSM for this device. Utilizing the Cell>Create FSM from Timing command, the Tau Library Editor automatically creates the structure for the asynchronous FSM needed to represent the timing characteristics that are entered. The automation provided by the Tau Library Editor for the creation of FSMs alleviates the user from the task of creating these structures manually. Figures 7 and 8 show the FSM Signals and FSM Behaviour the Tau Library Editor creates from the Cell Timing Information. Normally the Output Value of Relevant Signals (Figure 8) is not of interest. Tau, a symbolic timing analysis tool, tracks timing, and potential timing conflicts. The actual value that is presented on an address, or other multiple bit bus is of no concern. The time when the address is valid, however, is of great interest. When FSMs are automatically generated a value placeholder ($Q, $nq) is used to represent the Output Values. A corresponding placeholder is created as a valid FSM Signal. Figures 7 and 8 show these placeholders. Relevant Signals (Figure 8) Q and nq follow the changes made by the Trigger Signal, D. The value of Q will always be the same as D, and the value of nq will always be the complement of D (!D). We can make this small modification to the FSM model created by the Tau Library Editor to reflect this relationship. This simple change is shown in Figure 9. The changes made to the behavior of this FSM, make it no longer necessary to define the internal placeholder signals $Q and $nq. Figure 9: Modified FSM Behavior for MC100LVELT22 PAGE 7

8 Figure 10: Modified FSM Signals for MC100LVELT22 Figure 11: Cell Structure for MPC931 PAGE 8

9 They are not used or required. The FSM Signals are edited to reflect this change. The modified FSM Signals sheet is shown in Figure 10. The model created now has a Cell with Timing characteristics, an FSM with functional Behavior, and a Delay Correlation for tracking skew on like output pins. When this asynchronous model is used within Tau, Tau will be able to track the propagation of the clock through this device, including the values of the true and complement signals Low Voltage PLL Clock Driver, MPC931 [3] This complex device lends itself to the modeling requirement of Tau. With a multitude of operating modes and different output frequencies for pin pairs, a first glance at this device would suggest the modeling requirement to be somewhat of a daunting task. Further investigation finds this not to be the case. Although the Cell Structure contains many pins we only need to track a small number of these to effectively construct the Tau Model for this device. See Figure Getting the Timing Right The characteristics for this device are listed in [3], page 5, AC Characteristics. This page lists the AC Characteristics for both the MPC930 and the MPC931. The MPC931 is the device of interest. Unlike a simple clock propagation device, this device has many timing characteristics to consider. Investigation of the way this device is used in the design is required to produce an accurate model. After studying [3], observe that this device derives three separate pairs of clock outputs from a differential PECL reference clock input. The frequencies of these output clock pairs are controlled by the values of the input pins Div_Sela, Div_Selb and Div_Selc (page 6, [3]). Also shown, are a number of low power configurations that alter output clock frequency. Although somewhat desirable, it is not within the scope of symbolic timing analysis to model this level of complex functionality for a clock device, as would be the case if using a functional simulator. What is important, is the translation through the device of these clock signals and visibility of the output frequencies. Within Tau, all clock signals inherit the frequency Figure 12: Cell Timing for MPC931 PAGE 9

10 assigned to the clock at the top of the clock tree. In this case, this is not sufficient. The clock at the input of the device is not the same as the clock seen at the outputs, by virtue of the functionality provided by the device itself. Tau is able to assign independent frequencies for all clock signals within a design. Propagation Delay, Clock Skew, and Phase Shifts are all tracked. To create a model for symbolic timing analysis with Tau, two AC Characteristics from [3], page 6, are important, tos (Output-to- Output Skew), and tpd (propagation delay). The device is modeled with the PECL_CLK input, different clock frequencies on the output clocks, operating at lt_100mhz. These choices are design specific. Figure 12 shows the Cell Timing to model this device. Timing Links for Qa0, Qa1 and Qb0 are shown. These are the same for Qb1, Qc0 and Qc1. Since Qa0 and Qa1 are similar signals, with the same timing characteristics, one may be tempted to group these and the other output pairs together. Looking at the functional part of this model, it is not desirable to have these signals grouped together to a BusPort of width more than one. Skew specifications are captured in the Delay Correlation sheet (Figure 13). The output pin numbers to be tracked are grouped together in a Correlation Class called "outputs". The value from the data sheet of 400ps is assigned. The skew that these outputs exhibit is relative to themselves, so the Relative-To Class is also set to "outputs". All other pins are placed in an unused Correlation Class named (by default) after the largest unused pin number, in this case Modeling the Functionality After eliminating the alternate and low power modes for this device, a simple to model asynchronous clock propagation device is left. Output frequencies are altered, but this is handled in Tau automatically, so considerations for this do not need to complicate the modeling effort. With the timing characteristics specified correctly, the Tau Library Editor is able to create the asynchronous FSM for this device. The Cell>Create FSM from Timing command within the Tau Library Editor automatically creates the structure for the asynchronous FSM needed to represent the timing characteristics that we have entered. Figures 14 and 15 show the FSM Signals and FSM Behavior created from the Cell Timing information. The structure of the FSM created by the Tau Library Editor is modified slightly to more accurately represent this device. The reason for keeping the output clock signals (Qa0, Qa1, Qb0 ) separate, was so assignment to a known value; that of PECL_CLK, is possible. PECL_CLK is a signal of width 1. The FSM automatically generated from the Timing Links contains placeholders for the Output Value of our Relevant Signals, as shown in Figure 15. These placeholders ($Qa0, $Qa1, $Qb0 ) are sufficient for Tau to perform a timing analysis for this device, but are not sufficient to propagate the clock tree analysis. The values of the clock outputs follow the value of the input clock PECL_CLK. By keeping the output clocks separate (signal width of 1), they can be assigned to PECL_CLK. If grouping of the output clocks had occurred, this mapping would not have been able possible; signals of width 2 (Qa0 and Qa1, for example), to PECL_CLK, signal width 1. A 1 to 1 mapping needs to be present to facilitate clock tree analysis through further devices. The changes made to the behaviour of this FSM make it no longer necessary to have the internal placeholder signals $Qa0, $Qa1, $Qb0 defined. We can edit the FSM Signals to reflect this change. The modified FSM Signals sheet is shown in Figure 17. The model created now has a Cell with Timing characteristics, an FSM with functional Behaviour, and a Delay Correlation for tracking Figure 13: Delay Correlation for MPC931, different clock frequencies l._100mhz PAGE 10

11 Figure 14: FSM Signals for MPC931 Figure 15: FSM Behavior for MPC931 PAGE 11

12 Figure 16: Modified FSM Behavior for MPC931 Figure 17: Modifed FSM Signals for MPC931 skew on like output pins. When this asynchronous model is used within Tau, Tau will be able to track the propagation of the clock through this device, including the values of the true and complement signals. 5.2 Modeling Synchronous Memory By its very nature, synchronous systems are very predictable to design with. In a synchronous system, the exact times at which any output can change states is determined by a signal commonly called a clock. Most digital systems are principally synchronous (although there are always some asynchronous parts), since synchronous circuits are easier to design and troubleshoot [1]. Synchronous memory devices ensure that a regular timing window that is predictable is always available Synchronous DRAM, 128Mb: x4, x8, x16 SDRAM, MT48LC8M16A2 [4] This somewhat intimidating data sheet [4], (with it's many functional modes, and timing diagrams) has the information required in one timing characteristic table. Any of the waveforms are useable to PAGE 12

13 Figure 18: Cell Structure for MT48LC8M16A2 gain better understanding of the timing characteristic in question. Many of the signals shown in Figure 18 have been bundled into BusPorts. This permits a more elegant modeling of functionality, particularly when many signals have the same characteristics. This is particularly true for address and data busses Getting the Timing Right The timing characteristics for this device listed in [4], page 33, Electrical Characteristics and Recommended AC Operating Conditions. Different timing requirements for different device speed grades are also listed. Capitalizing on the ease with which Tau Models support multiple device timing variations, all timing values for all speed grades available will be entered so that selection of the most suitable part may be made during timing verification. The AC Functional characteristics on page 34 concern themselves with a higher level of functionality than is appropriate for symbolic timing analysis. This table lists command and initialization characteristics that would only be verified with a fully functional simulator. A selection of Timing Links for the MT48LC8M16A2 are shown in Figure 19. Each of the speed grades available for the device is modeled. Some of the timing characteristics shown in [4], page 33, are combined. The Timing Link tas/tah is a setup and hold timing characteristic comprising of tas and tah. These two characteristics pertain to the same constraint in Tau, so their combination is a natural choice and requirement. Other timing characteristics are combined for the same reason Modeling the Functionality With the timing characteristics specified correctly, the Tau Library Editor is able to create the FSM for this synchronous device. Utilizing the Cell>Create FSM from Timing command, the Tau Library Editor automatically creates the structure for the synchronous FSMs needed to represent the timing characteristics that are entered. Figures 20 and 21 show the FSM Signals and FSM Behavior created automatically from the Cell Timing information. As with all synchronous devices, the FSMs that the Tau Library Editor generates are sufficient for analysis. Signal transitions always occur relative to a clock signal, so there is no need to modify the FSM that is automatically created. Figure 21 shows the internal placeholder $DQ_OUT used to track the timing for data output. 5.3 Modeling Asynchronous Memory Asynchronous memory relies exclusively on the transition of control signals to signify different operating modes. A clock signal is not present to synchronize timing, so timing characteristics are defined relative to the control signals themselves. An asynchronous PAGE 13

14 Figure 20: FSM Signals for MT48LC8M16A2 Figure 21: FSM Behavior for MT48LC8M16A2. PAGE 14

15 Figure 22: Cell Structure for IDT71256SA Figure 22: Cell Structure for IDT71256SA PAGE 15

16 Figure 24: FSM Signlas for IDT71256SA memory device will generally consist of a read cycle, a write cycle, and an idle state. As Tau models incorporate FSMs, this functionality is able to be modeled while verify the timing of these relative control signals CMOS Static RAM 256K (32K x 8), IDT71256SA [5] The Cell Structure for this asynchronous memory device from IDT can be seen in Figure 22. The address and data busses have been bundled into Busports Getting the Timing Right The constraints for this device are listed in [5], page 4, AC Electrical Characteristics. The timing requirements for the available device speeds are presented within the same table. Capitalizing on the ease with which Tau Models support multiple device timing variations, all timing values for all speed grades available will be entered so that selection of the most suitable part may be made during timing verification. Although the timing characteristics are specified in [5], page 4, the signals that these timing characteristics are relative to are specified graphically by timing waveforms, [5], pages 5 and 6. done by using the Cell>Create FSM from Structure command. The Tau Library Editor automatically creates the FSM Signals and FSM Behaviour. These are shown in Figures 24 and 25. The FSM Behaviour that is created is mostly empty. Completion of the FSM model will require additional work. Truth Table 3, of [5], page 2, lists the different functions that this device encounters as it cycles through its operating modes. The control signals that facilitate the change of modes for the device are the Conditions that we need to track as we develop the FSM for this device. As can be seen in Figure 26, the change from one state, to the next is controlled by the value of these control signals. A generic FSM, 32Kx8SRAM, is created to describe the functionality of this device. The FSM signal connections are defined in the Cell Structure sheet (Figure 22). Using generic functional models for a device permits a single FSM to be used for modeling devices that have the same functionality, but different timing. By specifying the current State, the Next State, and the signal Conditions that need to be met to transition to the Next State, detailed FSMs can be easily built that model the device behavior Modeling the Functionality This memory is a complex asynchronous device. The Tau Library Editor is unable to extract the functionality from timing, as was done for simple asynchronous devices, or for any synchronous device. Creating the structure for this complex asynchronous device can be PAGE 16

17 Figure 25: FSM Behavior for IDT71256SA Figure 25: FSM Behavior for IDT71256SA PAGE 17

18 7. Conclusion Symbolic timing analysis offers an elegant timing verification solution to board level designers without reporting the false timing paths of static timing analysis or requiring complex models and long runtimes required in functional simulations. The models used by Tau for symbolic timing analysis provide sufficient functionality to differentiate timing. Three common types of models have been explored: clock propagation devices for clock tree analysis, synchronous subsystems, and asynchronous subsystems. These models provide a sound foundation for the modeling of other similar devices. Board level designs do not need to have high frequency clocks in order to suffer from timing problems; all that is required is aggressive timing. Advanced FPGA technologies offer engineers many new design and timing alternatives. The exploration of these timing alternatives can be done in a controlled, repeatable manner with visibility to conservative timing variations by employing complete board timing verification solutions, as is available today through symbolic timing analysis with Tau. 8. References [1] Ronald J. Tocci, Digital Systems, Principles and Applications, Fourth Edition, Prentice Hall, 1988 [2] Motorola Semiconductor Technical Data, Dual LVTTL/LVCMOS to Differential LVPECL Translator, MC100LVELT22, [3] Motorola Semiconductor Technical Data, Low Voltage PLL Clock Driver, MPC931, [4] Micron Semiconductor Products, Inc, Synchronous DRAM, 128Mb: x4, x8, x16 SDRAM, MT48LC8M16A2, [5] IDT, CMOS Static RAM 256K (32K x 8), IDT71256SA, [6] Mentor Graphics Corporation, FSM Cookbook, Unpublished Proprietary Work, Available to Mentor Graphics Customers [7] Mentor Graphics Corporation, Board Level Timing Analysis Using Tau, A Mentor Graphics Training Workbook, v2.2, March 2000, Unpublished Proprietary Work, Available to Mentor Graphics Customers [8] Mentor Graphics Corporation, Tau Users Manual v2.2, Unpublished Proprietary Work, Available to Mentor Graphics Customers PAGE 18

19 For more information, call us or visit: R Copyright 2000 Mentor Graphics Corporation. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposed only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use of this information. Corporate Headquarters Mentor Graphics Corporation 8005 S.W. Boeckman Road Wilsonville, Oregon USA Phone: North American Support Center Phone: Fax: Silicon Valley Headquarters Mentor Graphics Corporation 1001 Ridder Park Drive San Jose, California USA Phone: Fax: Europe Headquarters Mentor Graphics Corporation Immeuble le Pasteur 13/15, rue Jeanne Braconnier Meudon La Forêt France Phone: 33-(0) Fax: 33-(0) Pacific Rim Headquarters Mentor Graphics (Taiwan) Room 1603, 16F, International Trade Building No. 333, Section 1, Keelung Road Taipei, Taiwan, ROC Phone: Fax: Japan Headquarters Mentor Graphics Japan Co., Ltd. Gotenyama Hills 7-35, Kita-Shinagawa 4-chome Shinagawa-Ku, Tokyo 140 Japan Phone: Fax: PAGE 19