High Density Packaging User Group International

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1 High Density Packaging User Group International Flip Chip Package Reliability Characterization Project: Temperature Cycling Tests Final Report Holly Rubin, Project Leader Lucent Technologies, Princeton, NJ 27 July 2001 HDP User Group International, Inc. International Headquarters North Scottsdale Road, Suite B, Scottsdale, AZ European Office Langbrodalsvagen 73, S Alvsjo, Sweden 1

2 Disclaimer No part of the information in this document can be redistributed, copied, or reproduced without prior written consent of HDP User Group International, Inc. Warranties THIS INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. REFERENCES TO CORPORATIONS, THEIR SERVICES AND PRODUCTS, ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED. IN NO EVENT SHALL HDP USER GROUP INTERNATIONAL, INC BE LIABLE FOR ANY SPECIAL, INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS INFORMATION. Descriptions of, or references to, products, services or publications within this document does not imply endorsement of that product, service or publication. HDP User Group International, Inc. makes no warranty of any kind with respect to the subject matter included herein, the products listed herein, or the completeness or accuracy of the information. HDP User Group International, Inc. specifically disclaims all warranties, express, implied or otherwise, including without limitation, all warranties of merchantability and fitness for a particular purpose. THIS PUBLICATION COULD INCLUDE TECHNICAL INACCURACIES OR TYPOGRAPHICAL ERRORS. CHANGES MAY BE PERIODICALLY MADE TO THE INFORMATION HEREIN. 2

3 Flip Chip Package Reliability Characterization Project: Temperature Cycling Tests Abstract A study was undertaken to determine the 2nd level attachment reliability of various flip chip packages, ranging in I/O from small 48 I/O CSP packages to large, 1140 I/O plastic ball grid arrays (BGAs) and 1567 ceramic column grid arrays (CCGAs). Temperature cycling, 0 to 100 C, was carried out to 8197 cycles. Early failures, a failure in the cycling chamber, and delaying failure mode analysis (FMA) until packages had been subject to several thousand thermal cycles make it difficult to assign root cause of failure. The Flip Chip Package Reliability Characterization team carried out this work as part of the Flip Chip Package Characterization Project of the High Density Packaging (HDP) Users Group. Acknowledgments Bill Marcus (Abpac) for board design and Matt Kaufmann (HP) for his assistance in scoping out the initial design Gregg Croteau (Sanmina) for design documentation Laurene Yip and Sanjay Dandia (VLSI), Ahmer Syed (Amkor), Irv Memis (IBM), Bob Marrs and Ron Molnar (Abpac) for providing packages for testing Charles Ma, Sundar Kamath, Kishan Patel (Sanmina) for board assembly George Dudnikov, Heather Duncan (Sanmina) for board fabrication Chung Lam and Yuk Yu (Sun Microsystems) and Steve Iketani (Sanmina) conducted failure analyses Sam Dai, Carlos Avila (HP), David Love (Sun Microsystems), Joe Smetana (Alcatel), Theo Ejim, Guy Lynott, Jack Morris (Lucent), and George Dudnikov (Sanmina) for all their support and technical advice Trace Laboratories was funded by HDP User Group to perform the temperature cycling, thanks to Dave Ashcraft and Jeff Schutt for the periodic updates and the final report Project Team David Towne, David Love (Sun Microsystems), Carlos Avila, Sam Dai (HP), Holly Rubin, Jack Morris (Lucent), George Dudnikov (Sanmina), Joe Smetana (Alcatel), Paul Collander (Nokia), Irv Memis (IBM), Arne Tolvgard (Ericsson) 3

4 Table of Contents 1. Introduction 2. PCB Design and Construction 3. Assembly 4. Thermal Cycling 5. Results and Discussion 4

5 1. Introduction This work was performed as one of the research projects of the HDP Users Group, a consortium of electronic companies. The HDP User Group charter is to reduce the time to market for the Telecommunications and Computer industries by improving cooperation between system integrators and their suppliers in the packaging design process. The objective of this study was to compare various flip chip package constructions with respect to solder joint integrity. This was not an attempt to "qualify" any of the included components, but rather an experiment to assess the 2nd level reliability of packages that use flip chip construction. With one exception, there was no monitored connection to the silicon chips in the package. Therefore, only the 2nd level solder joint connection was monitored. Two control components, (a 256 I/O wire bonded BGA and a 481/0 TSOP), the reliability of which are established and were used in the HDP Chip Scale Package (CSP) Reliability Characterization Program, were included. Package details are outlined in Table 1. Table 1. Package Details, FC=Flip Chip 2. PCB Design and Construction The printed circuit board (PCB) was designed to include four of each component per board. We had to use parts as supplied by the vendors, and thus make use of whatever daisy chain existed in their parts. The number of electrical loops for each component is included in Table 2 below. For the 1140 FCBGA, the daisy chain includes both 1st and 2nd level interconnections; for the remaining parts, only 2nd level attachment was monitored. Table 2 also includes the ID used by Trace Laboratories during temperature cycling and a notation indicating whether the chains monitor balls near the periphery (outer) or center (inner) of the device. Note that the board includes sites for 2 components (a 2561/0 FC-BGA and a 28 I/O FC-CSP) that were never assembled due to lack of availability. Because it was felt that many of the higher I/O parts would require via-in-pad (VIP) technology when used in real applications, half the sites for each component were VIP. 5

6 Identification of VIP locations is also included in Table 2. PWBs were fabricated using resin-coated copper (RCC), an unreinforced dielectric. All boards were 6 layers, 0.062" thick, with an OSP finish. Component mounting pads were designed to have 1:1 diameter ratios with the pads on the respective packages and were non-solder mask defined (NSMD). 3. Assembly Assembly was performed at an assembly subcontractor using Alpha Metal UP78 no clean paste. A 6-mil stencil thickness was used except for a step-up to 8 mils at the CCGA sites. Stencil aperture details are shown in Table 3. The reflow profile used is shown in Fig 1. A photograph of the assembled board is shown in Fig 2. Table 2. Component ID, number of daisy chains, VIP information 6

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8 Table 3. Aperture details Component U01: CCGA1657 U02:FC1140 U03: FC256 U04: BGA 256 U05: FC 280 U06: TSOP48 U07:FC119 U08: FC64 U09: FC48 Aperture 30 MIL ROUND 20 MIL ROUND 30 MIL ROUND 30 MIL ROUND 17.3 MIL ROUND 10X54 RECT. 30 MIL ROUND 17.3 MIL ROUND 17.3 MIL ROUND After assembly, all boards were x-rayed and electrically probed by the assembly subcontractor. As verbally communicated by them, no anomalies were seen in the x-ray images. Results of the initial probing gave resistances in the range indicated in Table 4 for each component type. Table 4. Resistance by component 4. Thermal Cycling Eight boards underwent thermal cycling. Testing was done at Trace Labs. Prior to testing, Trace provided temperature maps of the chamber. Trace Labs also provided a final report (Thermal Cycling with in-situ Event Detection Continuity Monitoring, No ). Anatech detection monitors were used to continuously monitor resistance during the test. A 0 C to 100 C, 20 minute cycle was used. The cycling profile used for the first 3799 cycles is in Fig 3. At 3799 cycles the chamber malfunctioned. Boards saw five cycles which below -50 C (cycles 3741 to 3745) at which point the problem was noticed, the chamber shut down, and a valve replaced. Cycles from 3745 to 3798 were OK, but some glitches were seen in the temperatures so Trace made the decision to shut down the chamber and overhaul it. The thermal profile for the remainder of the test is shown in Fig 4. Test was re-started after 7-8 weeks. 8

9 5. Results of Discussion: Interpretation of the FMA results that will be presented, along with identification of root cause of failure, is complicated by several factors: The failure of the cycling chamber could have caused boards to see temperatures as low as liquid nitrogen, causing damage to boards and components. Prior to FMA, all boards have seen many thousands of cycles. Any cracking observed in components and boards could be due to extended cycling. No information is available allowing us to pinpoint the location of initial failure. There were several instances where a failure as detected on the Anatechs could not be reproduced with a manual probe, so the initial failure reading could have been in error, with cracks causing the failure to occur at a later time than the equipment measured. The assembly subcontractor is to be commended for the reflow profile they developed. Although times above liquidus temperature may not have been adequate for all components, especially the CCGA, it was a challenge to optimize the assembly parameters (reflow temperatures/time above liquidus/etc) due to the wide range of package types used on the board. HDP User Group teams should keep this issue in mind as future test vehicles are designed. Raw failure data is included in Appendix A. Failures by component are shown in Figure 5. Weibull plots are provided in Figures 6-9. A dashed line on the plots indicates cycle 3799 (chamber failure). The control components (256 I/O BGA and TSOP) failed at a higher rate than seen previously on RCC boards (both the BGA and the TSOP had one failure through 6600 cycles in the CSP program on an RCC board. It is important to keep in mind that optimization of assembly parameters was much more difficult on the FC-BGA board than on the CSP board, and assembly-related issues could result in early failures). The Weibull plots for the majority of the components appear to have a single slope, indicating a single failure mode (Fig 6). However, the Weibull plots for two of the components, FC48 and 1140, Figure 7, exhibit multiple slopes. Weibull software confirmed this. The 1140 data appears to divide into early fails (<1000 cycles) and failures after 1000 cycles (see Fig 8). With the 48 I/O part, failures of the VIP sites occurred prior to the non-vip sites. If the data is split between VIP and non-vip sites, the non-vip has good correlation, but not the VIP (see Fig 9). The data also does not correlate well to component location or early vs. late fails. The low temperature exposures around 3799 cycles could have induced new failure modes, but there did not appear to be a correlation when the data was examined for fails before and after chamber failure (3799 cycles). There is additional evidence suggesting that the chamber malfunction and low temperature excursion did not induce a new failure mode. For the VLSI component, there are clearly two slopes for failures prior to 1000 cycles and failures after 1000 cycles (see Fig 8). For this component, no effect of the thermal excursion is evident in the Weibull plots. The FC64, VLSI, control BGA, and 119 show no obvious changes in slope from before the event to after the event either. For the TSOP, other than one early fail prior to 100 cycles, all failures were subsequent to the chamber event, so it is impossible to determine if the event precipitated failures. However, the TSOP data is in line with previous TSOP data, again indicating no adverse effect from the excursion. For the FC48, non-vip failures 9

10 occurring prior to the thermal excursion fall on the same slope as those subsequent to the failure, again indicating that the chamber failure did not precipitate a change in failure mode. In an attempt to understand failure modes, FMA was performed. 2561/0 BGAs that failed at 2208 and 5981 cycles were examined. Both parts were on VIP sites. In one case via cracks were observed (see Fig 10a). These via cracks appear to be associated with radial cracks in the unsupported RCC dielectric (Fig 10b). The other part came off the board, with the board pads remaining on the component solder pads, leaving the signal traces and vias exposed. This supports failure at the microvia. We cannot ascertain if the via cracking is the root cause of failure. For the reasons stated at the beginning of this section (low temperature excursion, extended cycling times, inability to pinpoint location of initial failure), the FMA cannot clearly indicate root cause of failure. The radial cracking of the RCC resin mentioned above was seen at all sites. Figure 11 shows cracking seen around the balls of the 119 I/O device. Figure 12 shows cracking seen around the pads of the 256 I/O BGA that came off the board. The short vertical cracks near the pads and the long crack between pads were also seen on the samples where the part remained attached to the board. As stated, it is unknown whether these cracks have any relation to the failures. RCC boards used in the HDP User Group CSP reliability characterization program showed cracking, but it did not cause failures. Reliability of unsupported RCC boards may be an area that HDP User Group should further investigate. CCGA failures were attributed to cracking of the solder column (Fig 13). The 119, 256, 48, and 641/0 parts that were examined all showed signs of radial cracking in the PCB epoxy around the failed solder balls. On non-vip parts (the 119, 48, and 641/0 packages), CSAM showed delamination at the solder-pad interface (one example shown in Fig 14). This is another unexpected failure mode and it is impossible to assign a root cause, other than the general conclusion that it can be due to a board, assembly, or component issue. Further examination of the 1191/0 part showed evidence of die cracking and resin cracking in the package substrate (Fig 15), although there was no evidence of the resin cracking causing a break in any of the copper traces. However, the fact that there was so much damage in the package, especially to the silicon die, indicates the possibility of the package being overstressed. Data was also analyzed to see if component position (distance from the center of the PWB) might have played a role in the failure distributions. The CCGA component was the only component for which an effect might have been seen - Ul 1, the component closes to the center of the board, started failing later than the other three CCGA components. No differences were seen among the remaining parts (other three CCGA positions or other components). In conclusion, with the exception of the CCGA, there is no evidence of solder fatigue in the limited number of samples examined. There is evidence of via cracking in failed parts on VIP sites, and delamination between the solder balls and the copper pads for failed parts on non-vip sties. However, since boards were not removed as failures occurred, one cannot determine whether the cracking occurred through extended cycling (time or temperature) or where in the part initial failure actually occurred (since probing 10

11 wasn t done until the boards were removed for FMA). Therefore, the areas sectioned may not be the actual locus for initial failures and may thus not be showing the true root cause. For this reason, the team strongly urges HDP to design experiments to allow early FMA to occur (which means designing boards to allow removal of boards/components for FMA immediately after failure and assembling enough test vehicles to still maintain statistical integrity of final results). Additionally, the team recommends designers of future test vehicles carefully consider the use of packages of widely disparate sizes and thermal mass so as to reduce the chance of assembly related defects and early failures. Supporting Documentation The following supporting documentation is available (with a password) on the HDP User Group Member Website at Failure analysis reports: Board 3- Sun FA Report #C20028, 9/21/00 Board 3 - Sun FA Report # C20027,9/13/00 Board 3, Defect Analysis for HDP User Group BGA test board, 2/21/00 - Sanmina Board 2 - Sun FA Report #C20104,2/13/01 FEM presentations: Flip-Chip Package Characterization: Finite Element Modeling, Flip-Chip Package Characterization: FE Modeling and Moire Results 11