EE382V-ICS: System-on-a-Chip (SoC) Design

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1 EE38V-CS: System-on-a-Chip (SoC) Design Hardware Synthesis and Architectures Source: D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Chapter 6: Hardware Synthesis, Springer, 9. Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin Outline Design flow RTL architecture nput specification Specification profiling RTL synthesis Variable merging (Storage sharing) Operation Merging (FU sharing) Connection Merging (Bus sharing) Chaining and multi-cycling Data and control pipelining Scheduling Component interfacing Conclusions EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner

2 Hardware Synthesis Design Flow Compilation Estimation HLS Model generation RTL synthesis Logic synthesis Layout RTL Component Library Specification Compilation Tool Model Estimation HLS Allocation Binding Scheduling Model Generation RTL Model RTL Tools... EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 3 Hardware Synthesis Design flow RTL architecture nput specification Specification profiling RTL synthesis Variable merging (Storage sharing) Operation Merging (FU sharing) Connection Merging (Bus sharing) Chaining and multi-cycling Data and control pipelining Scheduling Component interfacing Conclusions EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 4

3 RTL Processor Architecture ler FSM controller Programmable controller Datapath components Storage components Functional units Connection components Pipelining Functional unit Datapath Structure Chaining Multicycling Forwarding Branch prediction Caching EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 5 RTL Processor with FSM ler Simple architecture Small number of states nputs Data nputs Output Logic Signals B B RF nput Logic Status Signals ALU MUL Memory FSM ler Outputs B3 Datapath Data Outputs EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 6 3

4 RTL with Programmable Complex architecture and datapath pipelining Advanced structural features Large number of states (CW or S) nputs Data nputs PC Cmem or PMem R or CWR Signals B B RF Offset AG Status Address SR ALU MUL Memory Programmable ler B3 Datapath Outputs Data nputs EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 7 Outline Design flow RTL architecture nput specification Specification profiling RTL synthesis Variable merging (Storage sharing) Operation Merging (FU sharing) Connection Merging (Bus sharing) Chaining and multi-cycling Data and control pipelining Scheduling Component interfacing Conclusions EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 8 4

5 nput Specification Programming language (C/C, ) Programming semantics requires pre-synthesis optimization System description language (SystemC, ) Simulation semantics requires pre-synthesis optimization /Data flow graph (CDFG) CDFG generation requires dependence analysis Finite state machine with data (FSMD) State interpretation requires some kind of scheduling RTL netlist RTL design that requires only input and output logic synthesis Hardware description language (Verilog / VHDL) HDL description requires RTL library and logic synthesis EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 9 C Code for Ones Counter Programming language semantics Sequential execution, Coding style to minimize coding HW design Parallel execution, Communication through signals : int OnesCounter(int Data){ : int Ocount = ; 3: int Temp, Mask = ; 4: while (Data > ) { 5: Temp = Data & Mask; 6 Ocount = Data Temp; 7: Data >>= ; 8: } 9: return Ocount; : } Function-based C code : while() { : while (Start == ); 3: Done = ; 4: Data = nput; 5: Ocount = ; 6: Mask = ; 7: while (Data>) { 8: Temp = Data & Mask; 9: Ocount = Ocount Temp; : Data >>= ; : } : Output = Ocount; 3: Done = ; 4: } RTL-based C code EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 5

6 CDFG for Ones Counter /Data flow graph Resembles programming language Loops, ifs, basic blocks (BBs) Explicit dependencies dependences between BBs Data dependences inside BBs Missing dependencies between BBs Start nput Data Mask Ocount Done Data Mask Ocount Done & >> Data Ocount Done Data > Output Done EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner FSMD for Ones Counter FSMD more detailed then CDFG States may represent clock cycles Conditionals and statements executed concurrently All statement in each state executed concurrently signal and variable assignments executed concurrently FSMD includes scheduling FSMD doesn't specify binding or connectivity EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 6

7 CDFG and FSMD for Ones Counter EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 3 RTL Specification for Ones Counter RTL Specification ler and datapath netlist nput and output tables for logic synthesis RTL library needed for netlist Present State S S S nputs: Start Data = nput logic table Next State S S S Output: Done Output logic table Start nport State RF Read Port A RF Read Port B ALU Shifter RF selector RF Write Outport S Z Output Logic Signals RF S RF[] RF[] subtract pass nport B3 RF[] RF[] Z Z B B RF[] increment pass B3 RF[] Z nput Logic status ALU Shifter RF[] RF[] RF[] RF[3] AND add pass pass B3 B3 RF[3] RF[] Z Z FSM ler Done B3 Datapath Outport RF[] RF[] pass shift right B3 RF[] disable Z enable RF[] = Data, RF[] = Mask, RF[] = Ocount, RF[3] = Temp EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 4 7

8 HDL description of Ones Counter HDL description Same as RTL description Several levels of abstraction Variable binding to storage Operation binding to FUs Transfer binding to connections Netlist must be synthesized Partial HLS may be needed : // : always@(posedge clk) 3: begin : output_logic 4: case (state) 5: // 6: : begin 7: B = RF[]; 8: B = RF[]; 9: B3 = alu(b, B, l_and); : RF[3] = B3; : next_state = ; : end 3: // 4: : begin 5: B = RF[]; 6: Outport <= B; 7: done <= ; 8: next_state = S; 9: end : endcase : end : endmodule EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 5 Outline Design flow RTL architecture nput specification Specification profiling RTL synthesis Variable merging (Storage sharing) Operation Merging (FU sharing) Connection Merging (Bus sharing) Chaining and multi-cycling Data and control pipelining Scheduling Component interfacing Conclusions EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 6 8

9 Profiling and Estimation Pre-synthesis optimization Preliminary scheduling Simple scheduling algorithm Profiling Operation usage Variable life-times Connection usage Estimation Performance Cost Power EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 7 Square-Root Algorithm (SRA) SQR = ((.875x.5y), x) x = ( a, b ) y= min ( a, b ) S a = n b = n Start S t = a t = b x = ( t, t ) y = min ( t, t ) t3 = x >> 3 t4 = y >> t5 = x t3 t6 = t4 t5 t7 = ( t6, x ) Done = Out = t7 EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 8 9

10 Variable and Operation Usage S Variable usage a b t t x y t3 t4 t5 t6 t7 No. of live variables 3 3 S a = n b = n Start S t = a t = b x = ( t, t ) y = min ( t, t ) t3 = x >> 3 t4 = y >> t5 = x t3 abs min >> - No. of operations S Max. no. of units Operation usage t6 = t4 t5 t7 = ( t6, x ) Done = Out = t7 EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 9 Connectivity usage S Max. no. of units Operation usage abs min >> - No. of operations S S a = n b = n Start t = a t = b x = ( t, t ) y = min ( t, t ) t3 = x >> 3 t4 = y >> a b t t x y t3 t4 t5 t6 t7 Connectivity usage t5 = x t3 abs O abs O t6 = t4 t5 min >>3 >> O O O O O t7 = ( t6, x ) Done = Out = t7 - O O EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner

11 Outline Design flow RTL architecture nput specification Specification profiling RTL synthesis Variable merging (Storage sharing) Operation Merging (FU sharing) Connection Merging (Bus sharing) Chaining and multi-cycling Data and control pipelining Scheduling Component interfacing Conclusions EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner Datapath Synthesis Variable Merging (Storage Sharing) Operation Merging (FU Sharing) Connection Merging (Bus Sharing) Register merging (RF sharing) Chaining and Multi-Cycling Data and Pipelining EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner

12 Register Sharing Register sharing Grouping variables with non-overlapping lifetimes Sharing reduces connectivity cost a c b d a, c b, d x y x, y Partial FSMD Datapath without register sharing Datapath with register sharing EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 3 General Partitioning Algorithm Compatibility graph Compatibility: Non-overlapping in time Not using the same resource Non-compatible: Overlapping in time Using the same resource Priority Critical path Same source, same destination no Start Create compatibility graph Merge highest priority nodes Upgrade compatibility graph All nodes incompatible yes Stop EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 4

13 / Variable Merging for SRA / / / (a) nitial compatibility graph (b) Compatibility graph after merging t3, t5, and t6 (c) Compatibility graph after merging t, x, and t7 (d) Compatibility graph after merging t and y R = [ a, t, x, t7 ] R = [ b, t, y, t3, t5, t6 ] R3 = [ t4 ] (e) Final compatibility graph (f) Final register assignments EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 5 Datapath with Shared Registers Variables combined into registers One functional unit for each operation R R R3 a b min - >> >>3 EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 6 3

14 Functional Unit Sharing Functional unit sharing Smaller number of FUs Larger connectivity cost Si x = a b a c b d Sj y = c d /- x y Partial FSMD Non-shared design Shared design EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 7 Operation Merging for SRA / a / / b / / a / / b / / / min / / / / / / / - min / / / / - nitial compatibility graph Compatibility graph after merging of and - Compatibility graph after merging of min,, and - Final graph partitions EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 8 4

15 Datapath with Shared Registers and FUs Variables combined into registers Operations combined into functional units R R R3 abs/ abs/min//- >> >>3 EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 9 Connection Usage for SRA S a = n b = n Start S t = a t = b x = ( t, t ) y = min ( t, t ) t3 = x >> 3 t4 = y >> t5 = x t3 t6 = t4 t5 t7 = ( t6, x ) Done = Out = t7 Find compatible connections for merging into buses A B C D E F G H J K L M N Connection usage table S S EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 3 5

16 Connection Merging for SRA Combine connection not used at the same time Priority to same source, same destination Priority to imum groups M K S S A B C D E F G H J K L M N Compatibility graph for input buses Bus assignment J L N Compatibility graph for output buses EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 3 Datapath with Shared Registers, FUs, Buses Minimal SRA architecture 3 registers 4 () functional units 4 buses EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 3 6

17 Register Merging into RFs Register merging: Port sharing Merge registers with non-overlapping access times No of ports is equal to simultaneous read/write accesses Register assignment S a = n b = n Start S t = a t = b x = ( t, t ) y = min ( t, t ) t3 = x >> 3 t4 = y >> t5 = x t3 R R S S t6 = t4 t5 R t7 = ( t6, x ) R3 R R3 Done = Out = t7 Compatibility graph Register access table EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 33 Datapath with Shared RF RF minimize connectivity cost by sharing ports n n R R3 R Bus Bus abs/ abs/min//- H >>3 >> Bus3 Bus4 Out EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 34 7

18 Outline Design flow RTL architecture nput specification Specification profiling RTL synthesis Variable merging (Storage sharing) Operation Merging (FU sharing) Connection Merging (Bus sharing) Chaining and multi-cycling Data and control pipelining Scheduling Component interfacing Conclusions EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 35 Datapath with Chaining Chaining connects two or more FUs Allows execution of two or more operation in a single clock cycle mproves performance at no cost S a = n b = n Start = S t = a t = b x = ( t, t ) t3 = ( t, t )>>3 t4 = min ( t, t )>> t5 = x t3 t6 = t4 t5 t7 = ( t6, x ) Done = n Out = t7 EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 36 8

19 Datapath with Chaining and Multi-Cycling Multi-cycling S S a = n b = n Start t = a t = b Operations that take more than one cycle Allows use of slower FUs Allows faster clock-cycle n n x = ( t, t ) t3 = ( t, t )>>3 [t4]= min ( t, t )>> R R R3 t5 = x t3 t4 = [min ( t, t ) >>] Bus Bus t6 = t4 t5 abs/ abs//- min t7 = ( t6, x ) Done = n Out = t7 Bus 3 >>3 >> Bus 4 Out EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 37 Outline Design flow RTL architecture nput specification Specification profiling RTL synthesis Variable merging (Storage sharing) Operation Merging (FU sharing) Connection Merging (Bus sharing) Chaining and multi-cycling Data and control pipelining Scheduling Component interfacing Conclusions EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 38 9

20 Pipelining Functional Unit pipelining Two or more operation executing at the same time Datapath pipelining Two or more register transfers executing at the same time Pipelining Two or more instructions generated at the same time EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 39 Functional Unit Pipelining () S S a = n b = n Start t = a t = b Operation delay cut in half Shorter clock cycle Dependencies may delay some states Extra NO states reduce performance gain x = ( t, t ) t3 = ( t, t )>>3 t4 = min( t, t )>> t5 = x t3 t6 = t4 t5 t7 = ( t6, x ) S8 Done = n Out = t7 EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 4

21 Functional Unit Pipelining () S a = n b = n Start S t = a t = b x = ( t, t ) t3 = ( t, t )>>3 t4 = min( t, t )>> Timing diagram with 4 additional NO states S S NO NO NO NO S8 t5 = x t3 t6 = t4 t5 Read R Read R Read R3 ALU stage ALU stage a a b b a b t t t t t3 min - min - t5 t4 t6 t7 t7 = ( t6, x ) S8 Done = n Out = t7 Shifters Write R Write R Write R3 Write Out a b t t t3 >>3 t4 >> t5 t6 t7 t7 EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 4 Datapath Pipelining () Register-to-register delay cut in equal parts Much shorter clock cycle Dependencies may delay some states Extra NO states reduce performance gain n n R R R3 Bus Bus ALU >>3 >> Bus3 Bus4 Out EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 4

22 Datapath pipelining () n n S a = n b = n Bus Bus R R R3 Start ALU S t = a Bus3 >>3 >> Bus4 t = b Out x = ( t, t ) t3 = ( t, t )>>3 t4 = min( t, t )>> t5 = x t3 t6 = t4 t5 Timing diagram with additional NO clock cycles Cycles Read R a t t Read R b t t Read R3 ALUn(L) a t t 8 9 x t3 x t5 t4 t4 ALUn(R) b t t t3 t5 ALUOut a b min x t6 x t6 8 t7 t7 = ( t6, x ) Shifters >>3 >> S8 Done = n Out = t7 Write R Write R Write R3 a b t t x t3 t4 t5 t6 t7 Write Out t7 EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 43 Datapath and Pipelining () Fetch delay cut into several parts Shorter clock cycle Conditionals may delay some states Extra NO states reduce performance gain nputs Data nputs signals S PC CMem CWR Register RF Mem a>b x = c d AG Offset Status Signals ALU / Bus Bus y = x - ler SR Outputs Register Data Outputs Bus3 Datapath EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 44

23 Data and Pipelining () nputs signals Data nputs 3 NOP cycles for the branch NOP cycles for data dependence PC AG CMem Offset CWR Status Signals SR Register ALU RF Mem / Bus Bus Bus3 ler Outputs Timing diagram with additional NO clock cycles Register Data Outputs Datapath S Cycle Operation Read PC a>b Read CWR Read RF(L) S a NO NO NO c NO NO x x = c d Read RF(R) Write ALUn(L) Write ALUn(R) Write ALUOut b a b d c d cd x x- y = x - Write RF x y Write SR a>b Write PC 3 4/ EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 45 Hardware Synthesis Design flow RTL architecture nput specification Specification profiling RTL synthesis Variable merging (Storage sharing) Operation Merging (FU sharing) Connection Merging (Bus sharing) Chaining and multi-cycling Data and control pipelining Scheduling Component interfacing Conclusions EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 46 3

24 Scheduling Scheduling assigns clock cycles to register transfers Non-constrained scheduling ASAP scheduling ALAP scheduling Constrained scheduling Resource constrained (RC) scheduling Given resources, minimize metrics (time, power, ) Time constrained (TC) scheduling Given time, minimize resources (FUs, storage, connections) EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 47 C and CDFG for SRA Algorithm a=n b=n Start t= a t= b x=(t,t) y=min(t,t) t3=x>>3 t4=y>> t5=x-t3 t6=t4t5 t7=(t6,x) Done= Out=t7 n n a b Start a b a b min >> >>3 - Out Done C flowchart CDFG EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 48 4

25 RC Scheduling ASAP schedule ALAP schedule Ready list with mobilities (ALAP ASAP) RC schedule (for single FU and shifters) EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 49 Scheduling Algorithms RC algorithm TC algorithm EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 5 5

26 TC Scheduling a b a b a b S a b a min - a b b >> >>3 - min >>3 min >>3 >> - >> - S8 Out ASAP Out ALAP Out TC schedule EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 5 Distribution Graphs for TC scheduling AU units Probability sum/state Shift units AU units Probability sum/state Shift units S a b. S a b. min min >> >> >>3. >> nitial probability distribution graph Graph after,, and were scheduled EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 5 6

27 Distribution Graphs for TC scheduling AU units Probability sum/state Shift units AU units Probability sum/state Shift units S a b. S a.. b... min. >>3. min. >>3. -. >>. -. >>..... Graph after,, -, min, >>3, and >> were scheduled Distribution graph for final schedule EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 53 Hardware Synthesis Design flow RTL architecture nput specification Specification profiling RTL synthesis Variable merging (Storage sharing) Operation Merging (FU sharing) Connection Merging (Bus sharing) Chaining and multi-cycling Data and control pipelining Scheduling Component interfacing Conclusions EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 54 7

28 nterface Synthesis Combine process and channel codes HW and protocol clock cycles may differ nsert a bus-interface component Communication in three parts: Freely schedulable code Scheduled with process code Schedule constrained code MAC driver for selected bus interface Bus interface mplemented by bus interface component from library EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 55 Bus nterface ler () ler Datapath CMem signals Reg RF Mem Bus offset Bus AG Status signals ALU / Bus 3 Bus 4 ready ack OutCntrl OutAddr OutData ndata nput logic Output logic signals Address NC Write Queue Read Queue MAC driver REQUEST GRANT CONTROL ADDRESS DATA EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 56 8

29 Bus nterface ler () ler Datapath CMem signals S ready = Reg RF Mem Bus ready = offset Bus OutAddr = BusAddr AG Status signals ALU / ready = OutData = BusData OutCntrl = WRTE_WORD ack = ready = ack = Bus 3 Bus 4 ready ack OutCntrl OutAddr OutData ndata signals Output logic Write Read Queue Queue nput Address logic NC MAC driver REQUEST GRANT CONTROL ADDRESS DATA Bus protocol EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 57 Transducer/ Bridge Translates one protocol into another ler receives data with protocol and writes into queue ler reads from queue and sends data with protocol PE Bus Bus Transducer PE nterrupt Ready Ack nterrupt Processor <clk> ler <clk> Ready Ack ler <clk> Processor <clk> Data Data Memory Queue <clk3> Memory EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 58 9

30 Conclusions Synthesis techniques Variable Merging (Storage Sharing) Operation Merging (FU Sharing) Connection Merging (Bus Sharing) Architecture techniques Chaining and Multi-Cycling Data and Pipelining Forwarding and Caching Scheduling Metric constrained scheduling nterfacing Part of HW component Bus interface unit f too complex, use partial order EE38V-CS: SoC Design 9 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 59 3

EE382V: Embedded System Design and Modeling

EE382V: Embedded System Design and - Introduction Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu : Outline Introduction Embedded systems System-level