Advanced Digital Logic Design

Transcription

1 \ / Advanced Digital Logic Design Using VHDL, State Machines, and Synthesis for FPGAs Sunggu Lee С ENGAGE 1% Learning" Australia Canada Mexico Singapore Spain United Kingdom United States

2 Ф Ф ФФтшш»» ' 1 Condensed Overview of Introductory Digital Logic Design Number Formats Combinational Logic Combinational Logic Devices Combinational Logic Circuit Design Sequential Logic Sequential Logic Devices Synchronous Sequential Circuit Design Hazards and Glitches Metastability Resources Bibliography Problems 28 2 Digital Logic Design Using Hardware Description Languages Hardware Description Languages Design Flow Synthesis Register Transfer Level Notation Logic Simulation Properties of Actual Circuits Chapter Review Resources Bibliography Problems 43 3 Introduction to VHDL and Test Benches VHDL Basics Entity and Architecture Signals, Data Types, Constants, and Operators Libraries and Packages Structural and Behavioral Descriptions Testing and The Test Bench Manufacturing Testing Functional Testing Test Benches VHDL Test Bench More Advanced VHDL Concepts Concurrent and Sequential VHDL Variables and Signals Delay Modeling Attributes Procedures and Functions Generics and Modeling a Bidirectional Bus Construction of Complete VHDL Programs Combinational Logic Circuits Sequential Logic Circuits Behavioral Modeling of More Complex Circuits Chapter Review Resources Bibliography Problems 122 ф ф # # is # * #» *.»» 4 High-Level VHDL Coding for Synthesis Register-Transfer Level Notation 126

3 VI 4.2 Combinational Logic Synthesis Using Concurrent Signal Assignment Statements for Combinational Logic Using Process Blocks for Combinational Logic Complex Combinational Logic Code Sequential Logic Synthesis Using Process Blocks for Sequential Logic Synthesis Synthesis Heuristics Synthesis using A Commercial Tool High-Level VHDL Coding Chapter Review Resources Bibliography Problems 169 Ш 9 # 5 State Machine Design Manual State Machine Design Pseudocode RTL Program Datapath State Diagram Control Logic State Machine Design using ASM Charts Automatic Synthesis-Based State Machine Design Automatic Synthesis-Based Design Procedure Algorithm to HDL Code Conversion Design: Vending Machine Automatic State Machine Design for a Vending Machine Manual State Machine Design for a Vending Machine Timing Diagram Correspondence between Automatic and Manual Designs Design: LCD Controller Target LCD Module VHDL Solution Chapter Review Resources Bibliography Problems FPGA and Other Programmable Logic Devices Programmable Logic Devices Circuit Customization Programmable Logic Arrays Programmable Read-Only Memories Programmable And-Array Logic Field-Programmable Gate Arrays Gate Arrays FPGA Overview Xilinx FPGA FPGA Configuration Xilinx Spartan-ll FPGA Configuration Example Boundary Scan Chapter Review Resources Bibliography Problems Design of a USB Protocol Analyzer Overview of USB Full-Speed Mode Packet Transfer Protocol Initialization Sequence Physical Layer Interface USB Packets Cyclic Redundancy Checks 260

4 VÜ Observation of Actual USB Signals Design Overview State Machine Subcircuit Partitioning VHDL Solution Digital Phase Locked Loop NRZI-to-Binary Converter CRC Checker Subcircuits Packet ID Recognizer State Machine Subcircuit Top-Level Circuit Test-Bench Code for Entire Circuit Simulation Results Chapter Review Resources Bibliography Problems Design of Fast Arithmetic Units Adder Designs Ripple Carry Adder Carry-Lookahead Adder Carry-Save Adder Multiplier Designs Combinational Multiplier Sequential Multiplier Fast Multiplication Multiply-Accumulate Units Pipelined Functional Units Introduction to Pipelining Pipelined Multiply-Accumulate Units HDL Implementations HDL Implementation Overview HDL Design for a Pipelined Multiply-Accumulate Unit Test Bench and Simulation Results Chapter Review Resources Bibliography Problems 357 1ЩР ЩИ? Щг 40 Щ? ^JP W W w w w W Ш W Ш ш 9 Design of a Pipelined RISC Microprocessor Introduction to Microprocessors Reduced Instruction Set Computers Basic Computer Operation The THUMB Microprocessor Architecture THUMB Programming Model Overview of the THUMB Instruction Set Instruction Pipeline Design Pipeline Hazards Hazard Prevention Techniques Pipeline Hazard Solutions Adopted HDL Implementation of the THUMB Pipeline VHDL THUMB Implementation Test Bench Verification Chapter Review Resources Bibliography Problems 408 A THUMB Instruction Set Listing 411 A.1 ADC <Rd), (Rm) 411 A.2 ADD (Rd), (Rn), #immed3 411 A.3 ADD (Rd), immed8 412 A.4 ADD (Rd), (Rn), (Rm) 412 A.5 ADD (Rd), (Rm) 412 A.6 ADD (Rd), PC, #immed8 x A.7 ADD (Rd), SP, #immed8 x A.8 ADD SP, #immed7 x A.9 AND (Rd), (Rm) 413

5 VÜi A.10 ASR (Rd), (Rm), #immed5 413 A.11 ASR (Rd), (Rs) 414 A. 12 B(cond), (target-address) 414 A. 13 В (target_address) 415 A.14 BIC (Rd), (Rm) 416 A.15 BKPT (immed8) 416 A.16 BL (target_address) or BLX (target_address) 416 A.17 BLX (Rm) 417 A.18 BX (Rm) 417 A.19 CMN (Rn), (Rm) 418 A.20 CMP (Rn), #immed8 418 A.21 CMP (Rn), (Rm) 418 A.22 CMP (Rn), (Rm) 419 A.23 EOR (Rd), (Rm) 419 A.24 LDMIA (Rn)!, (registers) 419 A.25 LDR (Rd), (Rn), #immed5 x A.26 LDR (Rd), (Rn), (Rm) 420 A.27 LDR (Rd), PC, #immed8 x A.28 LDR (Rd), SP, #immed8 x A.29 LDRB (Rd), (Rn), #immed5 421 A.30 LDRB (Rd), (Rn), (Rm) 421 A.31 LDRH (Rd), (Rn), #immed5 x A.32 LDRH (Rd), (Rn), (Rm) 422 A.33 LDRSB (Rd), (Rn), (Rm) 422 A.34 LDRSH (Rd), (Rn), (Rm) 422 A.35 LSL (Rd), (Rm), #immed5 423 A.36 LSL (Rd), (Rs) 423 A.37 LSR (Rd), (Rm), #immed5 423 A.38 LSR (Rd), (Rs) 424 A.39 MOV (Rd), #immed8 424 A.40 MOV (Rd), (Rn) 424 A.41 MOV (Rd), (Rm) 424 A.42 MUL (Rd), (Rm) 425 A.43 MVN (Rd), (Rm) 425 A.44 NEG (Rd), (Rm) 425 A.45 ORR (Rd), (Rm) 425 A.46 POP (registers) 426 A.47 PUSH (registers) 426 A.48 ROR (Rd), (Rs) 427 A.49 SBC (Rd), (Rm) 427 A.50 STMIA (Rn)!, (registers) 427 A.51 STR (Rd), (Rn), #immed5 x A.52 STR (Rd), (Rn), (Rm) 428 A.53 STR (Rd), SP, #immed8 x A.54 STRB (Rd), (Rn), #immed5 428 A.55 STRB (Rd), (Rn), (Rm) 429 A.56 STRH (Rd), (Rn),#immed5 x A.57 STRH (Rd), (Rn), (Rm) 429 A.58 SUB (Rd), (Rn),#immed3 429 A.59 SUB (Rd),#immed8 430 A.60 SUB (Rd), (Rn), (Rm) 430 A.61 SUB SP, #immed7 x A.62 SWI (immed8) 430 A.63 TST (Rn), (Rm) 431 Щ # # В Answers to Selected Problems 432 B.1 Condensed Digital Logic Review 432 B.2 Digital Logic Design Using Hardware Description Languages 435 B.3 Introduction to VHDL and Test Benches 437 B.4 High-Level VHDL Coding for Synthesis 450 B.5 State Machine Design 460 B.6 FPGAs and Other Programmable Logic Devices 468 B.7 Design of a USB Protocol Analyzer 471 B.8 Design of Fast Arithmetic Units 473 B.9 Design of a Pipelined RISC CPU 479 Index 485