Chapter 6. Single-stage integrated-circuit amplifier
|
|
- Alaina Preston
- 5 years ago
- Views:
Transcription
1 hapter 6. Single-stage integrated-circuit amplifier ntroduction 6. design philosophy 6. omparison of the MSFET and the BJT 6.3 biasing-current - sources, mirrors and steering circuits 6.4 High-frequency response-general consideration 6.5 The common-source and common-emitter amplifiers with active loads 6.6 High-frequency response of the S and E amplifiers 6.7 The common-gate and common-base amplifiers with active loads 6.8 The cascode amplifier 6.9 The S and E amplifiers with source (emitter) 6.0 The source and emitter followers 6. Some useful transistor pairings 6. ircuit-mirror circuits with improved 6.3 The SPE MSFET model
2 담당교수 (instructor) 연도 (year) 학기 (semester) 교과목번호 (course number) 교과목명 (course name) 분반 (section) 권혁숭 0 B7899 전자회로 () 담당교수메일또는연락처 :hskwon@pusan.ac.kr, , 상담가능시간 : 수 :3:00~5:00. 교수목표및강의개요 (ourse objectives & Description) ) 교수목표. 차동증폭기, 다단증폭기,P-mp. 의동작특성과주파수응답특성등을분석, 설계할수있는능력을배양시킨다.. Feedback, ctive filter, Tuned amplifier 및신호발생기 ( 발진기 ) 전력증폭기등다양한응용분야를학습한다. 3. P-Spice simulation 을이용하여회로의동작과특성을분석하고설계하는능력을키운다. ) 강의개요. BJT, MSFET 와같은개별소자를이용한여러가지응용회로와귀환, 발진, 필터회로등을학습하고, 주파수특성에따른응답을확인한다.. P-mp.(74, MS ) 의기본적인구조와특성을 D 해석과소신호해석을통해파악한다. 또한이를이용한다양한회로와응용분야를학습한다. 3. 전자회로시스템의주요분야중하나인 ctive filter 와 tuned 증폭기, 신호발생기, 함수발생기, 전력증폭기등의동작특성과이론을학습한다.. 주교재 (Required textbook) 교재 : :Microelectronics ircuits" 5th Ed. 교재 : 저자 : del S. Sedra Kenneth. Smith 출판사 : "xford University Press 004" 3. 평가방법 (Requirements & Grading) 중간고사 : 30% 기말고사 : 30% Quiz: 0% Homework: 0% 출석 : 0% (subject to change if necessary)
3 4. 주별강의계획 (Schedule) 주별강의및실험 실기내용과제및기타참고사항 제 주 제 주 제 3 주 제 4 주 ch. 6 Single-stage ntergrated-ircuit mp.[ 표절등학술적부정행위예방교육실시 ] ch. 6 Single-stage ntergrated-ircuit mp.[ 표절등학술적부정행위예방교육실시 ] ch. 6 Single-stage ntergrated-ircuit mp. ch. 7 Differential and multistage mp. 제 5 주 ch. 7 Differential and multistage mp. Homework 제 6 주 제 7 주 제 8 주 제 9 주 ch.. 9 p-mp. and Data converter circuits ch.. 9 p-mp. and Data converter circuits ch.. 9 p-mp. and Data converter circuits Mid Exam. ch. 8 Feedback 제 0 주 ch. 8 Feedback Homework 제 주 제 주 제 3 주 제 4 주 제 5 주 제 6 주 ch. Filter and tuned amp. ch. Filter and tuned amp. Quiz ch. 3 Signal genterators and waveform shaping circuit. ch. 3 Signal genterators and waveform shaping circuit. ch. 4. Power mp. ch. 4. Power mp. Final Exam. 5. 참고문헌 (References) 교재명 :" 전자회로 ": 저자 :Boylestad, 김수원외, 출판사 : 사이텍미디어
4 6. design philosophy * nalogrf design hexagon Noise Power Linearity Frequency Supply voltage Gain * lmost any two of the six parameters tradeoff with each other to some extent
5 6. design philosophy * Semiconductor technologies for wireless communication RF section ntenna TR Duplexer ModulatorDemodulator LNPFilters Frequency synthesizer Gas MESFET Gas HBT SiGe BJT MS DSP section oding Multiplexer ccess ontrol EchoFade Power control MS section Battery management Display oice nterface MS Technology choice -. Performance, ost, Time-to-market three critical factors -. Level of integration, form factor, prior (successful integration) experience -. urrent technologies (MS BiMS Gas etc)
6 6. design philosophy design constraints -. avoid large resistors -. the number of -. realize as and capacitors to reduce the chip area external capacitors is also minimized to reduce the chip terminals many of the functions required as possible using MS transistor and small MS capacitor only design freedom -. the size of -. array of -. packing a MS transistors, their width and length, can be selected for design requirements transistors can be matched with a desired size ratio large number of devices on the same chip -. below 0. m minimum channel length, 007(0.3m : popular, 90nm process) urrent technology f DD T -. high - -. on printed - circuit currents -. high - 40GHz, usual od for 08. μm NMS, quality P - amp. output currents 0. 80GHz -. high reliability under severe environmental for 03. μm BJT is still better than MSFET in stand - alone performance conditions
7 6. omparison of the MSFET and the BJT. Typical values of MSFET parameters 0.8µm 0.5 µm 0.5 µm 0.8 µm Parameter NMS PMS NMS PMS NMS PMS NMS PMS t ox (nm) ox (ffµm ) µ(cm s) µ ox (µ ) t0 () DD () (µm) oυ (ffµm) Extra area Base on reversed times. times 6.5 times 5.6 times µm 0.5µm 0.5µm 0.8µm
8 Ex.) ntel computer : PU development 4004 processor 8086 processor 86 processor 386 processor 486 processor clock speed: 08KHz Transistor:,300 technology: 0μm clock speed: 5MHz Transistor: 9,000 technology: 3μm clock speed: 6MHz Transistor: 34,000 technology:.5μm clock speed: 6MHz Transistor: 75,000 technology:.5μm clock speed: 5MHz Transistor:,00,000 technology: μm pentium processor pentium pro processor pentium processor pentium 4 processor pentium M processor clock speed: 66MHz Transistor: 3,00,000 technology: 0.8μm clock speed: 00MHz Transistor: 5,500,000 technology: 0.6μm clock speed: 300MHz Transistor: 7,500,000 technology: 0.5μm clock speed:.5ghz Transistor: 4,000,000 technology: 0.8μm clock speed:.7ghz Transistor: 55,000,000 technology: 90nm pentium Dual core processor pentium D processor Quad core ore i7(nehalem) ore i..(sandy Bridge) clock speed: 3.GHz Transistor: 9,000,000 technology: 65nm clock speed: 3.GHz above Transistor: 80,000,000 technology: 45nm clock speed: 3.GHz above Transistor:,60,000,000 above technology: 3nm clock speed: 3.GHz above Transistor:,900,000,000 above technology:nm
9 . Typical values of BJTs Standard High-oltage Process dvanced Low-oltage Process Parameter npn Lateral pnp npn Lateral pnp E (µm ) S () β 0 () () E0 () τ F 0.35ns 30ns 0ps 650ps je0 pf 0.3pF 5fF 4fF µ0 0.3pF pf 5fF 5fF r x (Ω)
10 3. omparison of important characteristics NMS npn ircuit Symbol To perate in the ctive Mode, Two onditions Have To Be Satisfied () nduce a channel : υ GS t, t = Let υ GS = t + υ () Pinch-off channel at drain : υ GD < t or equivalently, υ DS, = () Forward-bias EBJ : υ on, on 0.5 () Reverse-bias BJ : υ B < Bon, Bon 0.4 or equivalently, υ E 0.3
11 omparison of the MSFET and BJT (ontinued) NMS npn urrent-oltage haracteristics in the ctive Region W id nox GS t L i G W nox L 0 DS DS i i B i e c S T E Low-Frequency Hybrid-π Model
12 omparison of the MSFET and BJT (ontinued) NMS npn Low-Frequency T Model Transconductance g m g m D W g L m n ox W g L m n ox D g m T
13 omparison of the MSFET and BJT (ontinued) NMS npn utput Resistance r o L r r ' o D D o ntrinsic Gain 0 g m r o ' L WL ' n ox D 0 T nput Resistance with Source (Emitter) Grounded r= g m
14 omparison of the MSFET and BJT (ontinued) NMS npn high- Frequency Model
15
16 6. omparison of MSFET and BJT BJT has the advantage over MSFET of a much higher transconductance g m at same value of D current. much higher gain per stage MSFET has infinite high input resistance at gate. MSFET provides an excellent implementation of switch. MSFET doesn t have the thermal run-away. MSFET has very high packing density. BiMS is a technology that combining high quality BJT and high density MS on the same chip.
17 6.3 Biasing urrent Sources, urrent Mirrors and urrent-steering ircuits constant D current (reference current) is generated at one location and is replicated at various other locations for biasing (current steering) 6.3. The basic MSFET current source urrent Mirror ' W D kn ( GS tn) L DD GS D R :current source (, R are outside of DD Q ) : ' W D kn ( L output current of GS tn ) current source Q o 와 관계는 ( W L) ( W L) Tr. 결합구조에따른다 : current mirror if Q Q urrent Transfer Ratio
18 in saturation for : Q t GS Early effect of : Q r R o ) ( ) ( ) ( ) ( ) ( ) ( GS DS DS L W L W L W L W ) ( ) ( DS DS DS DS DS DS DS DS Effect of o on o ) drain resistance(r : Effect of Drain short, Gate - : 0 Q Q
19 6.3. MS current-steering circuits Q, together with R determine the reference current Transistors Q, Q and Q 3 form a two output current mirror GS GS GS3 ( W L) ( W L), 3 ( W L) ( W L) 3 GD G D D G th th th PMS To ensureoperation in thesaturation or D, D D3, D3 SS SS GS tn, region urrent sink (pull) from load GS 4 4 D5 3, GS 5 DD ( W ( W L) L) 5 4 urrent source (push) to load ( ) GS G S
20 6.3.3 BJT ircuits ssume Q Q S S S,, & ) ( S E S B B e e T T 0 & ) ( B B S S e e T T,
21 BJT ircuits & 3) (,,, B E S B E S e e T T E E E E E E E E E E E E E E E B B ) ( ) (
22 ,, S m S m: current transfer ratio ( ) & ( ) ( 3) & & m ( m ) m ( m )
23 Simple urrent Source R o r o R urrent Steering EE R EB
24 & N BN B B B N N N N ) (
Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs
Integrated Circuit Amplifiers Comparison of MOSFETs and BJTs 17 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 )
More informationBJT Amplifier. Superposition principle (linear amplifier)
BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited
More informationImproving Amplifier Voltage Gain
15.1 Multistage ac-coupled Amplifiers 1077 TABLE 15.3 Three-Stage Amplifier Summary HAND ANALYSIS SPICE RESULTS Voltage gain 998 1010 Input signal range 92.7 V Input resistance 1 M 1M Output resistance
More information8. Biasing Transistor Amplifiers
8. iasing Transistor Amplifiers Lecture notes: Sec. 5 Sedra & Smith (6 th d): Sec. 5.4, 5.6 & 6.3-6.4 Sedra & Smith (5 th d): Sec. 4.4, 4.6 & 5.3-5.4 65, Winter013, F. Najmabadi ssues in developing a transistor
More informationPreliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B
Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B Problem 1. Consider the following circuit, where a saw-tooth voltage is applied
More informationChapter 15 Goals. ac-coupled Amplifiers Example of a Three-Stage Amplifier
Chapter 15 Goals ac-coupled multistage amplifiers including voltage gain, input and output resistances, and small-signal limitations. dc-coupled multistage amplifiers. Darlington configuration and cascode
More informationAnalog Integrated Circuit Design Exercise 1
Analog Integrated Circuit Design Exercise 1 Integrated Electronic Systems Lab Prof. Dr.-Ing. Klaus Hofmann M.Sc. Katrin Hirmer, M.Sc. Sreekesh Lakshminarayanan Status: 21.10.2015 Pre-Assignments The lecture
More informationEE 140 / EE 240A ANALOG INTEGRATED CIRCUITS FALL 2015 C. Nguyen PROBLEM SET #7
Issued: Friday, Oct. 16, 2015 PROBLEM SET #7 Due (at 8 a.m.): Monday, Oct. 26, 2015, in the EE 140/240A HW box near 125 Cory. 1. A design error has resulted in a mismatch in the circuit of Fig. PS7-1.
More informationF9 Differential and Multistage Amplifiers
Lars Ohlsson 018-10-0 F9 Differential and Multistage Amplifiers Outline MOS differential pair Common mode signal operation Differential mode signal operation Large signal operation Small signal operation
More informationHomework Assignment 12
Homework Assignment 12 Question 1 Shown the is Bode plot of the magnitude of the gain transfer function of a constant GBP amplifier. By how much will the amplifier delay a sine wave with the following
More informationCOMPARISON OF THE MOSFET AND THE BJT:
COMPARISON OF THE MOSFET AND THE BJT: In this section we present a comparison of the characteristics of the two major electronic devices: the MOSFET and the BJT. To facilitate this comparison, typical
More informationCurrent Mirrors. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-1
Current Mirrors Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 { Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 { Current Source and Sink Symbol
More informationSolid State Devices & Circuits. 18. Advanced Techniques
ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1 Darlington Configuration - Popular
More informationWeek 12: Output Stages, Frequency Response
ELE 2110A Electronic Circuits Week 12: Output Stages, Frequency esponse (2 hours only) Lecture 12-1 Output Stages Topics to cover Amplifier Frequency esponse eading Assignment: Chap 15.3, 16.1 of Jaeger
More informationMultistage Amplifiers
Multistage Amplifiers Single-stage transistor amplifiers are inadequate for meeting most design requirements for any of the four amplifier types (voltage, current, transconductance, and transresistance.)
More informationLow Dropout Voltage Regulator Operation and Performance Review
Low Drop Voltage Regulator peration and Performance Review Eric Chen & Alex Leng ntroduction n today s power management systems, high power efficiency becomes necessary to maximize the lifetime of the
More informationChapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors
1 Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors Current Mirror Example 2 Two Stage Op Amp (MOSFET) Current Mirror Example Three Stage 741 Opamp (BJT) 3 4
More informationIntroduction to MOSFET MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
Microelectronic Circuits Introduction to MOSFET MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Slide 1 MOSFET Construction MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Slide 2
More informationCode: 9A Answer any FIVE questions All questions carry equal marks *****
II B. Tech II Semester (R09) Regular & Supplementary Examinations, April/May 2012 ELECTRONIC CIRCUIT ANALYSIS (Common to EIE, E. Con. E & ECE) Time: 3 hours Max Marks: 70 Answer any FIVE questions All
More informationDesign and Simulation of Low Voltage Operational Amplifier
Design and Simulation of Low Voltage Operational Amplifier Zach Nelson Department of Electrical Engineering, University of Nevada, Las Vegas 4505 S Maryland Pkwy, Las Vegas, NV 89154 United States of America
More informationCourse Number Section. Electronics I ELEC 311 BB Examination Date Time # of pages. Final August 12, 2005 Three hours 3 Instructor
Course Number Section Electronics ELEC 311 BB Examination Date Time # of pages Final August 12, 2005 Three hours 3 nstructor Dr. R. Raut M aterials allowed: No Yes X (Please specify) Calculators allowed:
More informationMOSFET in ON State (V GS > V TH )
ndian nstitute of Technology Jodhpur, Year 08 Analog Electronics (ourse ode: EE34) ecture 8 9: MOSFETs, Biasing ourse nstructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in Webpage: http://home.iitj.ac.in/~sptiwari/
More informationAdvanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage
More informationChapter 8 Differential and Multistage Amplifiers
1 Chapter 8 Differential and Multistage Amplifiers Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4.
More informationLecture Wrap up. December 13, 2005
6.012 Microelectronic Devices and Circuits Fall 2005 Lecture 26 1 Lecture 26 6.012 Wrap up December 13, 2005 Contents: 1. 6.012 wrap up Announcements: Final exam TA review session: December 16, 7:30 9:30
More informationLecture 34: Designing amplifiers, biasing, frequency response. Context
Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will
More informationES 330 Electronics II Homework # 2 (Fall 2016 Due Wednesday, September 7, 2016)
Page1 Name ES 330 Electronics II Homework # 2 (Fall 2016 Due Wednesday, September 7, 2016) Problem 1 (15 points) You are given an NMOS amplifier with drain load resistor R D = 20 k. The DC voltage (V RD
More informationLaboratory #5 BJT Basics and MOSFET Basics
Laboratory #5 BJT Basics and MOSFET Basics I. Objectives 1. Understand the physical structure of BJTs and MOSFETs. 2. Learn to measure I-V characteristics of BJTs and MOSFETs. II. Components and Instruments
More informationSingle-Stage Integrated- Circuit Amplifiers
Single-Stage Integrated- Circuit Amplifiers Outline Comparison between the MOS and the BJT From discrete circuit to integrated circuit - Philosophy, Biasing, etc. Frequency response The Common-Source and
More informationMICROELECTRONIC CIRCUIT DESIGN Third Edition
MICROELECTRONIC CIRCUIT DESIGN Third Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 1/25/08 Chapter 1 1.3 1.52 years, 5.06 years 1.5 1.95 years, 6.46 years 1.8 113
More informationEE105 Fall 2015 Microelectronic Devices and Circuits
EE105 Fall 2015 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 11-1 Transistor Operating Mode in Amplifiers Transistors are biased in flat part of
More information6.012 Microelectronic Devices and Circuits
Page 1 of 13 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Microelectronic Devices and Circuits Final Eam Closed Book: Formula sheet provided;
More informationDepletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET
Ch. 13 MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor : I D D-mode E-mode V g The gate oxide is made of dielectric SiO 2 with e = 3.9 Depletion-mode operation ( 공핍형 ): Using an input gate voltage
More informationQUESTION BANK for Analog Electronics 4EC111 *
OpenStax-CNX module: m54983 1 QUESTION BANK for Analog Electronics 4EC111 * Bijay_Kumar Sharma This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 4.0 Abstract
More informationFINAL EXAMINATION SOLUTIONS
FINAL EXAMINATION SOLUTIONS Electronics I for EE ourse Number EE 09-3 N 0460 Instructor: James K Beard, PhD beard@rowanedu Page of 3 Table of ontents Problem (0%)3 Solution 3 Problem (0%)5 Solution 6 Problem
More informationBuilding Blocks of Integrated-Circuit Amplifiers
Building Blocks of ntegrated-circuit Amplifiers 1 The Basic Gain Cell CS and CE Amplifiers with Current Source Loads Current-source- or active-loaded CS amplifier Rin A o R A o g r r o g r 0 m o m o Current-source-
More informationMetal Oxide Semiconductor Field-Effect Transistors (MOSFETs)
Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) Device Structure N-Channel MOSFET Providing electrons Pulling electrons (makes current flow) + + + Apply positive voltage to gate: Drives away
More informationCHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS
CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS Chapter Outline 8.1 The CMOS Differential Pair 8. Small-Signal Operations of the MOS Differential Pair 8.3 The BJT Differential Pair 8.4 Other Non-ideal
More informationECEN 5008: Analog IC Design. Final Exam
ECEN 5008 Initials: 1/10 ECEN 5008: Analog IC Design Final Exam Spring 2004 Instructions: 1. Exam Policy: Time-limited, 150-minute exam. When the time is called, all work must stop. Put your initials on
More informationES 330 Electronics II Fall 2016
ES 330 Electronics II Fall 2016 Sect Lectures Location Instructor Office Office Hours Email Tel 001 001 9:00 am to 9:50 am Wednesday 10:00 am to 10 :50 am 2001 2001 Dr. Donald Estreich Dr. Donald Estreich
More informationAnalog Electronics (Course Code: EE314) Lecture 9 10: BJT Small Signal, Biasing, Amplifiers
Indian Institute of Technology Jodhpur, Year 08 Analog Electronics (ourse ode: EE34) Lecture 9 0: BJT Small Signal, Biasing, Amplifiers ourse Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in
More informationLecture 33: Context. Prof. J. S. Smith
Lecture 33: Prof J. S. Smith Context We are continuing to review some of the building blocks for multi-stage amplifiers, including current sources and cascode connected devices, and we will also look at
More informationMicroelectronic Circuits
SECOND EDITION ISHBWHBI \ ' -' Microelectronic Circuits Adel S. Sedra University of Toronto Kenneth С Smith University of Toronto HOLT, RINEHART AND WINSTON HOLT, RINEHART AND WINSTON, INC. New York Chicago
More informationLecture 030 ECE4430 Review III (1/9/04) Page 030-1
Lecture 030 ECE4430 Review III (1/9/04) Page 0301 LECTURE 030 ECE 4430 REVIEW III (READING: GHLM Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material
More informationBJT Circuits (MCQs of Moderate Complexity)
BJT Circuits (MCQs of Moderate Complexity) 1. The current ib through base of a silicon npn transistor is 1+0.1 cos (1000πt) ma. At 300K, the rπ in the small signal model of the transistor is i b B C r
More informationChapter 11. Differential Amplifier Circuits
Chapter 11 Differential Amplifier Circuits 11.0 ntroduction Differential amplifier or diff-amp is a multi-transistor amplifier. t is the fundamental building block of analog circuit. t is virtually formed
More informationES 330 Electronics II Homework # 8 Soltuions (Fall 2017 Due Wednesday, November 13, 2017)
Page1 Name Solutions ES 330 Electronics Homework # 8 Soltuions (Fall 017 ue Wednesday, November 13, 017) Problem 1 (16 points) You are given a common-emitter BJT and a common-source MSFET (n-channel).
More informationSingle-Stage BJT Amplifiers and BJT High-Frequency Model. Single-Stage BJT Amplifier Configurations
1 Single-Stage BJT Amplifiers and BJT High-Frequency Model Asst. Prof. MONTREE SIRIPRUCHYANUN, D. Eng. Dept. of Teacher Training in Electrical Engineering, Faculty of Technical Education King Mongkut s
More informationChapter 4 Physics of Bipolar Transistors. EE105 - Spring 2007 Microelectronic Devices and Circuits. Structure and Symbol of Bipolar Transistor
EE105 - Spring 2007 Microelectronic Devices and ircuits Lecture 10 Bipolar ransistors hapter 4 Physics of Bipolar ransistors 4.1 General onsiderations 4.2 Structure of Bipolar ransistor 4.3 Operation of
More informationEE311: Electrical Engineering Junior Lab, Fall 2006 Experiment 4: Basic MOSFET Characteristics and Analog Circuits
EE311: Electrical Engineering Junior Lab, Fall 2006 Experiment 4: Basic MOSFET Characteristics and Analog Circuits Objective This experiment is designed for students to get familiar with the basic properties
More informationECEG 350 Electronics I Fall 2017
EEG 350 Electronics Fall 07 Final Exam General nformation Rough breakdown of topic coverage: 0-0% JT fundamentals and regions of operation 0-40% MOSFET fundamentals biasing and small-signal modeling 0-5%
More informationLecture 21 - Multistage Amplifiers (I) Multistage Amplifiers. November 22, 2005
6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 2 Lecture 2 Multistage Amplifiers (I) Multistage Amplifiers November 22, 2005 Contents:. Introduction 2. CMOS multistage voltage amplifier 3.
More informationDesign and Analysis of Two-Stage Amplifier
Design and Analysis of Two-Stage Amplifier Introduction This report discusses the design and analysis of a two stage amplifier. An FET based common source amplifier was designed.fet was preferred over
More informationEE105 Fall 2015 Microelectronic Devices and Circuits
EE105 Fall 2015 Microelectronic Devices and Circuits Multi-Stage Amplifiers Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of MOS Amplifiers Common
More informationSAMPLE FINAL EXAMINATION FALL TERM
ENGINEERING SCIENCES 154 ELECTRONIC DEVICES AND CIRCUITS SAMPLE FINAL EXAMINATION FALL TERM 2001-2002 NAME Some Possible Solutions a. Please answer all of the questions in the spaces provided. If you need
More informationI E I C since I B is very small
Figure 2: Symbols and nomenclature of a (a) npn and (b) pnp transistor. The BJT consists of three regions, emitter, base, and collector. The emitter and collector are usually of one type of doping, while
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
OTA-output buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage
More informationMicroelectronic Circuits II. Ch 6 : Building Blocks of Integrated-Circuit Amplifier
Micrelectrnic Circuits II Ch 6 : Building Blcks f Integrated-Circuit Amplifier 6.1 IC Design Philsphy 6.A Cmparisn f the MOSFET and the BJT 6.2 The Basic Gain Cell CNU EE 6.1-1 Intrductin Basic building
More informationCMOS Cascode Transconductance Amplifier
CMOS Cascode Transconductance Amplifier Basic topology. 5 V I SUP v s V G2 M 2 iout C L v OUT Device Data V Tn = 1 V V Tp = 1 V µ n C ox = 50 µa/v 2 µ p C ox = 25 µa/v 2 λ n = 0.05 V 1 λ p = 0.02 V 1 @
More informationINTRODUCTION TO ELECTRONICS EHB 222E
INTRODUCTION TO ELECTRONICS EHB 222E MOS Field Effect Transistors (MOSFETS II) MOSFETS 1/ INTRODUCTION TO ELECTRONICS 1 MOSFETS Amplifiers Cut off when v GS < V t v DS decreases starting point A, once
More informationThe Differential Amplifier. BJT Differential Pair
1 The Differential Amplifier Asst. Prof. MONTREE SRPRUCHYANUN, D. Eng. Dept. of Teacher Training in Electrical Engineering, Faculty of Technical Education King Mongkut s nstitute of Technology North Bangkok
More informationHello, and welcome to the TI Precision Labs video discussing comparator applications, part 4. In this video we will discuss several extra features
Hello, and welcome to the TI Precision Labs video discussing comparator applications, part 4. In this video we will discuss several extra features that are integrated into some comparators to help simplify
More informationDepartment of Electrical Engineering IIT Madras
Department of Electrical Engineering IIT Madras Sample Questions on Semiconductor Devices EE3 applicants who are interested to pursue their research in microelectronics devices area (fabrication and/or
More informationSIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR (AUTONOMOUS) Siddharth Nagar, Narayanavanam Road QUESTION BANK
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR (AUTONOMOUS) Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK Subject with Code : Electronic Circuit Analysis (16EC407) Year & Sem: II-B.Tech & II-Sem
More informationDesign of Analog and Mixed Integrated Circuits and Systems Theory Exercises
102726 Design of nalog and Mixed Theory Exercises Francesc Serra Graells http://www.cnm.es/~pserra/uab/damics paco.serra@imb-cnm.csic.es 1 Introduction to the Design of nalog Integrated Circuits 1.1 The
More informationMICROELECTRONIC CIRCUIT DESIGN Fifth Edition
MICROELECTRONIC CIRCUIT DESIGN Fifth Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 07/05/15 Chapter 1 1.5 1.52 years, 5.06 years 1.6 1.95 years, 6.52 years 1.9 402
More informationChapter 12 Opertational Amplifier Circuits
1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.
More information4.2.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
4.2.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) The Metal Oxide Semitonductor Field Effect Transistor (MOSFET) has two modes of operation, the depletion mode, and the enhancement mode.
More informationES 330 Electronics II Homework # 6 Soltuions (Fall 2016 Due Wednesday, October 26, 2016)
Page1 Name Solutions ES 330 Electronics Homework # 6 Soltuions (Fall 016 ue Wednesday, October 6, 016) Problem 1 (18 points) You are given a common-emitter BJT and a common-source MOSFET (n-channel). Fill
More informationField Effect Transistors
Field Effect Transistors Purpose In this experiment we introduce field effect transistors (FETs). We will measure the output characteristics of a FET, and then construct a common-source amplifier stage,
More informationReading. Lecture 33: Context. Lecture Outline. Chapter 9, multi-stage amplifiers. Prof. J. S. Smith
eading Lecture 33: Chapter 9, multi-stage amplifiers Prof J. S. Smith Context Lecture Outline We are continuing to review some of the building blocks for multi-stage amplifiers, including current sources
More information1. The fundamental current mirror with MOS transistors
1. The fundamental current mirror with MOS transistors The test schematic (ogl-simpla-mos.asc): 1. Size the transistors in the mirror for a current gain equal to unity, a 30μA input current and V DSat
More informationEE105 Fall 2015 Microelectronic Devices and Circuits Multi-Stage Amplifiers. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)
EE105 Fall 2015 Microelectronic Devices and Circuits Multi-Stage Amplifiers Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) Differential & Common Mode Signals Why Differential? Differential
More informationLecture 26 - Design Problems & Wrap-Up. May 15, 2003
6.012 Microelectronic Devices and Circuits - Spring 2003 Lecture 26-1 Lecture 26 - Design Problems & 6.012 Wrap-Up May 15, 2003 Contents: 1. Design process 2. Design project pitfalls 3. Lessons learned
More informationD n ox GS THN DS GS THN DS GS THN. D n ox GS THN DS GS THN DS GS THN
Name: EXAM #3 Closed book, closed notes. Calculators may be used for numeric computations only. All work is to be your own - show your work for maximum partial credit. Data: Use the following data in all
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 216 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
Low power OTA 1 Two-Stage, Miller Op Amp Operating in Weak Inversion Low frequency response: gm1 gm6 Av 0 g g g g A v 0 ds2 ds4 ds6 ds7 I D m, ds D nvt g g I n GB and SR: GB 1 1 n 1 2 4 6 6 7 g 2 2 m1
More informationLinear electronic. Lecture No. 1
1 Lecture No. 1 2 3 4 5 Lecture No. 2 6 7 8 9 10 11 Lecture No. 3 12 13 14 Lecture No. 4 Example: find Frequency response analysis for the circuit shown in figure below. Where R S =4kR B1 =8kR B2 =4k R
More informationBipolar Transistors. Ideal Transistor. Reading: (4-5 th edition) 8-16, Bipolar Transistor - Terminals. NPN Bipolar Transistor Physics
Bipolar Transistors deal Transistor Bipolar Transistor Terminals Reading: (45 th edition) 816, 2633 P Bipolar Transistor Physics Large Signal Model Early Effect Small Signal Model Modern Electronics: F3
More informationLecture 9. Bipolar Junction Transistor (BJT) BJT 1-1
Lecture 9 ipolar Junction Transistor (JT) JT 1-1 Outline ontinue JT JT iasing D analysis Fixed-bias circuit mitter-stabilized bias circuit oltage divider bias circuit D bias with voltage feedback circuit
More informationDC Coupling: General Trends
DC Coupling: General Trends * Goal: want both input and output to be centered at halfway between the positive and negative supplies (or ground, for a single supply) -- in order to have maximum possible
More informationDESIGN ANALYSIS AND COMPARATIVE STUDY OF RF RECEIVER FRONT-ENDS IN 0.18-µM CMOS
International Journal of Electrical and Electronics Engineering Research Vol.1, Issue 1 (2011) 41-56 TJPRC Pvt. Ltd., DESIGN ANALYSIS AND COMPARATIVE STUDY OF RF RECEIVER FRONT-ENDS IN 0.18-µM CMOS M.
More informationChapter 6. BJT Amplifiers
Basic Electronic Devices and Circuits EE 111 Electrical Engineering Majmaah University 2 nd Semester 1432/1433 H Chapter 6 BJT Amplifiers 1 Introduction The things you learned about biasing a transistor
More informationField-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism;
Chapter 3 Field-Effect Transistors (FETs) 3.1 Introduction Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism; The concept has been known
More information4.5 Biasing in MOS Amplifier Circuits
4.5 Biasing in MOS Amplifier Circuits Biasing: establishing an appropriate DC operating point for the MOSFET - A fundamental step in the design of a MOSFET amplifier circuit An appropriate DC operating
More informationMini Project 3 Multi-Transistor Amplifiers. ELEC 301 University of British Columbia
Mini Project 3 Multi-Transistor Amplifiers ELEC 30 University of British Columbia 4463854 November 0, 207 Contents 0 Introduction Part : Cascode Amplifier. A - DC Operating Point.......................................
More informationIndex. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10
Index A absolute value, 308 additional pole, 271 analog multiplier, 190 B BiCMOS,107 Bode plot, 266 base-emitter voltage, 16, 50 base-emitter voltages, 296 bias current, 111, 124, 133, 137, 166, 185 bipolar
More informationThe Miller Approximation. CE Frequency Response. The exact analysis is worked out on pp of H&S.
CE Frequency Response The exact analysis is worked out on pp. 639-64 of H&S. The Miller Approximation Therefore, we consider the effect of C µ on the input node only V ---------- out V s = r g π m ------------------
More informationChapter 4 DC Biasing BJTs. BJTs
hapter 4 D Biasing BJTs BJTs Biasing Biasing: The D voltages applied to a transistor in order to turn it on so that it can amplify the A signal. Operating Point The D input establishes an operating or
More informationCurrent Mirrors. Basic BJT Current Mirror. Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror.
Current Mirrors Basic BJT Current Mirror Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror. For its analysis, we assume identical transistors and neglect
More informationECE 3110: Engineering Electronics II Fall Final Exam. Dec. 16, 8:00-10:00am. Name: (78 points total)
Final Exam Dec. 16, 8:00-10:00am Name: (78 points total) Problem 1: Consider the emitter follower in Fig. 7, which is being used as an output stage. For Q 1, assume β = and initally assume that V BE =
More informationLecture 14. Bipolar Junction Transistor (BJT) BJT 1-1
Lecture 14 ipolar Junction Transistor (JT) JT 1-1 Outline ontinue JT iasing D analysis Fixed-bias circuit (revision) mitter-stabilized bias circuit oltage divider bias circuit D bias with voltage feedback
More informationCode No: Y0221/R07 Set No. 1 I B.Tech Supplementary Examinations, Apr/May 2013 BASIC ELECTRONIC DEVICES AND CIRCUITS (Electrical & Electronics Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions
More informationETI , Good luck! Written Exam Integrated Radio Electronics. Lund University Dept. of Electroscience
und University Dept. of Electroscience EI170 Written Exam Integrated adio Electronics 2010-03-10, 08.00-13.00 he exam consists of 5 problems which can give a maximum of 6 points each. he total maximum
More informationV o2 = V c V d 2. V o1. Sensor circuit. Figure 1: Example of common-mode and difference-mode voltages. V i1 Sensor circuit V o
M.B. Patil, IIT Bombay 1 BJT Differential Amplifier Common-mode and difference-mode voltages A typical sensor circuit produces an output voltage between nodes A and B (see Fig. 1) such that V o1 = V c
More informationBJT as an Amplifier and Its Biasing
Microelectronic ircuits BJT as an Amplifier and Its Biasing Slide 1 Transfer haracteristics & Biasing Slide 2 BJT urrent-oltage relationship The collector current i I i i B s e i B vbe Is e T v BE T Emitter
More informationEE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)
EE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 7-1 Simplest Model of MOSFET (from EE16B) 7-2 CMOS Inverter 7-3 CMOS NAND
More informationLecture 12. Bipolar Junction Transistor (BJT) BJT 1-1
Lecture 12 Bipolar Junction Transistor (BJT) BJT 1-1 Course Info Lecture hours: 4 Two Lectures weekly (Saturdays and Wednesdays) Location: K2 Time: 1:40 pm Tutorial hours: 2 One tutorial class every week
More informationCurrent Supply Topology. CMOS Cascode Transconductance Amplifier. Basic topology. p-channel cascode current supply is an obvious solution
CMOS Cascode Transconductance Amplifier Basic topology. Current Supply Topology p-channel cascode current supply is an obvious solution Current supply must have a very high source resistance r oc since
More informationTWO AND ONE STAGES OTA
TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +39-38-50505; fax. +39-038-505677 474 EE Department
More information