8. Biasing Transistor Amplifiers

Transcription

1 8. iasing Transistor Amplifiers Lecture notes: Sec. 5 Sedra & Smith (6 th d): Sec. 5.4, 5.6 & Sedra & Smith (5 th d): Sec. 4.4, 4.6 & , Winter013, F. Najmabadi

2 ssues in developing a transistor amplifier: 1. Find the iv characteristics of the elements for the signal (which can be different than their characteristics equation for bias). o This will lead to different circuit configurations for bias versus signal. ompute circuit response to the signal o Focus on fundamental transistor amplifier configurations 3. How to establish a ias point (bias is the state of the system when there is no signal). o Stable and robust bias point should be resilient to variations in µ n ox (W/L), t (or β for JT) due to temperature and/or manufacturing variability. o ias point details impact small signal response (e.g., gain of the amplifier). F. Najmabadi, 65, Winter 013, Amplifier iasing (/9)

3 JT biasing with ase oltage (Fixed ias) KL : + 0 β β 0 KL : + β ( 0 ) F. Najmabadi, 65, Winter 013, Amplifier iasing (3/9) * Typically in order to reduce the need for additional erence voltages.

4 xercise 1: Find and such that JT would be in active with 5 and 5 ma. ( 15, Si JT with β 0 and A ). JT is in Active since 0 and 5 0 > 0.7 / β 0.5 ma KL : k KL : Ω F. Najmabadi, 65, Winter 013, Amplifier iasing (4/9)

5 xercise : onsider the circuit designed in xercise 1 ( 400, 57. k, 15 ). Find the operating point of JT if β 00. Assume JT is in Active: 0.7, > 0 and 0.7 KL : ma β 50 ma KL : JT in saturation! Note, compared to xercise 1: is the same. has increased. had decreased. F. Najmabadi, 65, Winter 013, Amplifier iasing (5/9)

6 Why biasing with base voltage (fixed bias) does not work? hanges in JT β changes the bias point drastically. o JT can end up in saturation or in cut-off easily. n fixed bias, is set through JT β then sets β ( changes with β ). o circuit then sets. 0 ut, requirements for JT in active are on and and NOT on o > 0, > 0 To make bias point independent of changes in β, the bias circuit should set and NOT! F. Najmabadi, 65, Winter 013, Amplifier iasing (6/9)

7 iasing with mitter egeneration equires a resistor in the emitter circuit! KL : β + 1 f : << ( β + 1) 0 0 ndependent of β! ondition of << ( β +1) means that the voltage drop across is small and the bias voltage 0 appears across, setting and. F. Najmabadi, 65, Winter 013, Amplifier iasing (7/9) Note that resistor is NOT necessary for good biasing but it may exist due to other considerations.

8 mitter resistor provides negative feedback! + + e / T Negative Feedback: -KL ndependent of junction β! β o f (because β ), -KL junction β o f (because β ), F. Najmabadi, 65, Winter 013, Amplifier iasing (8/9)

9 equirements for iasing with mitter egeneration equires a resistor in the emitter circuit. The bias voltage 0 should appear across to set : 1. + << << ( β +1) o We need to set << ( β min + 1) to ensure that this condition is always satisfied!. 0. n reality, 0 ± with 0.1 o We need to set >> 0.1 or 1 F. Najmabadi, 65, Winter 013, Amplifier iasing (9/9)

10 mitter egeneration ias with a voltage divider eal ircuit oltage ivider F. Najmabadi, 65, Winter 013, Amplifier iasing (/9)

11 xercise 3: Find the bias point of the JT (Si JT with β 00 and A ) k 34 k 5.03 k 5.9 k k + 34 k Assume JT is in Active: 0.7, > 0 and 0.7 KL :.. KL : ma + F. Najmabadi, 65, Winter 013, Amplifier iasing (11/9) > /( β + 1) 14.1 µ A /( β + 1) β /( β + 1).8 ma Notes: 1. We need to solve the complete -KL as we do not know if << ( β + 1). β >> 1 is a good approximation that reduces the amount of work. Answers using β >> 1 approximation:.84 ma, 14. µ A.7

12 xercise 4: esign a JT bias circuit (emitter degeneration with voltage divider) such that.5 ma and 7.5. ( 15 Si JT with β ranging from 50 to 00 and A ). Step 1: Find and KL : ( 3.0 k + + ) Free to choose individual values & (we will see later that amplifier parameters sets the individual values) hoose : k k.0 k heck: 1 ircuit Prototype F. Najmabadi, 65, Winter 013, Amplifier iasing (1/9)

13 xercise 4 (ont d): esign a JT bias circuit (emitter degeneration with voltage divider) such that 5 ma and 5. ( 15 Si JT with β ranging from 50 to 00 and A ). Step : Find and << ( β + 1) 0.1 ( βmin + 1) 5.1 k min 5.1 k Using relative error, ε % Use largest (Will see later why) Step 3: Find 1 and k k 3.9 k k Step 4: Find commercial values: k 1 k 1 4 k 6.4 k F. Najmabadi, 65, Winter 013, Amplifier iasing (13/9)

14 mitter-degeneration bias circuits asic Arrangement + + ias with one power supply (voltage divider) + + ias with two power supplies F. Najmabadi, 65, Winter 013, Amplifier iasing (14/9)

15 MOS bias with Gate oltage (Fixed ias) S 0.5µ n ox W L ( GS t ) This method is NOT desirable as µ n ox (W/L) and t are not welldefined. ias point (i.e., and S ) can change drastically due to temperature and/or manufacturing variability. o See S&S xercise 5.33 (S&S 5 th d: xercise 4.19): hanging t from 1 to 1.5 leads to a 75% change in. F. Najmabadi, 65, Winter 013, Amplifier iasing (15/9)

16 MOS bias with Source egeneration (esistor S provides negative feedback!) GS G S W 0.5µ nox ( GS t L ) Negative Feedback: GS KL q. o f (because µ n ox (W/L) or t ) GS GS KL o f (because µ n ox (W/L) or t ) GS q. Feedback is most effective if S GS >> G GS + S 0 G / S F. Najmabadi, 65, Winter 013, Amplifier iasing (16/9)

17 Source-degeneration bias circuits asic Arrangement + G GS S ias with one power supply (voltage divider) + G ias with two power supplies + GS S SS GS S 0 GS + S SS F. Najmabadi, 65, Winter 013, Amplifier iasing (17/9)

18 xercise 5: Find the bias point for t 1 and µ n ox (W/L) 1.0 ma/ (gnore channel-width modulation). oltage divider ( G 0) G ( 7) /(7 + 8) µ GS- KL : O O 5 O + t n + O 15 4 S ox W O L 7 G 7 ( S- KL : 15 GS S S G S O / + 1 S GS S ma GS O O S ) 7 1 xercise (impact of S ): Prove that if t 1.5 (50% change), 0.455mA (9% change) F. Najmabadi, 65, Winter 013, Amplifier iasing (18/9)

19 iasing in s esistors take too much space on the chip. So, biasing with emitter or source degeneration are NOT implemented in s. ecall that the goal of a good bias is to ensure that and (or and S for MOS) do not change. One can force (or for MOS) to be constant using a current source. urrent source forces urrent source forces F. Najmabadi, 65, Winter 013, Amplifier iasing (19/9)

20 JT response to a current source 1) urrent source forces: ) / β 3A) 3) is set by -KL ) F. Najmabadi, 65, Winter 013, Amplifier iasing (0/9)

21 MOS response to a current source 1) urrent source forces: ) GS is set by W 0.5µ nox ( GS t ) L 3A) 3) S G GS GS 4) S S F. Najmabadi, 65, Winter 013, Amplifier iasing (1/9)

22 urrent Mirrors (or urrent Steering circuits) are used as current sources for biasing s Q is always in active since i, > 0,, 0 dentical JTs dentical JTs and v, v 1 o JTs will have the same i and the same i (ignoring arly effect) i KL : i, + i i + β i 1 1+ / β Since 1 const. regardless of 1, this is a current source! For the current mirror to work, Q1 should be in active: F. Najmabadi, 65, Winter 013, Amplifier iasing (/9)

23 An implementation of a JT urrent Mirror - KL ( Q ) : F. Najmabadi, 65, Winter 013, Amplifier iasing (3/9)

24 xercise 6: Find the bias point of Q (Si JT with β 0 and A ). urrent Mirror Assume Q in active: ma / β 46.5 µ A - KL : ma ma 5 F. Najmabadi, 65, Winter 013, Amplifier iasing (4/9) - KL : heck Q1 in active: > ( 5) > Q in active!

25 xamples of JT current mirrors One erence JT feeds many current mirrors PNP current Mirror nteger multiple of can be made (See Q3 & Q4) F. Najmabadi, 65, Winter 013, Amplifier iasing (5/9)

26 MOS urrent-steering ircuit Q is always in saturation since S, GS, GS, GS1 > GS O, O1 O GS, t dentical MOS: Same µ ox and t 1 i i 1, 1 0.5µ 0.5µ ( W / L) 1 ( W / L) n n ox ox ( W ( W / L) / L) 1 O Since 1 const. regardless of 1, this is a current source! O For the current steering circuit to work, Q1 should be in saturation: S1 > O GS t F. Najmabadi, 65, Winter 013, Amplifier iasing (6/9)

27 An implementation of a MOS current steering circuit i GS- KL 0.5µ ( Q n ox ) : ( W / L) i O + v GS SS i + [ 0.5µ n O ox ( W SS / L) + ] t O 0 + O + [ SS + t ] 0 The above quadratic equation gives O. 1 is then found from the MOS i equation. F. Najmabadi, 65, Winter 013, Amplifier iasing (7/9)

28 xamples of MOS current steering circuits One erence MOS feeds many current steering circuits. Any value of can be made (thus, currentsteering circuit instead of current-mirror) 1 ( W / L) 1 W W / L W ( ) ( / L) ( / L) PMOS current steering circuit F. Najmabadi, 65, Winter 013, Amplifier iasing (8/9)

29 An implementation of current steering circuit to bias several transistors in an F. Najmabadi, 65, Winter 013, Amplifier iasing (9/9) xercise: ompute 4 /