IRS2184/IRS21844(S)PbF
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- Aldous Ferguson
- 5 years ago
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1 Data Sheet No. PD Features Floating channel designed for bootstrap operation Fully operational to + V Tolerant to negative transient voltage, dv/dt immune Gate drive supply range from V to V Undervoltage lockout for both channels. V and V input logic compatible Matched propagation delay for both channels Logic and power ground +/- V offset Lower di/dt gate driver for better noise immunity Output source/sink current capability. A/.8 A RoHS compliant Description The IRS8/IRS8 are high voltage, high speed power MOSFET and IGBT drivers with dependent high-side and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to. V logic. The output drivers feature a IRS8/IRS8(S)PbF Packages Feature Comparison Part Input logic Crossconduction prevention logic HALF-BRIDGE DRIVER 8-Lead PDIP IRS8 8-Lead SOIC IRS8S Deadtime (ns) -Lead PDIP IRS8 Ground Pins 8 COM HIN/LIN no none 8 VSS/COM 8 Internal COM HIN/LIN yes 8 Program - VSS/COM 8 Internal COM IN/SD yes 8 Program - VSS/COM -Lead SOIC IRS8S high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to V. ton/toff (ns) 8/ 8/ 8/7 Typical Connection up to V V B IN IN SD SD COM V S TO AD up to V IRS8 IRS8 V B (Refer to Lead Assignments for correct configuration).these diagrams show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. IN SD V SS R DT IN SD DT V SS V S COM TO AD
2 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Units V B High-side floating absolute voltage -. (Note ) V S High-side floating supply offset voltage V B - V B +. V High-side floating output voltage V S -. V B +. Low-side and logic fixed supply voltage -. (Note ) V Low-side output voltage DT Programmable deadtime pin voltage (IRS8 only) V SS V IN Logic input voltage (IN & SD) V SS V SS Logic ground (IRS8 only) - +. dv S /dt Allowable offset supply voltage transient V/ns P D Package power T A + C RthJA Thermal resistance, junction to ambient (8-lead PDIP). (8-lead SOIC). (-lead PDIP). (-lead SOIC). (8-lead PDIP) (8-lead SOIC) (-lead PDIP) 7 (-lead SOIC) T J Junction temperature T S Storage temperature - T L Lead temperature (soldering, seconds) Note : All supplies are fully tested at V and an internal V clamp exists for each supply. Recommended Operating Conditions The input/output logic timing diagram is shown in Fig.. For proper operation the device should be used within the recommended conditions. The V S and V SS offset rating are tested with all supplies biased at a V differential. Symbol Definition Min. Units V B High-side floating supply absolute voltage V S + V S + V S High-side floating supply offset voltage Note V High-side floating output voltage V S V B Low-side and logic fixed supply voltage V Low-side output voltage V V IN Logic input voltage (IN & SD) V SS DT Programmable deadtime pin voltage (IRS8 only) V SS V SS Logic ground (IRS8 only) - T A Ambient temperature - C Note : Logic operational for V S of - V to + V. Logic state held for V S of - V to -V BS. (Please refer to the Design Tip DT97- for more details). V W C/W C
3 Dynamic Electrical Characteristics V BIAS (, V BS ) = V, V SS = COM, C L = pf, T A = C, DT = V SS unless otherwise specified. Symbol Definition Min. Units Test Conditions ton Turn-on propagation delay 8 9 V S = V toff Turn-off propagation delay 7 V S = V or V tsd Shut-down propagation delay 8 7 MTon Delay matching, HS & LS turn-on 9 MToff Delay matching, HS & LS turn-off tr Turn-on rise time tf Turn-off fall time DT MDT Deadtime: turn-off to turn-on(dt-) & 8 R DT = Ω turn-off to turn-on (DT-) µs R DT = kω Deadtime matching = DT - - DT- Static Electrical Characteristics V BIAS (, V BS ) = V, V SS = COM, DT= V SS and T A = C unless otherwise specified. The V IL, V IH, and I IN parameters are referenced to V SS /COM and are applicable to the respective input leads: IN and SD. The V O, I O, and Ron parameters are referenced to COM and are applicable to the respective output leads: and. Symbol Definition Min. Units Test Conditions V IH Logic input voltage for & logic for. V IL Logic input voltage for & logic for.8 V SD,TH+ SD input positive going threshold. V SD,TH- SD input negative going threshold.8 V OH High level output voltage, V BIAS - V O. I O = A V OL Low level output voltage, V O. I O = ma I LK Offset supply leakage current V B = V S = V µa I QBS Quiescent V BS supply current V IN = V or V I QCC Quiescent supply current... ma I IN+ Logic input bias current IN = V, SD = V µa I IN- Logic input bias current. IN = V, SD = V UV+ and V BS supply undervoltage positive going V BSUV+ threshold UV- and V BS supply undervoltage negative going V BSUV- threshold UVH Hysteresis..7 ns R DT = Ω R DT = kω ns V V V S = V = V to V V BSUVH I O+ Output high short circuit pulsed current..9 IO- Output low short circuit pulsed current.8. A V O = V, PW µs V O = V, PW µs
4 Functional Block Diagrams 8 SD UV DETECT DELAY IN VS VB PULSE FILTER HV LEVEL SHIFTER R R S Q UV DETECT PULSE GENERATOR VSS/COM LEVEL SHIFT VSS/COM LEVEL SHIFT +V DEADTIME COM VCC 8 SD UV DETECT DELAY IN DT VSS VS VB PULSE FILTER HV LEVEL SHIFTER R R S Q UV DETECT PULSE GENERATOR VSS/COM LEVEL SHIFT VSS/COM LEVEL SHIFT +V DEADTIME COM VCC
5 Lead Definitions Symbol Description IN Logic input for high-side and low-side gate driver outputs ( and ), in phase with (referenced to COM for IRS8 and VSS for IRS8) SD DT VSS V B V S COM Logic input for shutdown (referenced to COM for IRS8 and VSS for IRS8) Programmable deadtime lead, referenced to VSS. (IRS8 only) Logic ground (IRS8 only) High-side floating supply High-side gate drive output High-side floating supply return Low-side and logic fixed supply Low-side gate drive output Low-side return Lead Assignments IN V B 8 IN V B 8 SD 7 SD 7 COM V S COM V S 8-Lead PDIP 8-Lead SOIC IRS8PbF IRS8SPbF IN IN SD V B SD V B VSS VSS DT V S DT V S COM COM Lead PDIP -Lead SOIC IRS8PbF IRS8SPbF
6 IN SD IN() IN() % % ton t r toff tf Figure. Input/Output Timing Diagram 9% 9% % % Figure. Switching Time Waveform Definitions IN % % SD % DT - % 9% t sd 9% DT - 9% MDT= DT - % - DT - Figure. Shutdown Waveform Definitions Figure. Deadtime Waveform Definitions IN() IN () % % % MT MT 9% Figure. Delay Matching Waveform Definitions
7 T u r n - o n P r o p a g a t i o n D e l a y ( n s ) T u r n - o n P r o p a g a t i o n D e l a y ( n s ) 8 8 Figure A. Turn-On Propagation Delay Figure B. Turn-On Propagation Delay vs. Supply Voltage T u r n - o f f P r o p a g a t i o n D e l a y ( n s ) Figure 7A. Turn-Off Propagation Delay T u r n - o f f P r o p a g a t i o n D e l a y ( n s ) 7 8 Figure 7B. Turn-Off Propagation Delay vs. Supply Voltage 7
8 S D P r o p a g a t i o n D e l a y ( n s ) S D P r o p a g a t i o n D e l a y ( n s ) 8 Figure 8A. SD Propagation Delay Figure 8B. SD Propagation Delay vs. Supply Voltage Turn-On Rise Time (ns ) 8 Max Turn-On Rise Time (ns ) Figure 9A. Turn-On Rise Time vs. Temperature Figure 9B. Turn-On Rise Time vs. Supply Voltage 8
9 8 8 Turn-Off Fall Time (ns ) Typ Turn-Off Fall Time (ns ) Figure A. Turn-Off Fall Time vs. Temperature 8 Figure B. Turn-Off Fall Time vs. Supply Voltage 9 9 D e a d t i m e ( n s ) 7 Min. D e a d t i m e ( n s ) 7 Min Figure A. Deadtime 8 Figure B. Deadtime vs. Supply Voltage 9
10 7 Deadtime (µs) Min. R DT (KΩ) Input Voltage (V) Min Figure C. Deadtime vs. R DT Figure A. Logic "" Input Voltage Input Voltage (V) 8 Logic "" Input Voltage (V) V BAIS Figure B. Logic "" Input Voltage vs. Supply Voltage Figure A. Logic "" Input Voltage
11 Logic "" Input Voltage (V) 8 SD Input threshold (+) (V) Figure B. Logic "" Input Voltage vs. Supply Voltage Figure A. A. SD input positive going threshold (+) SD Input threshold (+) (V) 8 SD Input Negative Going Threshold (V) Figure B. SD input positive going threshold (+) vs. Supply Voltage Figure A. SD Input Negative Going Threshold
12 SD Input Negative Going Threshold (V) 8 High Level Output Voltage (V) Figure B. SD Input Negative Going Threshold vs. Supply Voltage Figure A. High Level Output Voltage (Io = ma) High Level Output Voltage (V).... Max.. 8 V BIAS Low Level Output (V) Figure B. High Level Output Voltage vs. Supply Voltage (Io = ma) Figure 7A. Low Level Output
13 Low Level Output (V) O f f s e t S u p p l y L e a k a g e C u r r e n t (µa) Figure 7B. Low Level Output vs. Supply Voltage Figure 8A. Offset Supply Leakage Current Offset Supply Leakage Current (µa) V B S S u p p l y C u r r e n t (µ A ) Min V B Boost Voltage (V) Figure 8B. Offset Supply Leakage Current vs. V B Boost Voltage Figure 9A. V BS Supply Current
14 V BS Supply Current (µa) Min. Supply Current (ma) V C C Min V BS Floating Figure 9B. V BS Supply Current vs. V BS Floating Supply Voltage Figure A. Supply Current Supply Current (ma) 8 Min L o g i c " " I n p u t B i a s C u r r e n t (µa ) Figure B. Supply Current vs. Supply Voltage Figure A. Logic "" Input Bias Current
15 Logic "" Input Bias Current (µa) 8 8 Figure B. Logic "" Input Bias Current vs. Supply Voltage Lo gic " " Input Bia s Current ( µa) Max Temperature ( C) Figure A. Logic Input Bias Curremt Logic "" Input Bias C urr ent (µa) Max 8 Figure Figure B. B. Logic Logic "" Input Input Bias Bias Current Curremt vs. Voltage and V BS UV Threshold (+) (V) Min Figure. and V BS Undervoltage Threshold (+)
16 and V BS UVThreshold (-) (V) Min Output Source Current (A) Min Figure. and V BS Undervoltage Threshold (-) Figure A. Output Source Current. Output Source Current (A) Min. 8 Output Sink Current (A).... Min Figure B. Output Source Current vs. Supply Voltage Figure A. Output Sink Current
17 Output Sink Current (A) Min. Temprature ( o C) 8 v 7v v 8 Figure B. Output Sink Current vs. Supply Voltage Figure 7. IRS8 vs. Frequency (IRFBC), = Ω, = V 8 v 7v v 8 v 7v v Figure 8. IRS8 vs. Frequency (IRFBC), = Ω, = V Figure 9. IRS8 vs. Frequency (IRFBC), = Ω, = V 7
18 v 7v v 8 8 v 7v v Figure. IRS8 vs. Frequency (IRFPE), = W, = V Figure. IRS8 vs. Frequency (IRFBC), = W, = V 8 v 7v v 8 v 7v v Figure. IRS8 vs. Frequency (IRFBC), = W, = V Figure. IRS8 vs. Frequency (IRFBC), = W, = V 8
19 v 7v 8 v 8 v 7v v Figure. IRS8 vs. Frequency (IRFPE), = W, = V Figure. IRS8s vs. Frequency (IRFBC), = W, = V v 7v 8 v 7v v 8 v Figure. IRS8s vs. Frequency (IRFBC), = W, = V Figure 7. IRS8s vs. Frequency (IRFBC), = W, = V 9
20 V 7V V Tempreture ( o C) 8 8 v 7v v Figure 8. IRS8s vs. Frequency (IRFPE), = W, = V Figure 9. IRS8s vs. Frequency (IRFBC), = W, = V 8 Figure. IRS8s vs. Frequency (IRFBC), = W, = V v 7v v 8 Figure. IRS8s vs. Frequency (IRFBC), = W, = V v 7v v
21 v 7v v 8 Figure. IRS8s vs. Frequency (IRFPE), = W, = V
22 Cast Outlines 8-Lead PDIP - - (MS-AB) A E X D 8 7 e B H. [.] A. [.] X.7 [.] FOOTPRINT 8X.7 [.8] 8X.78 [.7] DIM INC HES MILLIMETERS MIN MAX MIN MAX A A b.... c D E e. BASIC.7 BASIC e. BASIC. BASIC H K L y e A C y K x 8X b A. [.] C A B. [.] 8X L 7 8X c NOTES:. DIMENSIONING & TOLERANCING PER ASME Y.M-99.. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS ARE SWN IN MILLIMETERS [INCHES].. OUTLINE CONFORMS TO JEDEC OUTLINE MS-AA. 8-Lead SOIC DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE (MS-AA)
23 -Lead PDIP - - (MS-AC) -Lead SOIC (narrow body) -9 - (MS-AB)
24 Tape & Reel 8-lead SOIC ADED TA PE FEED DIRECTION B A H D F C N OTE : CONTROLLING D IMENSION IN MM E G CARRIER TAPE DIMENSION FOR 8SOICN M etr ic Im p erial Code Min Max Min Max A B.9... C D E F G. n/a.9 n/a H F D E C B A G H REEL DIMENSIONS FOR 8SOICN M etr ic Im p erial Code Min Max Min Max A B C D E F n/a 8. n/a.7 G H
25 Tape & Reel -lead SOIC ADED TA PE FEED DIRECTION B A H D F C N OTE : CONTROLLING D IMENSION IN MM E G CARRIER TAPE DIMENSION FOR SOICN M etr ic Im p erial Code Min Max Min Max A B.9... C D E.... F G. n/a.9 n/a H F D E C B A G H REEL DIMENSIONS FOR SO IC N M etr ic Im p erial Code Min Max Min Max A B C D E F n/a. n/a.88 G H
26 LEADFREE PART MARKING INFORMATION Part number Date code IRSxxxxx YWW? IR logo Pin Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - digit SPN code) Assembly site code Per SCOP - ORDER INFORMATION 8-Lead PDIP IRS8PbF -Lead PDIP IRS8PbF 8-Lead SOIC IRS8SPbF -Lead SOIC IRS8SPbF 8-Lead SOIC Tape & Reel IRS8STRPbF -Lead SOIC Tape & Reel IRS8STRPbF The SOIC-8 is MSL qualified. The SOIC- is MSL qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at IR WORLD HEADQUARTERS: Kansas St., El Segundo, California 9 Tel: () -7 Data and specifications subject to change without notice. /7/
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