GRETINA. Electronics. Auxiliary Detector Workshop. Sergio Zimmermann LBNL. Auxiliary Detectors Workshop. January 28, 2006

Transcription

1 GRETINA Auxiliary Detector Workshop Electronics Sergio Zimmermann LBNL 1

2 Outline Electronic Interface Options Digitizers Trigger/Timing System Grounding and Shielding Summary 2

3 Interface Options Three options Ethernet readout: connects directly to the switch Use standard Gretina digitizers: the auxiliary detectors connect directly to GRETINA digitizers Digital data stream: example: FERA interface (Mario s talk) Presently, the only interface that is funded and is part of the requirement document is the Ethernet Readout 3

4 System Local Trigger and Timing Module Digitizer Crystal Modules Pre amplifier Global Trigger and Timing Module Readout Computer 30 Crystals 2.2 MB/s 66 MB/s Processing Farm Network Switch 75 dual Processors 6.9 MB/s Aux. Det. Trigger Workstations, Servers Aux. Det. Data Data Storage 2.3 MB/s + Aux. Data 4

5 Ethernet Readout Is part of the requirement document and it will be part of GRETINA Requirement 2.1.1: Readout Data from the auxiliary detectors shall be combined with the GRETINA data (Ethernet switch) Requirement 2.1.2: Trigger The GRETINA trigger system shall provide 8 digital inputs with any logical combination [look up table]. 8 digital outputs that inform when a Level 2 trigger occurred [etc.] 5

6 Ethernet Readout Requirement 2.1.3: Time Stamp The auxiliary detectors shall provide their own time stamp with the same resolution as the GRETINA time stamp. Requirement 2.1.4: Clock Synchronization and Verification GRETINA shall provide clock and reset signals to synchronize the auxiliary detectors with GRETINA. Verification methods shall be implemented to verify that the auxiliary detector is properly synchronized with GRETINA. 6

7 Ethernet Readout Example: The auxiliary detectors have a circular buffer where data is stored. The buffer depth (size of the memory) allows for the GRETINA and Auxiliary Detector latency. GRETINA (or the auxiliary detector) provides a trigger. The data is removed from the circular buffer and moved to the readout buffer. If no trigger, the data is overwritten on the circular buffer. After some reasonable amount of data is stored in the readout buffer, it is transmitted to the GRETINA DAQ (through Ethernet). 7

8 Standard GRETINA Digitizers The auxiliary detectors are connected to the GRETINA digitizers Most likely, the same timing (with time stamp), trigger and readout applies. The data is readout by the same type of CPU readout controller and sent to the switch Information we will need: Number of channels Voltage range Rise time Pulse shape Condition for trigger, etc. Also, more in Mario s talk 8

9 System Local Trigger and Timing Module Digitizer Crystal Modules Pre amplifier Global Trigger and Timing Module Readout Computer 30 Crystals 2.2 MB/s 66 MB/s Processing Farm Network Switch 75 dual Processors 6.9 MB/s Aux. Det. Trigger Workstations, Servers Aux. Det. Data Data Storage 2.3 MB/s + Aux. Data 9

10 Digitizers 10

11 Digitizers Preamp/adc 100 MHz FPGA FIFO VME Preamp/adc 10 Inputs Preamp/adc Serial Interface Trigger/Timing Digital Inputs/Outputs Control and monitor registers External synch 100 MHz clock Clock distribution & local oscillator When the digitizer received a trigger, it transfer the data from a circular buffer (inside the FPGA) to the FIFO. If not, the data is overwritten. When the FIFO has data (say, half full), the Crate Controller readouts out the data. 11

12 Digitizers Data processing in FPGA Leading Edge Discrimination: yn = xn xn k (differentiation) yn = (xn + xn 2) + xn 1<<1 ( 4, Gaussian filtering) Threshold comparison LED time Constant Fraction Discrimination: yn = xn xn k (differentiation) yn = (xn + xn 2) + xn 1<<1 ( 2, Gaussian filtering) yn = xn k fxn (constant fraction, f is an attenuation factor) Zero crossing comparison CFD time Trapezoidal filter and energy determination (V.T Jordanov, G.F. Knoll, NIM A345 (1994) ) yn = yn 1 + ( (xn + xn 2m k) ) (xn m + xn m k) ) Maximum tracking energy Pole Zero correction yn = xn + In /t (where t is the pre amplifier time constant) In = In 1 + xn 12

13 Digitizers Flow of data in the DSP board From ADC Delay 1 k Leading Edge Disc. Delay 2 m Delay 3 k LED Time Const. Fraction Disc. Energy P/Z Delay 4 m CFD Time CFD Amplitudes Energy 13

14 Digitizers Detector Digitizer Connection Cable Connector 5 T wis t e d p air ( 2 6 A W G) wit h f o il s h ie ld ing Dr ain wir e f o r c ab le s h ie ld ing Fo il and b r aid s h ie ld ing J ac k e t 5. Dr a in wir e f o r ind ivid ua l t wis t e d pa ir s Centi Line 2D from ITT/Cannon Proper pin assignment reduces the crosstalk 14

15 Trigger/Timing System Transmit data and timing information from Trigger/Timing units to/from Digitizers GLOBAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER used to recover clock and data sent from Global Trigger Unit Single Pair: Clock and Data XTAL OSC FULL DUPLEX Differential Twisted Pair 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X FULL DUPLEX Differential Twisted Pair 15

16 Trigger/Timing System The following trigger algorithms are planned at this point (and are part of the requirements) Multiplicity: A programmable number of energy over threshold occurs inside some walking time window. Energy: Segment and/or central contact energy at lower resolution (which appears earlier in the digitizer ). It can use the energy of a segment or central contact or the sum of energies of segments and central contacts. When this energy falls within some pre set window (within some low and high energy limit) a Level 2 trigger is generated. 16

17 Trigger/Timing System Pattern distribution: GRETINA shall trigger if the Trigger System detects coincidence of gamma rays energy at lower resolution above threshold in any two pre programmed central contact of the crystals. Auxiliary detector trigger: GRETINA will receive an external trigger within the pipeline depth [presently at 20 µs, goal 100 µs]. 17

18 Trigger/Timing System Serial Data 100Mb/s FPGA Serializers Delay Line Phase Detector DCM BLOCK CLK0 DATA CLOCK CLK90 CLK180 CLK270 FREQ/PHASE CORRECTION Specifications Freq: 100MHz Pull: +/ 70ppm Jitter: 5ps RMS 100MHz LOOP FILTER UP DOWN 18

19 Grounding and Shielding Detector modules Isolated from support and from other modules Reduce capacitance to support structure One common safety ground for each module, no other connection to ground. Detector enclosure (iridite) provides Faraday cage Detector power supplies and bias Each crystal has its own set of floating supplies Power: twisted pair, shielded cable Bias: high voltage coaxial All electronics for one detector module is assembled close together Signals: optical or twisted shielded pairs Clean AC power 19

20 Grounding and Shielding Need to coordinate the grounding and shielding of the auxiliary detectors with GRETINA s grounding and shielding. We have documented GRETINA s grounding and shielding. 20