Digital Logic, Algorithms, and Functions for the CEBAF Upgrade LLRF System Hai Dong, Curt Hovater, John Musson, and Tomasz Plawski

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1 Digital Logic, Algorithms, and Functions for the CEBAF Upgrade LLRF System Hai Dong, Curt Hovater, John Musson, and Tomasz Plawski Introduction: The CEBAF upgrade Low Level Radio Frequency (LLRF) control system is being designed to incorporate digital feedback. To implement a digital feedback control system one may use a Digital Signal Processor (DSP) or embed the control functions within a dense programmable logic device (PLD) such as a field programmable gate array (FPGA). We have decided for speed reasons (DSP is too slow for our application) to use an FPGA. Control algorithms implemented within a DSP would have delays of 10 of µseconds while an embedded approach using an FPGA would be approximately one µsecond. FPGA s come in all shapes, sizes and costs depending on the number of logic gates and speed needed to implement a design. To determine the size of the FPGA needed for the system we have designed a generic digital controller with the algorithms and functions needed for LLRF control. With this information we can then determine the number of the logic gates needed and hence the size and cost of the FPGA. The purpose of the digital section of the Low Level Radio Frequency (LLRF) Control board is to regulate the magnitude and phase of the cavity RF to a controlled set point. The input to the digital section is from an analog-to-digital converter (ADC) that is driven by the down converted cavity signal (70MHz) which is clocked at 60 MHz. The digital controller then compares this to set points and processes the error signal such that a correction can be applied to the cavity. The correction signal from the FPGA then drives a Dual I/Q digital-to-analog (DAC) converter running at 60 MHz. The DACs in turn drive the quadrature modulator and is then upconverted to the cavity frequency. The delay through the digital section is being driven by the gains needed to reduce the cavity microphonic fluctuations. Since the present analog LLRF system has a bandwidth of 1 MHz we anticipate the digital controller to need a similar bandwidth and hence the target delay of 1 us. This is effectively driving the high clock frequencies and our concern for the algorithm delays. The following will be described in this technote. System Implementation FPGA Detailed Description o I/Q Demodulation o FIR o Rotation Matrix o PID PID Proportional PID Integral PID Differential 1

2 System Implementation The digital section (controller) computes the functions shown in Figure 1. The I/Q Demodulator separates the signal from the ADC to Q (in phase) and I (90 0 Phase) components. The Low pass finite impulse response (FIR) filters followed remove the high frequency noise of the I/Q signals and any energy from the any close cavity modes. The Rotation Matrix changes the I/Q angles to that specified by the user. The I/Q signals with corrected angle enter proportional, integral, and differential (PID) controller to have their amplitude regulated to the set points. The feed forward circuit adjusts the signals to compensate for repeatable error sources in the system. Finally. The scaling circuit puts the signals into required DAC format. Figure 1. LLRF DIGITAL FUNCTIONAL BLOCK 2

3 These functions will be implemented in a FPGA integrated circuit (IC). The FPGA contains basic electronic logic elements (LE) to realize the digital circuits (functions). The more LE s an FPGA has, the more circuits can be realized. Since the cost is proportional to the number of LE s, a study was made to determine the most cost effective FPGA size. The study involves trading off the number of LE s needed and the propagation delay from the ADC input to the DAC output which is specified at less than one microseconds. The FPGA will be clocked at 60 MHz. The circuits to implement these functions are described in detail in subsequent sections. Their size and delay are summarized in the Table 1. The delay shown in the table is owing to the pipelining that enables the circuits to run at 60 MHz. If the functions were implemented using an application specific integrated circuit (ASIC) instead of FPGA, the delay could be reduced by approximately about 10 clock cycles. However an ASIC is cost prohibitive (see ASIC addendum). The table also shows the time taken by TI 6711 floating point DSP to execute the functions. A digital output bit is toggled before and after a function is executed to indicate the time taken for that function. Function Number of LE Delay (# of clock) Delay (us) Decimation (# of DAC input) DSP Delay (us) I/Q Demodulator x.4 FIR (10 tap) 2 x x 6.8 Rotation Matrix x 1.44 PID 2 x x 1.28 Feed Forward 2 x x.38 DAC Scaling 2 x x.38 TOTAL Table 1: Estimate Size and Delay for Digital Control (FPGA size) 3

4 Figure 2 shows the block diagram for the digital portion of the LLRF control board. The functions are to be implemented using an Altera APEX 20K600 or equivalent. The Intersil shown is a digital down converter (DDC) that has a I/Q Demodulator and FIR filters that can have up to 255 taps. It is included to compare the trade off between using the DDC and coding the I/Q Demodulator and FIR into the FPGA. Two dual port (DP) random access memories (RAM) provide the Sine and Cosine look up tables for the I/Q Demodulator. The others two DP RAM contain the compensation tables for the feed forward circuits. DP RAM is used to allow the TI6711 Digital Signal Processor (DSP) to access and load the tables. The feed forward values, I/Q set point, and the rotation angle value for the rotation matrix are computed by the DSP. The DSP is provided with 256Kx32 FLASH and 4Mx32 SDRAM for program and data storage and 32 digital input and output for testing and possibly drive stepper motors or Piezo tuners for resonance control. TI Code Composer Studio will be used to developed program and algorithms for the DSP. VME interface to support EPICS is implemented with another DP RAM and the FPGA. Figure 2: LLRF Board Block Diagram 4

5 In addition to size, the number of I/O pins was considered in choosing the FPGA. Table 2 shows the I/O required. APEX 20K600 I/O count (488 available I/O pins for 652 pins BGA) Functions # of BiDir # of Input # of Output I, Q from DDC 34 Demod Sine Table Demod Cos Table Table for Q Feedforward Table for I Feedforward I DAC 16 Q DAC 16 DSP VME ADC 15 Test Point 16 Total Grand Total 376 Table 2: FPGA I/O Count 5

6 FPGA Detailed Description I/Q Demodulation: The I/Q Demodulation decomposes the RF input from the ADC into it real (Q) and imaginary (I) component as shown in Figure 3. The I/Q demodulator multiplies the input with sine and cosine sinusoidal references stored in the DP RAM to create I and Q respectively. Figure 3: I/Q Demodulator 6

7 The I/Q demodulator circuit along with its size and delay is shown in Figure 4. The registers (reg.) shown in the figure are necessary to get the circuit to run at 60 MHz in the FPGA. If the circuit is implemented in an ASIC, the input registers can be eliminated and the multiply can be done in one stage instead of two. Figure 4: I/Q Demodulator Circuit 7

8 FIR: The FIR filter adds the weighted sum (depends on number of taps) of the most current ADC input. A FIR that has 10 taps multiplies the 10 most recent inputs each with a different coefficient and then adds the results. The value of the coefficients, the number of taps, and the sampling rate (rate at which the data comes in) determines the characteristic of the filter. The obvious implementation would be to have 10 multipliers and an adder as shown in Figure 5. The advantage with this approach is that it can keep up with the ADC data rate. The disadvantage is the size. The size is dependent on the number of taps and it is too large to practically implement with an FPGA. A brute force 10 taps FIR is a candidate for ASIC implementation. Figure 5: FIR 10 Tap Brute Force Implementation 8

9 A practical approach to implement a FIR filter is shown in Figure 6. This multiply and accumulate (MAC) performs the multiplications serially instead of in parallel. The result of a multiplication is added to a running sum that has a value of 0 before the first multiply. Since the circuit can only do one multiply and add for each clock, the number of taps determines the number of clock cycles needed to complete tallying all inputs. For example, a FIR with 10 taps will take 10 clocks to produce an output. Since the inputs cannot change during the process, the circuit is essentially decimating the input by the number of taps of the FIR filter if the FPGA clock is the same as the ADC clock. In other words, if the FPGA clock is less than the number of taps times the ADC clock, the circuit will not be able to keep up with the ADC data rate and can only accept every x sample for an x number of taps. The advantage of this approach is it size. The size does not vary by much with the number of taps and it can be realize with an FGPA. Figure 6: FIR MAC Implementation 9

10 Rotation Matrix: The rotation matrix as shown in Figure 7 rotates I/Q signals by the angle specified by the user (EPICS). Figure 7: Rotation Matrix 10

11 Figure 8 shows the rotation matrix circuit. Since the user angle specification does not occur on a clock-by-clock basis, the sine and cosine tables will be stored in the DSP memory. The depth and width of the table is determine by the following specification: Range of 0 to 360 degree rotation Resolution of.1 degree Accuracy of.01 degree The formulas used are: Table Depth = Range/Resolution = 360/.1 = 3600 locations = 12 address bits. Table Width =ln -1 2(location/accuracy)= ln -1 2(3600/.01) = 19 data bits. Figure 8: Rotation Matrix Circuit 11

12 PID: The PID controller shown in Figure 9 minimizes the difference (~ 1/G) between the signal from rotation matrix (feed back from cavity) and a set point specified by the users (EPICS). The difference (error) goes into proportional, integral, and differential circuits. The outputs of these circuits are summed to produce the overall PID output. Figure 9: PID Controller Circuit 12

13 PID Proportional: The proportional is used to provide sufficient RF drive so that the signal feedback is the same as the set point. The proportional circuit shown in Figure 10 multiplies the error by a constant (Pgain) settable by the DSP. The width of this constant is determine by the specification that the proportional gain s range is from 0 to 100 db. The formulas used are: Voltage Gain = log -1 (100 db / 20) = Width = ln -1 2(Voltage Gain) = 17 bits The resolution is Resolution = 1/ 20(log 2 17 ) =.0098 db Figure 10: PID Proportional Circuit 13

14 PID Integral: The Integral is used to add long-term precision to a control loop and to reduce offsets. As shown in Figure 11, the integral keeps a running sum (Pid Istate) and multiplies the sum by a constant (IGain). The sum is limited to a Maximum and Minimum value to prevent saturation and cause instability. The width of Igain is determined by the specification that the integral s range is from 0 to 100 ms and a 1us resolution. The formulas used are: IGain = 100 ms / 1us = 100,000 Width = ln -1 2(100,000) = 17 bits Figure 11: PID Integral Circuit 14

15 PID Differential: The differential is used to predict the future behavior of the cavities and conditions the RF drive so that feed back signal equals the set point sooner. As shown in Figure 12, the circuit subtracts the current error to the previous error and multiplies the difference by a constant (Pid Dgain). The width of Pid Dgain is chosen to be 16 bits since there is yet a specification for the differential gain. Providing differential feedback is the most difficult for a PID controller and is used only when the system is very well known. It may not be needed by our control system. Figure 12: PID Differential Circuit 15

16 ASIC Addendum This addendum compares and contrasts ASIC to FPGA. ASIC and FPGA are both made to realize digital circuits. However, the way that the circuits are realized is different between the two. An FPGA contains fundamental building blocks that will be connected via programmable switches to realize more complex digital circuits. This switch-setting matrix can be loaded into the FPGA either by a computer or from an electrical erasable programmable memory (EEPROM). Changes in a design only require recompiling the design and reload the matrix. The ASIC, on the other hand, contains premade transistors on a wafer (die). The transistors are connected with wires (instead of programmable switches) to realize digital circuits. Building an ASIC involves making masks that contains wire traces for the wafer. A mistake in the design will require remaking the die (a new chip). This fundamental difference manifests other differences. An ASIC will cost more for low volume production. Typically it will cost more than $100,000 for non-recurring engineering (NRE) and hundreds or tens of dollars per chip thereafter for high volume production that is vendors specific. A change in the design will typically cost less than $100,000 for NRE with the same vendor. An FPGA, on the other hand, will cost in the hundreds or several thousands per chip. A change in the design does not cost anything if the new design will still fit in the current FPGA. ASIC s are faster than FPGA s. In the ASIC the circuits are built by connecting transistors with wires. This architecture allows circuits to realize with fewer transistors that translate to smaller capacitive load and propagation delay. Moreover wires inherently have lower propagation delay than programmable switches. The speed improvement of 3 to 1 can be realized with the ASIC for the same die technology. ASIC s are denser than the FPGA s. For a given die size, more circuitries can be realized with an ASIC. There are two reasons for this. First, many of the wires that crisscrossing the FPGA die do not get use for a given design. Second, not all the circuitries contain in the building blocks will be used for a given design. In an ASIC, the wires and transistors are only connected as needed. The FPGA described in this paper, the DPRAM, and possibly the DSP can all be integrated into an ASIC. In summary, ASIC is suited for designs that require high speed processing, have circuit board size constraint, and high volume productions. 16