Development of Pixel Detectors for the Inner Tracker Upgrade of the ATLAS Experiment

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1 Development of Pixel Detectors for the Inner Tracker Upgrade of the ATLAS Experiment Natascha Savić L. Bergbreiter, J. Breuer, A. Macchiolo, R. Nisius, S. Terzo IMPRS, Munich # Franz Dinkelacker Li-S batteries Proseminar Energy Materials

2 Overview Introduction to the ATLAS Pixel Detector Motivation Experimental investigations of pixel modules charge collection measurements in the laboratory efficiency measurement during test beam campaigns Summary and Outlook 2

3 The ATLAS Pixel Detector The ATLAS Detector The Pixel Module Silicon sensor (thickness ~3 µm) The Pixel Detector Read-out chip (thickness ~2 µm) Sensor and read-out chip connected via bump bonds 3 March 11th 216

particles traverse the silicon sensors and release electrons and holes in the

4 What is a Pixel Detector? Read-out chip Bump bond Sensor negative voltage applied on the sensor backside particles traverse the silicon sensors and release electrons and holes in the depleted bulk which move to the electrodes è signal is created sensor and read-out chip are interconnected through solder bump bonds è signal is processed 4

5 Conditions before 213 Cross section of the pixel system 2 p-p collisions ever 5 ns 5

6 Conditions in 213 Insertable B-Layer (IBL): new pixel layer at 3.2 cm from the beamline 25 p-p collisions ever 25 ns 6

Conditions from 224 In view of the high luminosity phase of the LHC in 224 226 the

radiation for the ATLAS detector 14-2 pile-up events Pixel layers 1 to 4 layer 4

7 Conditions from 224 In view of the high luminosity phase of the LHC in the ATLAS experiment will undergo a major upgrade of its tracker system Expected radiation for the ATLAS detector 14-2 pile-up events Pixel layers 1 to 4 layer 4 layer 3 layer 2 layer 1 ~ 1-1.4x1 16 n eq cm -2 Scale of expected fluences in the different layers 7

frontside defect Sensor backside defect d c Increase of the leakage current increase of the

8 What happens to the pixel detector during irradiation? Charge trapping defects act as trapping centers è reduction of collected charge Sensor frontside defect Sensor backside defect d c Increase of the leakage current increase of the power consumption (P ~ I ~ ϕ è P ~ I x U ) è strong cooling requirements increase of the noise 1x1 15 n eq /cm -2 2x1 15 n eq /cm -2 8

9 Motivation Goal: radiation hardness of the innermost silicon detector è optimization of hit efficiency, leakage current and power dissipation i. reduction of the sensor thickness è higher electric field and smaller charge collection distance lead to less charge trapping and hence higher efficiency è lower operation voltage and thus leakage current lead to less power dissipation ii. improvement of the pixel design è increasing efficiencies of pixel cells è higher granularity Experimental investigations i. charge collection measurements in the laboratory ii. efficiency measurements during test beam campaigns 9

10 Sensors with different active thicknesses at MPP 1

11 Thinning production process flow of sensors sensor active thickness: 75 to 2 µm afterwards bump bonded to chips 11

12 Laboratory measurements Charge collection (CC) increasing fluence Samples : modules with 2 µm thick sensors irradiated to different fluences Method : 9 Sr radioactive β-source with external trigger via scintillator Cooling : in climate chamber down to -4 C sensor temperature 12

13 Laboratory measurements Charge collection (CC) Highest CC for 1 and 15 µm thin sensors 3 Samples : irradiated modules with sensor thicknesses from 75 to 285 µm 13

Efficiencies for different sensor thicknesses and irradiations 97.

14 Efficiencies for different thicknesses Efficiency measurements with the EUDET telescope at : Hit efficiency Efficiency in in % 1 1) DESY in Hamburg with 4 GeV electrons 2) SpS at CERN with 12 GeV pions using irradiated modules with sensor thickness from 1 to 27 µm Efficiencies for different sensor thicknesses and irradiations 97.1 % efficiency at just 3 V increasing thickness fluence ~ const FE-I4 1um, 5e15 FE-I4 15um, 4e15 FE-I4 2um, 6e15 FE-I4 27um, 5e Voltage Thinner sensors show higher charge collection and hit efficiency after irradiation. 14

15 Optimization of biasing structures and pixel pitches 15

Optimization of biasing structures and pixel pitches Cut-off

allowing for a smooth potential drop from the pixels to the

Bias rail Implant Aluminium Bump pad Biasing structure is

16 Optimization of biasing structures and pixel pitches Cut-off sensor surface Guard rings (protect the sensor edges by allowing for a smooth potential drop from the pixels to the cutting edge) Biasing ring Punch-through structure Bias dot Bias rail Implant Aluminium Bump pad Biasing structure is implemented in order to test the sensor before interconnecting to the chip 16

center Biasline over punch- through dot Modified 25x5 µm² pixel individual

17 Optimization of biasing structures and pixel pitches MPP designed sensors of 27 µm thickness fabricated and bonded to chips Standard punch- through Biasline over center Biasline over punch- through dot Modified 25x5 µm² pixel individual punch-through (p-t) Standard 5x25 µm² pixel Common punch- through common p-t 17 March 11th 216

18 Track Short y Side[µm] Track y [µm] Track Short y Side[µm] Efficiency Pixel Map DUT 2 Geometry 3 Comparison of performance of different p-t designs In-pixel hit efficiency Long Track Side x [µm] x25 µm² pitch Efficiency Pixel Map DUT 2 Geometry 4 Track x [µm] Long Track Side x [µm] [µm] Irradiated at 5x1 15 n eq /cm 2, U= 5 V Efficiency [%] Efficiency [%] Efficiency [%] 1 % hit efficiency before irradiation all three p-t designs implemented in one module Test beam analysis shows better hit efficiency when the p-t and bias rail is over-imposed to the pixel implant. 18

Track Short y Side[µm] Track y [µm] Track Short y Side[µm] Efficiency Pixel Map DUT 2 Geometry 3 Comparison of performance of different p-t designs In-pixel hit efficiency Efficiency Pixel Map DUT 2

19 Track Short y Side[µm] Track y [µm] Track Short y Side[µm] Efficiency Pixel Map DUT 2 Geometry 3 Comparison of performance of different p-t designs In-pixel hit efficiency Efficiency Pixel Map DUT 2 Geometry 4 Irradiated at 5x1 15 n eq /cm 2, U= 5 V cut-out of a 5x5 µm² pitch Long Track Side x [µm] x25 µm² pitch Track x [µm] Long Track Side x [µm] [µm] ~ 1 % hit efficiency before irradiation all three p-t designs implemented in one module Test beam analysis shows better hit efficiency when the p-t and bias rail are overimposed to the pixel implant. Efficiency [%] Efficiency [%] Efficiency [%] 19

Novel p-t design for 25x5 µm 2 pixel In-pixel hit efficiency Short Side[µm] Track y [µm] 25 25x5 µm² pitch

1 2 3 4 Track x [µm] 1 1.9.8.7.6.5 5.4.3.2.1 Efficiency [%] Efficiency in % Comparison Efficiency of

fluence 5x1 15 Δε =.3 % Common p-t for Biasline over p-t dot Standard p-t design 98.

20 Novel p-t design for 25x5 µm 2 pixel In-pixel hit efficiency Short Side[µm] Track y [µm] 25 25x5 µm² pitch Efficiency Pixel Map DUT 21 Geometry Long Side [µm] Track x [µm] Efficiency [%] Efficiency in % Comparison Efficiency of different hit efficiency punch-through of designs different in pixels, p-t 5e15 designs fluence 5x1 15 Δε =.3 % Common p-t for Biasline over p-t dot Standard p-t design 98. % Biasline over center Voltage Improved hit efficiency for the biasline over the p-t dot and common p-t after irradiation. 2

Estimation of hit efficiency for a 25x1 µm 2 pitch at a fluence of 3x1 15 n eq cm -2 Hit efficiency at 3x1 15 n eq cm -2 25x5 µm 2 25x1 µm 2 Inefficiencies appear at the edges of the pixel left:

21 Estimation of hit efficiency for a 25x1 µm 2 pitch at a fluence of 3x1 15 n eq cm -2 Hit efficiency at 3x1 15 n eq cm -2 25x5 µm 2 25x1 µm 2 Inefficiencies appear at the edges of the pixel left: first 4 µm show inefficiency caused by charge sharing right: last 6 µm show inefficiency caused by punch-through effective pitch of 25x1 µm 2 obtained by combining first 4 µm and last 6 µm of pixel cell example created to estimate a hit efficiency for the 25x1 µm 2 pitch Estimated hit efficiency for 25x1 µm 2 pitch at 5 V : 96.4 % (99.8 % for 25x5 µm 2 pitch and 96.5 % for standard 5x25 µm 2 pitch and standard p-t at 3x1 15 n eq cm -2 ) 21

) design 1 5x5 design 2 25x1 5 25x1 µm² pixel pitch design based on the existing prototype with 25x5 µm² pitch (results

22 New design for sensors with small pixel pitch 5x5 µm 2 and 25x1 µm 2 pixel pitches foreseen for a new radiation hard chip with a regular 5x5 µm 2 grid p-t design combination of biasline over p-t dot and common p-t (best performig ones!) design 1 5x5 design 2 25x1 5 25x1 µm² pixel pitch design based on the existing prototype with 25x5 µm² pitch (results shown before) 5 1 SOI wafers of new production at MPG-HLL with 1 and 15 µm active thickness successfully tested 25 2 UBM pad 22

23 Summary and Outlook Thin sensors 1 and 15 µm thick sensors show higher charge collection and hit efficiency 1 µm thick sensor reaches hit efficiency of up to 97.1 % after irradiation at n eq /cm 2 at just 3 V Investigations of new pixel cell design Improved hit efficiency for the biasline over the p-t and the common p- t with respect to the standard design after irradiation at n eq /cm 2 New MPG-HLL production Combines and implements new pixel cell design and best performing biasing structures on thinner sensors è Promising innovations of sensor design will be connected to the new ATLAS chips with a 5x5 grid and tested by the end of

24 Thank you for your attention! 24

Pixel sensors with different pitch layouts for ATLAS Phase-II upgrade

Pixel sensors with different pitch layouts for ATLAS Phase-II upgrade Different pitch layouts are considered for the pixel detector being designed for the ATLAS upgraded tracking system which will be operating