Precision Wide Range (3 na to 3 ma) High-Side Current Mirror ADL5315

Transcription

1 Precision Wide Range (3 na to 3 ma) High-Side Current Mirror FEATURES Accurately mirrors input current (: ratio) over 6 decades Linearity % from 3 na to 3 ma Stable mirror input voltage Voltage held V below supply using internal reference or can be set externally Adjustable input current limit 2.7 V to 8 V single-supply operation Miniature 8-lead LFCSP (2 mm 3 mm) APPLICATIONS Optical power monitoring from a single photodiode General voltage biasing with precision current monitoring Voltage-to-current conversion FUNCTIONAL BLOCK DIAGRAM VOLTAGE REFERENCE 2k 3 LIMITING NC 2 7 MIRROR : Figure. RLIM 6 VPOS GENERAL DESCRIPTION The is a wide input current range, precision high-side current mirror featuring a stable and user-adjustable input voltage. It is optimized for use with PIN photodiodes, but its flexibility and wide operating range make it suitable for a broad array of additional applications. Over the 3 na to 3 ma range, the current sourced from the pin is accurately mirrored with a : ratio and sourced from the output pin. In a typical photodiode application, the output drives a currentinput logarithmic amplifier to produce a linear-in-db output representing the optical power incident upon the photodiode. For linear voltage output, a single resistor to ground is all that is required. The photodiode anode can be connected to a high speed transimpedance amplifier for the extraction of the data stream. The voltage at the pin is temperature stable with respect to the voltage at the input pin, which it tracks. A temperature stable reference voltage is provided at the pin, which, when tied to, fixes the voltage at. V below VPOS. can also be driven from an external source. The input has very low input current and can be driven as low as the bottom rail, facilitating nonloading voltage-tocurrent conversion as well as minimizing dark current in photodiode applications. The also features adjustable input current limiting using an external resistor from RLIM to VPOS. The maximum current sourced by (and ) can be set between ma and 6 ma, beyond which the voltage at falls rapidly from its setpoint. Connecting RLIM directly to VPOS provides basic input short-circuit protection with the default current limit of 6 ma typical. The is available in a 2 mm 3 mm, 8-lead LFCSP and is specified for operation from C to +8 C. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... 2 Specifications... 3 Absolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions... Typical Performance Characteristics... 6 Theory of Operation... 9 Bias Control Interface... 9 Data Sheet Noise Performance... Mirror Response Time... Input Current Limiting... Applications... Average Power Monitoring... Translinear Log Amp Interfacing... 2 Extended Operating Range... 3 Using RLIM as a Secondary Monitor... 3 Characterization Methods... Evaluation Board... 6 Outline Dimensions... 7 Ordering Guide... 7 REVISION HISTORY 9/27 Rev. to Rev. A Changed CP-8- to CP Throughout Changes to Figure 2... Updated Outline Dimensions... 7 Changes to Ordering Guide... 7 /2 Revision : Initial Version Rev. A Page 2 of 7

3 SPECIFICATIONS VPOS = V, = V, I = 3 µa, TA = 2 C, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit MIRROR OUTPUT (Pin 8) Current Gain from to.99.. Current Gain from to C < TA < +8 C A/A Nonlinearity 3 na < IPD < 3 ma.2. % Small Signal Bandwidth I = 3 na khz I = 3 µa MHz Wideband Noise at IPDM I = 3 µa, CSET = 2.2 nf 2 na rms Specified Output Voltage Range VPOS V ROUT Product I = 3 µa 9 V MIRROR INPUT, VOLTAGE CONTROL (Pin ), (Pin 2), (Pin 3) Specified Input Current Range, I Flows from pin 3n 3m A Specified Voltage Range 2.7 V < VPOS < 6. V VPOS V 6. V < VPOS < 8 V VPOS 6. VPOS V Incremental Gain from to.2 V < < 7. V.98.2 V/V Incremental Input Resistance at =. V > GΩ Input Bias Current at =. V <3 pa Voltage, Relative to VPOS 2.7 V < VPOS < 8 V...97 V OVER PROTECTION Current Limit V drops to V, RLIM = Ω 6 ma V drops to V, RLIM = 3 kω ma POWER SUPPLY VPOS (Pin 6) Supply Voltage Range V Quiescent Current I = 3 µa ma I = 3 ma ma Rev. A Page 3 of 7

4 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage 8 V Input Current at 2 ma Internal Power Dissipation mw θja (Soldered Exposed Paddle) 8 C/W Maximum Junction Temperature 2 C Operating Temperature Range C to +8 C Storage Temperature Range 6 C to + C Lead Temperature (Soldering 6 sec) 3 C Data Sheet Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. A Page of 7

5 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW (Not to Scale) 7 NC 6 VPOS RLIM NOTES. NC = NO CONNECT. 2. EXPOSED PAD. INTERNALLY CONNECTED TO, SOLDER TO GROUND. Figure 2. 8-Lead LFCSP 69-2 Table 3. Pin Function Descriptions Pin No. Mnemonic Description Input Current. Pin sources current only. 2 Sets Voltage at (Gain = ). Range V to VPOS. V for VPOS < 6. V. For VPOS 6. V range, VPOS 6. V to VPOS V. Optional shielding of trace. 3 Reference Voltage for. Internally generated at VPOS. V through 2 kω. Can be shorted to for standard mirror operation. Analog Ground. RLIM External Resistor to VPOS. Sets current limit at from ma to 6 ma. ILIM = 8 V/(RLIM + 3 kω). 6 VPOS Positive Supply (2.7 V to 8. V). 7 N/C Optional Shielding of Trace. No connection to die. 8 Output Current. Mirrors current at with a gain of.. Sources current only. PADDLE Exposed Pad. Internally connected to, solder to ground. Rev. A Page of 7

6 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VPOS = V, V SET = V, VOUT = V, TA = 2 C, unless otherwise noted C C +2 C +7 C +8 C +2 C, +7 C, +8 C, C, C m m µ 2... I VS. I OUT, ALL VOLTAGE CONDITIONS m m µ LINEARITY (%).. µ µ I OUT (A) LINEARITY (%).. µ µ I OUT (A).. 2. µ µ µ m I (A) m V POS = 2.7V, V SET = V V POS = V, V SET = 2V V POS = V, V SET = V V POS = 8V, V SET = 2V V POS = 8V, V SET = V µ µ µ m m I (A) 69-6 Figure 3. Linearity vs. I for Multiple Temperatures, Normalized to 2 C and I = 3 µa Figure 6. Linearity vs. I for Multiple Supply Conditions, Normalized to VPOS = V, = V, and I = 3 µa 3 2 C +2 C +8 C 2 LINEARITY (%) 2 3 µ µ µ m I (A) m 69-2 V VARIATION (mv) C, V POS = 2.7V, V SET = V C, V POS = V, V SET = V C, V POS = V, V SET = V +2 C, V POS = 2.7V, V SET = V +2 C, V POS = V, V SET = V +2 C, V POS = V, V SET = V +8 C, V POS = 2.7V, V SET = V +8 C, V POS = V, V SET = V +8 C, V POS = V, V SET = V µ µ µ m I (A) m 69- Figure. Linearity vs. I for Multiple Temperatures and Devices Normalized to 2 C and I = 3 µa 3. Figure 7. V Variation vs. I for Multiple Temperatures and Voltage, Normalized to VPOS = V, = V, I = 3 µa and 2 C A WIDEBAND NOISE (%) V POS =.6V V POS = 7.8V V POS = 3.V NSD (A rms/ Hz) pa pa pa fa fa 3.6mA 36µA 36nA 36nA 3.6nA 3.6µA 36µA µ µ µ m I (A) m 69-6 fa Hz khz khz khz MHz FREQUENCY MHz 69-7 Figure. Output Wideband Current Noise as a Percentage of vs. I for Multiple Values of VPOS, CSET = 2.2 nf, BW = MHz Figure 8. Output Current Noise Density vs. Frequency for Multiple Values of I, VPOS =.6 V, = V, CSET = 2.2 nf Rev. A Page 6 of 7

7 SIGMA +3 SIGMA V DRIFT (mv) AVERAGE V DRIFT (mv) AVERAGE 3 SIGMA 3 SIGMA TEMPERATURE ( C) Figure 9. Temperature Drift of V with = V, 3-σ to Either Side of Mean TEMPERATURE ( C) Figure 2. Temperature Drift of V with = V (External Voltage Source), 3-σ to Either Side of Mean m NORMALIZED RESPONSE (db) 2 2 3nA 3nA 3nA 3 A 3 A 3mA 3 A 3 3 k k k M M M M FREQUENCY (Hz) Figure. Small-Signal AC Response of I to for I in Decades from 3 na to 3 ma 69-8 I OUT (A) m 3 A TO 3mA: T-RISE = <s, T-FALL = <3ns 3 A TO 3 A: T-RISE = <s, T-FALL = <3ns 3 A TO 3 A: T-RISE = <s, T-FALL = < s 3nA TO 3nA: T-RISE = <2ns, T-FALL = < s 3nA TO 3nA: T-RISE = < s, T-FALL = <2 s 3nA TO 3nA: T-RISE = < s, T-FALL = <2 s TIME ( s) Figure 3. Pulse Response of I to for in Decades from 3 na to 3 ma 69-7 V (V). T-RISE FOR ALL S 2ns. 3. A 3. T-FALL 9.ms A. T-FALL 8 s ma. T-FALL 6ns TIME (ms) 69-8 ERROR FROM CALCULATED LIMIT (%) I LIM = 8/(R LIM + 3k ) V POS = V, V SET = V V POS = 2.7V, V SET = V V POS = 8V, V SET = V R LIM (k ) 69-2 Figure. Pulse Response of to V ( Pulsed from V to V) for Multiple Values of I Figure. Current Limit Error in Percent vs. RLIM for Multiple Voltages Rev. A Page 7 of 7

8 Data Sheet. 3 3 N = 227 MEAN =.696 SD = V POS V (V) (%) V POS (V) V V POS (V) Figure. VPOS V vs. VPOS for Multiple Temperatures Figure 7. Distribution of V VPOS for VPOS = V and I = 3 µa 2 2 N = 2 MEAN =.2 SD = N = 23 MEAN =.227 SD =.379 (%) (%) I OUT /I (A/A) V SET V (V) 69-3 Figure 6. Distribution of /I for VPOS = V, = V, and I = 3 µa Figure 8. Distribution of V for VPOS = V, = V, and I = 3 μa Rev. A Page 8 of 7

9 THEORY OF OPERATION The addresses the need for precision high-side monitoring of photodiode current in fiber optic systems and is useful in many nonoptical applications as well. It is optimized for use with ADI s family of translinear logarithmic amplifiers, which take advantage of the wide input current range of the. This arrangement allows the anode of the photodiode to connect directly to a transimpedance amplifier for the extraction of the data stream without the need for a separate optical power monitoring tap. Figure 9 shows the basic connections for the. 2.2nF 3 kω 39pF RLIM 2 NC 7 VPOS 6 8 R LIM.µF MIRROR OUTPUT Figure 9. Basic Connections.µF VOLTAGE SUPPLY At the heart of the is a precision : current mirror with a voltage following characteristic that provides an adjustable bias voltage at the mirror input. This architecture uses a JFET input amplifier to drive the bipolar mirror and maintain stable V voltage, while offering very low leakage current at the pin. The current sourced by the low impedance pin is mirrored and sourced by the high impedance pin. BIAS CONTROL INTERFACE The voltage at the pin, V, is forced to be equal to the voltage applied to by the mirror-biasing loop. The voltage range extends down to ground, allowing the to be used as a voltage-to-current converter with a single resistor from to ground. This capability allows dark current to be minimized in PIN photodiode systems by maintaining a small voltage bias. The control also allows V to be set approximately equal to the load voltage at. Balancing the mirror voltages in this way provides inherently superior linearity over the widest current range independent of the supply voltage. Only leakage currents from the JFET op amp and ESD devices remain as significant sources of nonlinearity at very low currents. The voltage at can also be used to shield the highly sensitive pin and its board trace from leakage currents, because the two pins operate at approximately the same potential. Care must be taken to provide a low noise signal, since voltage noise at also appears at and is transformed by the input compensation network into current noise The provides a setpoint reference pin,, which can be connected to for standard 2-port mirror operation. V is maintained. V below VPOS over temperature and is independent of input current. When using to set the input voltage, a capacitor should be placed between and ground to filter noise from as well as improve power supply rejection over frequency. A value of 2.2 nf, for example, combined with the 2 kω output resistance at, creates a pole at approximately 3 khz. The voltage at the pin can be lowered to a desired fixed value with the use of a single external resistor from to ground. Mismatch between on-chip and external resistors limits the accuracy of the resultant voltage. In addition, internal clamping to protect the precision bias limits the range. Figure 2 shows an equivalent circuit model of the biasing. The Schottky diode clamp protects the µa current source when is pulled to ground. When V is.2 V or higher, the µa current flows to the pin. The current is shunted away and does not appear at the pin for V <.6 V. The transition region is between.6 V and.2 V with a large uncertainty in the pull-down current. It is recommended that a 2-resistor divider from VPOS (with no connection to ) or another external bias be used to bias VREF in this transition region. Equations for the voltage with an external pull-down REXT follow: V V REXT + 2kΩ ( V. V), V.2 V = POS REXT = REXT VPOS, V R + 2 kω EXT.6 V where the 2 kω is the process-dependent internal resistor. 2kΩ.9V V POS µa C SET R EXT Figure 2. Model of Bias Source with External Pull-Down Rev. A Page 9 of 7

10 Data Sheet The control is intended primarily to provide a dc bias voltage for the mirror input, but it is also well behaved in the presence of the transients. The rise time of V is largely independent of input current because the mirror is capable of sourcing large currents to pull up the pin. The fall time, however, is inversely proportional to I because only I is available to discharge the input compensation capacitor and other parasitics (see Figure ). The mirror output current can vary significantly from zero to several milliamps until V is fully settled. NOISE PERFORMANCE The noise performance for the, defined as the rms noise current as a fraction of the output dc current, generally improves with increasing signal current. This partially results from the relationship between the quiescent collector current and the shot noise in the bipolar transistors. At lower signal current levels, the noise contribution from the JFET amplifier and other voltage noise sources appearing at contribute significantly to the current noise. Filtering noise at, whether provided by or generated externally, as well as selecting optimal external compensation components on, minimizes the amount of current noise at generated by the voltage noise at. MIRROR RESPONSE TIME The response time of to changes in I is fundamentally a function of input current, with small-signal bandwidth increasing roughly in proportion to I (see Figure ). The value of the external compensating capacitor on strongly affects the response time (as well as the to V fall time, as noted in the Bias Control Interface section), although the value must be chosen to maintain stability and prevent noise peaking. INPUT LIMITING The provides a resistor-programmable input current limit with a fixed maximum of 6 ma for the RLIM pin tied to VPOS. The fixed maximum provides input short-circuit protection to ground. The current limit is defined as the current that forces V to V (when using a current source on the pin). Resistor RLIM between the VPOS and RLIM pins controls the current limit according to I LIM = R 8 V + 3kΩ LIM over an RLIM range of to kω, corresponding to 6 ma down to ma. Larger values of RLIM can be used for currents below ma (down to approximately 2 µa) with some degradation in accuracy. See Figure for more performance detail. Rev. A Page of 7

11 APPLICATIONS The is primarily designed for wide dynamic range applications, simplifying power monitoring designs where access is only permitted to the cathode of a PIN photodiode or receiver module. Figure 22 shows a typical application where the is used to provide an accurate bias to a PIN diode while simultaneously mirroring the diode current to be measured by a translinear logarithmic amplifier. In this application, the sets the bias voltage on the PIN diode. This voltage is delivered at the pin and is controlled by the voltage at the pin. is driven by the on-board reference V, which is equal to VPOS V. The input current, I, is precisely mirrored at a ratio of : to the pin. This interface is optimized for use with any of ADI s translinear logarithmic amplifiers (for example, the AD83 or AD83) to offer a precise, wide dynamic range measurement of the optical power incident upon the PIN. If a linear voltage output is preferred at, a single external resistor to ground is all that is necessary to perform the conversion. AVERAGE POWER MONITORING In applications where a modulated signal is incident upon the photodiode, the average power of the signal can be measured. Figure 2 shows the connections necessary for using the in such a measurement system. The value of the capacitor to ground should be selected to eliminate errors due to modulation of the input current. C SET VOLTAGE REFERENCE 2kΩ 3 LIMITING NC 2 7 MIRROR : RLIM 6 VPOS 8 V POS LINEAR VOLTAGE OUTPUT PIN TIA DATA PATH 69- Figure 2. Average Power Monitoring Using the NODE VOLTAGES V = V POS V V SET = V VOLTAGE REFERENCE 2kΩ 3 LIMITING NC 2 7 MIRROR : R LIM RLIM I LIM = ma 6mA 6 VPOS 8 V POS R LIM = 8V 3kΩ I LIM VSUM THIS CONNECTION IS NOT NECESSARY, BUT REDUCES ERRORS DUE TO LEAKAGE S AT LOW SIGNAL LEVELS. OPTICAL POWER PIN TIA DATA PATH Figure 22. Typical Application Using the TRANSLINEAR LOG AMP AD83, AD83, ETC Rev. A Page of 7

12 VSUM VNEG VNEG VPOS TRANSLINEAR LOG AMP INTERFACING The mirror current output,, of the is designed to interface directly to an Analog Devices translinear logarithmic amplifier, such as the AD83, AD83, or ADL36. Figure 2 shows the basic connections necessary for interfacing the to the AD83. In this configuration, the designer can use the full current mirror range of the for high accuracy power monitoring. The measured rms noise voltage at the output of the AD83 vs. the input current is shown in Figure 23, both for the AD83 by itself and in cascade with the. The relatively low noise produced by the, combined with the additional noise filtering inherent in the frequency response characteristics of the AD83, results in minimal degradation to the noise performance of the AD83. Data Sheet Careful consideration should be made to the layout of the circuit board in this configuration. Leakage current paths in the board itself could lead to measurement errors at the output of the translinear log amp, particularly when measuring the low end of the s dynamic range. It is recommended that when designing such an interface that a guard potential be used to minimize this leakage. This can be done by connecting the translinear log amp s VSUM pin to the NC pin of the, with the VSUM guard trace running on both sides of the trace. Additional details on using VSUM can be found in the AD83 or AD83 data sheets. The pin of the can be used in a similar fashion to guard the trace. NOISE (V rms).m.m.m.m 3.m 3.m 2.m 2.m AD83 AND.m.m.m AD83 ONLY µ µ µ I (A) m 69-2 Figure 23. Measured RMS Noise of AD83 vs. AD83 Cascaded with C SET PIN VOLTAGE REFERENCE 2kΩ 3 LIMITING NC 2 7 TIA DATA PATH MIRROR : R LIM RLIM I LIM = ma 6mA 6 VPOS 8 V POS R LIM = 8V 3kΩ I LIM kω F AD83 INPUT COMPENSATION NETWORK 2kΩ.7nF 2kΩ VRDZ VOUT VREF AD83 SCAL IREF BFIN VLOG µF 3V TO 2V 2 9 OUTPUT V OUT =.2 LOG (M /A) 69- Figure 2. Interfacing the to the AD83 for High Accuracy PIN Power Monitoring Rev. A Page 2 of 7

13 EXTENDED OPERATING RANGE The is specified over an input current range of 3 na to 3 ma, but the device remains fully functional over the full eight decade range specified for ADI s flagship translinear logarithmic amplifier, the AD83 ( pa to ma). Figure 2 and Figure 26 show the performance of the for this extended operating range vs. various temperature and supply conditions. This extended dynamic range capability allows the to be used in optical power measurement systems, precision test equipment, or any other system that requires accurate, high dynamic range current monitoring. LINEARITY (%) LINEARITY (%) p C C +2 C +7 C +8 C +2 C, +7 C, +8 C, C, C µ µ µ m I (A) m m µ µ µ p m Figure 2. Extended Operating Range of pa to ma for Multiple Temperatures, Normalized to 2 C and I = 3 µa I VS. I OUT, ALL VOLTAGE CONDITIONS m. V POS = 2.7V, V SET = V V POS = V, V SET = 2V. V POS = V, V SET = V V POS = 8V, V SET = 2V V POS = 8V, V SET = V 2. p p µ µ µ m m I (A) m µ µ µ Figure 26. Extended Operating Range of pa to ma for Multiple Supply Conditions, Normalized to VPOS = V, = V and I = 3 µa I OUT (A) I OUT (A) USING RLIM AS A SECONDARY MONITOR The RLIM pin can be used as a secondary linear output for monitoring input currents near the upper end of the current range. The RLIM pin sinks a current approximately equal to I/. The voltage generated by this current through the series combination of an internal 3 kω resistor and the external RLIM is compared to a.2 V threshold and fed back to the mirror bias to limit I. Figure 27 shows the equivalent circuit and one method for using RLIM to form a bias proportional to I, also referred to as automatic photodiode biasing. This configuration is useful in PIN photodiode systems to compensate for photodiode equivalent series resistance (ESR) while maintaining low reverse bias at low signal levels to minimize dark current. Choosing R2 >> RLIM minimizes impact on ILIM and allows the resistor ratio, R2/R, to be calculated based on maximum photodiode ESR using the following simplified equation. R2 R RPDmax =, R2 >> RLIM, R LIM R = R3 where RPDmax is the maximum ESR of the photodiode. For zero bias at zero input current, the sum of RLIM and R3 must equal R. For positive bias at zero input current, the sum of RLIM and R3 should be greater than R. The ratio of VPOS to varies directly. For example, choosing RLIM =.82 kω ( ma ILIM), R2 = kω, and R = 8.2 kω compensates for photodiode ESR up to 2 Ω. A simple low voltage drop current mirror with a load resistor can replace the differential amplifier shown in Figure 27, although the resulting input current limit is less accurate and will vary with temperature. R R2 V POS R3 R2 RLIM VPOS RLIM 3kΩ I / MIRROR BIAS.2V Figure 27. Providing Automatic Photodiode Voltage Biasing Using RLIM Pin 96-3 Rev. A Page 3 of 7

14 Data Sheet V SET VOLTAGE (V) p µ µ µ m I (A) Figure 28. Voltage vs. I when RLIM Is Configured for Automatic Photodiode Biasing m CHARACTERIZATION METHODS During characterization, the was treated as a precision : current mirror. To make accurate measurements throughout the six-decade current range, calibrated Keithley 236 current sources were used to create and measure the test currents. Measurements at low currents are very susceptible to leakage to the ground plane. To minimize leakage on the characterization board, the pin is connected to traces that buffer V from ground. These traces are connected to the triax guard connector to provide buffering along the cabling. The primary characterization setup shown in Figure 3 is used to perform all static measurements, including mirror linearity between I and, V variation vs. I, supply current, and I current limiting. Component selection of the characterization board is similar to that of the evaluation board, except that triax connectors are used instead of SMA. To measure pulse response, noise, and small signal bandwidth, more specialized test setups are used. V SET VOLTAGE (V) I (ma) Figure 29. Voltage vs. I when RLIM Is Configured for Automatic Photodiode Biasing Figure 28 and Figure 29 show the performance of the circuit in Figure 27. The reverse bias across the photodiode is held at a low value for small input currents to minimize dark current. The voltage increases in a linear manner at the higher input currents to maintain accurate photodiode responsivity. The minimum bias level for the configuration above is ~2 mv CHARACTERIZATION BOARD VPOS DC SUPPLIES/DMM KEITHLEY 236 KEITHLEY 236 Figure 3. Primary Characterization Setup The setup in Figure 3 is used to measure the output current noise of the. Batteries are used in numerous places to minimize introduced noise and remove the uncertainty resulting from the use of multiple dc supplies. In application, properly bypassed dc supplies provide similar results. The load resistor is chosen for each current to maximize signal-to-noise ratio while maintaining measurement system bandwidth (when combined with the low capacitance JFET buffer). The custom LNA is used to overcome noise floor limitations in the HP89A signal analyzer Rev. A Page of 7

15 .V + +.V.V + 2.2nF HP89A VECTOR SIGNAL ANALYZER VPOS + 9V +2V R INPUT FET BUFFER R LOAD 9V + 2V LNA Figure 3. Configuration for Noise Spectral Density and Wideband Current Noise Figure 32 shows the configuration used to measure the pulse response of I to. To create the test current pulse, Q is used in a common base configuration with the Agilent 332A pulse generator. The output of the 332A is a negative biased square wave with an amplitude that results in a one decade current step at. RC is chosen according to what current range is desired. For 3 µa and lower, the AD867 FET input op amp is used in a transimpedance amplifier configuration to allow for viewing on the TDS oscilloscope. For signals greater than 3 µa, the ADA899- replaced the AD867 to avoid limiting the bandwidth of the. The configuration in Figure 33 is used to measure V while is pulsed. Q and RC are used to generate the operating current on the pin. An Agilent 332A pulse generator is used on the pin to create a. V to. V square wave. The setup in Figure 3 was used to measure the small signal ac response from I to. The AD838 differential amplifier was used to couple the ac and dc signals together. The ac signal was modulated to a depth of % of full scale over frequency. The voltage across RF sets the dc operating point of I. The values of RF are chosen to result in decade changes in I. The ADA899- op amp is used as a transimpedance amplifier for all current conditions. Q R C AGILENT 332A PULSE GENERATOR TDS OSCILLOSCOPE EVALUATION BOARD VPOS DC SUPPLIES/DMM Figure 32. Configuration for Pulse Response of I to Q R C EVALUATION BOARD VPOS DC SUPPLIES/DMM R C TDS OSCILLOSCOPE AGILENT 332A PULSE GENERATOR KEITHLEY 236 Figure 33. Configuration for Pulse Response from to V NETWORK ANALYZER OUTPUT R A B POWER SPLITTER + AD838 + EVAL BOARD R F Ω EVALUATION BOARD VPOS DC SUPPLIES/DMM Figure 3. Configuration for Small-Signal AC Response R F Rev. A Page of 7

16 Data Sheet EVALUATION BOARD GND V SET C OPEN L C3 39pF R k 2 NC 8 7 R OPEN I OUT SW R3 3 VPOS 6 V POS R R2 C C2 k. F. F RLIM S REF Figure 3. Evaluation Board Schematic (Rev. A) 69-3 Table. Evaluation Board (Rev. A) Configuration Options Component Function Default Conditions VPOS, GND Supply and ground connections. Not applicable INPUT, L, C Input Interface: The evaluation board is configured to accept an input current at the SMA connector labeled INPUT. Filtering of this current can be done using L and C. L = Ω (size 8) C = open (size 63) R, C3 Input Compensation. Provides essential HF compensation at the pin. C3 = 39 pf (size 8) R =.2 kω (size 2),, SW, R, R6, R7, R R2 Bias Voltage. The dc voltage applied to determines the voltage at, = V. Connecting to sets the bias at to be V below VPOS. Opening SW allows for to be driven externally via the SMA connector. Output/Mirror Current Interface: The output current at the SMA connector labeled is equal to the value at. R allows a resistor to be installed for applications where a scaled voltage referenced to IPD is desirable instead of a current. Current Limiting. An external resistor to VPOS sets the current limit at from ma to 6 ma. ILIM = 8 V/(RLIM + 3 kω). The evaluation board is configured such that ILIM = 3.7 ma. SW = closed R = Ω (size 2) R6 = R7 = Ω (size 2) R = open (size 63) R2 = kω (size 2) C, C2, R3 Supply Filtering/Decoupling. C =. μf (size 2) C2 =. μf (size 63) R3 = Ω (size 8) Figure 36. Component Side Layout 69- Figure 37. Component Side Silkscreen 69- Rev. A Page 6 of 7

17 OUTLINE DIMENSIONS DETAIL A (JEDEC 9).2 MIN PIN INDEX AREA TOP VIEW BSC 8 EXPOSED PAD BOTTOM VIEW PIN INDIC ATOR AREA OPTIONS (SEE DETAIL A) PKG-67 SEATING PLANE MAX.2 NOM.23 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET A Figure Lead Lead Frame Chip Scale Package [LFCSP] 3 mm 2 mm Body and.7 mm Package Height (CP-8-23) Dimensions shown in millimeters ORDERING GUIDE Model, 2 Temperature Range Package Description Package Option Branding ACPZ-R7 C to +8 C 8-Lead LFCSP CP-8-23 Q ACPZ-WP C to +8 C 8-Lead LFCSP CP-8-23 Q -EVAL Evaluation Board Z = Pb-free part. 2 WP = Waffle pack 2 27 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D69--9/7(A) Rev. A Page 7 of 7