CMOS Current Starved Voltage Controlled Oscillator Circuit for a Fast Locking PLL

Transcription

1 IEEE INDICON CMOS Current Starved Voltage Controlled Oscillator Circuit for a Fast Locking PLL Abstract Two novel voltage controlled oscillators (CSN- and CSD-) have been proposed in this paper. CSN- has been designed with 20 transistors while with 24 transistors. It has been observed that CSN- could operate in the frequency range from to 2.2 GHz, and could operate from to 2.5 GHz. Tuning range for these s are determined to be 97 %, and 98.2 % while the values of gain obtained are 8.94 and 10.2 GradV -1 respectively. Phase noise analysis has been performed and the phase noise contribution by CSN- and are found to be -126 and MHz respectively. Prototype has been designed in Cadence virtuoso environment and implemented using GPDK090 library of 180 nm technology with a supply voltage of 1.8 V. Simulation of transfer function of PLL built with the s has been done in MATLAB and the step response has been compared with the circuit simulation results from Cadence. Lock time as low as 355 ns and 313 ns have been achieved for the CSN- and CSD- respectively. Keywords phase locked loop, voltage controlled oscillator, delay cell, phase noise. I. INTRODUCTION Radio frequency integrated circuits (RFICs) are widely used in all types of wireless communications. Phase locked loop represents a class of commonly used RFIC wherein Voltage controlled oscillator () is one of the important building blocks. Designing a PLL with less locking time while maintaining optimum values for power dissipation, phase noise and chip area is a challenging task. And lot of research is being carried out in this field to improve the topologies by which the s are built in order to optimize various parameters like higher operating frequencies, low phase noise, increased tuning range, low power dissipation and less area etc. The various sources of phase noise in a PLL could be categorized as either in-band or out-of-band. The loop filter and are subjected to high-pass filtering by loop action and are therefore significant sources of out-of-band phase noise 5]. has been reported to be a significant factor in optimizing the phase noise of the PLL system as it has been found to be the dominant source of out-of-band phase noise 1-4]. Many different types of voltage controlled oscillators are used in PLL. It has been reported in literature that LC s result in better phase noise and higher frequency at the expense of larger integration area. Hence CMOS ring oscillators have /15/$ IEEE. Abdul Majeed K.K, Binsu J Kailath Electronics Department IIITDM Kancheepuram, Chennai, India edm12d001@ iiitdm.ac.in, bkailath@iiitdm.ac.in been extensively used in s as it results in smaller integration area and wider tuning range when compared with the LC s. Implementation of a two stage CMOS ring oscillator using a delay cell with good phase noise performance has been presented by W.S.T Yan, et al 1]. Better tuning range and quadrature output have been obtained by modifying the delay cell and the same has been used to implement a four stage 2]. Two stage CMOS voltage controlled ring oscillator using scaled differential delay has been reported to result in wideband while a three stage differential delay is found to result in better phase noise as well 3]. Another LC with better phase noise but with lower tuning range and higher the power dissipation is also reported 4]. It could be observed that designed using CMOS delay cell ring oscillator may be a better option to be used as a in PLL as the phase noise could be reduced by increasing the number of delay cells. In view of this, two s based on current starved CMOS NAND cells and current staved CMOS delay cells are presented in this paper. The proposed s are integrated into a PLL and the design parameters have been optimized for a better PLL design. Proposed circuits and the delay cells are presented in section II and the simulation results are presented in section III. Performance analysis of PLL circuit and discussion based on derived transfer function are presented in section IV. II. PROPOSED DESIGN The ring oscillators designed with a series of delay cell stages have created great interest among researchers due to their numerous useful features. These attractive features are (i) the ease with which the circuits could be designed with CMOS and BiCMOS technology, (ii) lower control voltage required for oscillation, (iii) low power dissipation while providing higher frequency of oscillations, (iv) electrical tuning and wide range and (v) possibility to obtain multiphase outputs due to their basic structure 6]. A. Current starved NAND based (CSN-) Schematic diagram of the proposed CSN- is shown in Fig. 1 which uses three delay cells so as to reduce the phase noise contribution from the. NAND gates present in the center row act as inverter while upper PMOS and lower NMOS operate as current sources which limit the current available to the NAND gate forcing it to starve for current. The current in the first NMOS and PMOS (P1-N1) are 1

2 Fig.1. Schematic diagram of Current starved NAND based (CSN- ) mirrored in successive stages. The frequency of oscillation could be effectively controlled as the propagation delay is proportional to the charging and discharging currents. All the NMOS and PMOS transistors are designed with a width of 2 µm and length of 180 nm. B. Current starved Delay-cell based (CSD-) The proposed current starved delay-cell based (CSD- ) is shown in Fig. 3. which is implemented using the modified delay cell given in Fig. 2. This delay cell is composed of a differential pair of NMOS transistors (N1 and N2) with cross-coupled PMOS transistors (P3 and P4) as load, along with two PMOS current sources (P2 and P5) which perform the function of increasing or decreasing the output load current depending on the variation in the control voltage. The operation of implemented with three stages of this modified delay cell is similar to that of. Each NAND gate present in the centre row in the is replaced with modified delay cell, while upper PMOS and lower NMOS are operated as current sources. The current sources limit the current available to the delay cell starving it for current. The current in the first NMOS and PMOS are Fig.3. Schematic diagram of Current starved delay-cell based (CSD- ) mirrored in the successive delay cell stages. Comparatively better control of output frequency is achieved in this circuit as the propagation delay could be effectively controlled using charging and discharging currents. III. SIMULATION RESULTS OF The proposed current starved voltage controlled oscillators are simulated using GPDK 180 nm CMOS technology in CADENCE environment and performance parameters such as tuning range, phase noise, power dissipation and gain of the s are analyzed using Virtuoso ADE. A discussion on these results is provided in the following section with the summary of analysis presented in Table I. A. Transient Analysis Transient analyses of the proposed circuits have been performed in Cadence Virtuoso ADE with a supply voltage Vcnt=0.5 Vcnt=0.64 Vcnt=0.77 Vcnt=1.15 Vcnt=1.54 Vcnt=1.8 Fig.2. Schematic diagram delay cell used in Current starved delay-cell based (CSD-) Fig.4. Transient response of proposed CSN- with different control voltage 2

3 Oscillating Frequency (Hz) Phase Noise (dbc/hz) Vcnt=0.5 Vcnt= Vcnt= Vcnt= Vcnt=1.54 Vcnt=1.8 Fig.5. Transient response of proposed CSD- with different control voltage (V dd ) of 1.8 V. Corresponding transient responses of CSN- and CSD- with X-axis time scale varying from 485 ns to 500 ns are presented in Fig. 4 and Fig. 5 respectively. output signals for six different control voltages (Vcnt) viz. 0.5 V, 0.64 V, 0.77 V, 1.15 V, 1.54 V and 1.8 V are presented from top to bottom in both the figures. Increase in frequency of oscillation with increase in control voltage can be observed from both the plots. Also, output frequency of CSD- is found to be larger than that in CSN- for the same control voltage and the transfer characteristics is explained in the following section k 1M 100M Frequency (Hz) Fig.7. Phase noise analysis of proposed CSN- and CSD- B. Tuning Range. Oscillating frequency versus control voltage characteristics of the proposed s are presented in Fig. 6. The output frequency of the CSN- is found to vary from 66 MHz to 2.2 GHz as the control voltage is varied from 0 V to 2 V resulting in a tuning range of 97% and gain of 8.94 GradV -1. Whereas, the output frequency of CSD- is found to vary from 47 MHz to 2.5 GHz for the same range of control voltage resulting in a better tuning range of % and gain of 10.2 GradV -1. C. Phase Noise Analysis. Phase noise characteristics have been obtained by performing periodic steady state analysis and phase noise analysis 5] for the two s and the same are presented in Fig. 7. It can be inferred from measured values given in Table I that the CSD- is much more appropriate candidate for low jitter applications. 3G 2G 1G IV. PLL ANALYSIS Basic block diagram of the conventional PLL is presented in Fig. 8 and the transfer function for such a PLL implemented with the proposed s has been determined to compare the simulation results obtained from circuit simulation with that from simulation in MATLAB. where And hence, (1) Control Voltage (V) Fig.6. Transfer characteristics (Oscillating frequency versus control voltage characteristics) of CSN- and CSD- F(s) is the transfer function of loop filter and using F(s) in equation (1) would give: This could be expressed in terms of natural frequency and damping factor as (2) (3) 3

4 Voltage (V) Voltage (V) The constant values are obtained as A=N, B=-N and C=0. (7) Fig.8. Block diagram of PLL Where and ( ). (4) ] (8) The inverse Laplace transform of the equation (8) is obtained as * + (9) where. Equation (9) could be expressed as where as and hence ] (10) A. Lock time (settling time:t s ) of the PLL. Lock time of the PLL have been determined by computing the inverse Laplace transform of step response as well as by simulation in MATLAB and circuit simulation in Cadence and the results are compared. Coefficient of third order term in the denominator of transfer function is found to be of the order of 10-8 to for (C 1 =9 Pf, C 2 =1.125 pf, R 1 =5 KΩ, I cp =100 µa and ) and hence the transfer function given in equation (4) could be expressed as: C(s) is the output of the for a step input u(t)=1 and U(s)= By partial fraction equation (6) could be expressed as 1.06 (5) (6) ] (11) Settling time or lock time is defined as the time taken by the response to reach and stay within a specified error of 1 to 2 % of the final value. The exponentially decaying term in the time response of the PLL determines the settling time of PLL. As divide by N counter was set to divide the frequency by 16, the settling time needed to reach within the 1% tolerance limit (15.84) of the steady state value of 16 V could be computed from equation (11) as: ] for 1 % tolerance which gives ] (12) The values so obtained are presented in Table I along with the n 500n Time (s) Fig.9. Step Response of the PLL TFs using proposed CSN- (14) and CSD- (15) in MATLAB 0 250n 500n Time (s) Fig.10. Circuit level simulation of PLL control voltage using proposed CSN- and CSD- in Cadence 4

5 TABLE I. PERFORMANCE COMPARISON TABLE parameters CSN- CSD- 3] 1] Output Frequency (GHz) to to 1.22 to 0.66 to Tuning Range (%) Gain (GradV -1 ) Phase Noise (dbc/hz@1mhz Power dissipation (mw) No. of stages Lock Time CSN- CSD- By calculation (ns) By TF analysis (MATLAB) (ns) By simulation (CADENCE) (ns) corresponding values obtained from circuit simulation in Cadence and TF analysis using MATLAB. B. Step Response In order to find the step response of the PLL implemented with designed s, the respective transfer functions in each case has been determined and MATLAB simulation studies have been performed and are discussed in the following sub sections. The transfer function would be B.1. Analysis of PLL with CSN- (13) The gain of the CSN- is computed from its transfer characteristics as * + = 8.94G H zv -1, ω n =29.6 Mrads -1 and =0.66 and the TF for this circuit is obtained as: B.2. Analysis of PLL with CSD- (14) The gain of the CSD- is computed as * + = 10.2G H zv -1, ω n =31.7 Mrads -1 and =0.714 and the TF for this circuit is obtained as: (15) Step responses of PLL built in MATLAB with above TF and for both CSN- (14) and CSD- (15) are plotted in Fig.9 and the lock time so computed are presented in Table I. D. Lock time analysis of PLL using the designed s. PLL circuits have been implemented using each of the proposed s using CADENCE, along with phase frequency detector and charge pump 7], loop filter 8] and divide by eight counters. The charge pump circuit carries a constant current (I cp ) of 100 µa. Lock time characteristics have been obtained by performing transient analysis of PLL implemented with each of the designed s and are presented in Fig.10. It can be inferred from measured values given in Table I that the is having lower locking time when compared with. V. DISCUSSION The performances parameters of CSN- and CSD- have been compared with different architectures reported in literature and are presented in Table I. The phase noise contributions of the proposed s are found to be -126 dbc/hz and MHz for CSN- and CSD- respectively. The tuning range and gain of the designed s are also found to be better. Higher gain of results in accelerating the lock-in process of the PLL. Lower phase noise contribution from CSD- when compared with that of CSN- could be attributed to its higher delay due to the delay cells. Reduction in phase noise and increase in gain is found to result in improved lock-time for the PLL with CSD- and this has been verified by analytical computation, TF analysis in MATLAB and by circuit simulation using CADENCE. Hence these s are proposed to be utilized for low jitter and fast locking PLL. VI. CONCLUSION Two novel current starved CMOS s are presented in this paper. Both the s are found to provide higher tuning range and larger gain which make these designs suitable for PLL in wide band and fast locking applications. The PLL circuit has been implemented in Cadence and the response has been verified using simulation in MATLAB. CSD- is found to be a better design suitable for low jitter PLL design due to its reduced phase noise and faster locking time when compared with CSN-. REFERENCES 1] Yan, W.S.T, and Luong, H.C., "A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator," in Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol.48, no.2, pp , Feb ] ElKader, S.A. and Dessouky, M., "A 10 GHz ring using a wide range delay cell architecture," in Microelectronics (ICM), International Conference on, vol., no., pp , Dec ] Panigrahi, J.K.; Acharya, D.P., "Performance analysis and design of wideband CMOS voltage controlled ring oscillator," in Industrial and Information Systems (ICIIS), International Conference on, vol., no., pp , July Aug ] Rout, P.K.; Nanda, U.K.; Acharya, D.P.; Panda, G., "Design of LC for optimal figure of merit performance using CMODE," in Recent Advances in Information Technology (RAIT),1st International Conference on, vol., no., pp , March ] Homayoun, A.; Razavi, B., "Analysis of Phase Noise in Phase/Frequency Detectors," in Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.60, no.3, pp , March ] Shrivastava, A.; Khandelwal, S.; Akashe, S., "Performance Evaluation of Five Stage Ring Oscillator with Reverse Substrate Bias and SAL Technique Using Nanoscale CMOS Technology," in Advanced Computing and Communication Technologies (ACCT), Third International Conference on, vol., no., pp , 6-7 April ] Ismail, N.M.H.; Othman, M., "CMOS phase frequency detector for high speed applications," in Design and Test Workshop (IDT), 4th International, vol., no., pp.1-5, Nov ] Hanjun Jiang; Chengming He; Degang Chen; Randall, G., "Optimal loop parameter design of charge pump PLLs for jitter transfer characteristic optimization," in Circuits and Systems MWSCAS. The 45th Midwest Symposium on, vol.1, no., pp.i vol.1, 4-7 Aug