EE 4345 Semiconductor Electronics Design Project

Transcription

1 EE 4345 Semiconductor Electronics Design Project Transistor Current Sources and Active Loads Anuj Shah Himanshu Doshi Jayaprakash Chintamaneni Nareen Katta Nikhil Patel Preeti Yadav

2 Current Sources Current sources made by using active devices have come to be widely used in analog integrated circuits as Biasing elements and as load devices for amplifier stages The use of current sources in biasing can result in superior insensitivity of circuit performance to power supply variations and to temperature

3 A simple -transistor current source

4 Simple current source Since Q1 and Q have the same base-emitter voltage. Their collector currents are equal, c1 = c Summing currents at the collector of Q1 gives, ref c 1 c1 f 0 ref c1 1 f c c ref cc R be ( on) Thus, For identical devices Q1 and Q, the output and the reference Currents are equal

5 Collector characteristics for an npn transistor

6 Norton equivalent representation Of a transistor current source Thevenin equivalent Representation of a Transistor current source

7 Simple current source with current gain

8 The collector current c is different form the reference Current by a factor [ 1 + ( /ß f )] The emitter current of the transistor Q3 is given by, c1 c f f c Summing currents at the collector of Q1, ref c c1 f ( f 1) Since c1 and c are equal, o ref c 1 f f f 0 Thus, the reference and the output current differ only by a factor of 1/ß f

9 Widlar current source

10 Widlar current source Assuming that the transistors are identical and that ce is high enough to allow Q to operate in the active region,the collector current of Q is given by, s exp be c T 1 T ln C 1 be S ln c be T S

11 oltage equation around the base-emitter loop gives, Solving for R gives R be1 be e R T ln c C C 1 Neglecting the base currents, c1 ref cc R 1 be1

12 Design a widlar current source, given cc=15volts. Assume identical transistors.also, design a 10uA current mirror and compare total resistance required in the two circuits. Let ref =1mA 15 v 0.6v 14.4k 1mA R c1 1mA T ln 0.05 ln 1 c 10 A Design of current mirror, k R cc be 15 v 0.5 v A ref M

13 Cascode current source with bipolar transistors Performing a full small-signal analysis on this circuit, including the finite small-signal resistance of Q1 and Q4 We obtain, Ro =ß 0 r 0 /

14 Bipolar Wilson current source

15 Conventional Differential Amplifier A dm g m R c c R T c Resistors are used as load elements Large oltage Gain requires large power-supply voltage and large values of resistors Example: A voltage gain of 500 would require and c 100 A, R c would have to be c Rc K

16 Current Sources as Active Load Common-Emitter Amplifier with Active Load Emitter-Coupled Pair with Active Load nput Offset oltage of the Emitter-Coupled Pair with Active Load Common-Mode Rejection Ratio of the Emitter-Coupled Pair with Active Load Common-Source Amplifier with Active Load

17 Fig.Common-emitter amplifier with active load c1 ce c1 c c cc ce1 [( 1), ] cc ce BE

18 Fig.npn collector characteristic with pnp Load line superimposed Transistors NPN PNP nitially at i =0 at point 1 Off Saturates As i ncreases at point On On at point 3 On On at point 4 Saturated Saturated

19 AP ce T be s c AN ce T i s c exp 1 exp AP on BE T BE s c ref ) ( exp cc ce ce Large Signal Model

20 Fig.dc transfer characteristics Of common-emitter Amplifier with active load 0 Where [ cc, A( eff ) BE( on) ( 0 AN ]( AN AN AP AN AP AP [ CC BE ( on)]( ) A( eff ) [1 s1 exp ) & [ CC CE ( sat )] 0 [ CE ( sat )] AN AN AP ) ref i T ]

21 Fig.Small-signal equivalent Circuit for common-emitter Amplifier with active load A v g ( r r ) m1 m1 o1 o 1 1 r o1 g r 0 g g npn m1 m1 pnp g m R 0 =(r onop +r opon ) Typical values for voltage gain are 1000 to 000 range.

22 Fig.Emitter-coupled pair with Active load Drawback: The quiescent value of the common-mode output voltage is very sensitive to the value of the emitter-biasing current source and the active-load current sources.

23 Fig.Common-mode half-circuit for emitter-coupled pair with active load

24 Output voltage oc is very sensitive to the voltage at the base of Q 6, which is influence by ref. Example: f ref1 and ref are different by 4%, the output voltage oc will change by about. The same change result from a 1m mismatch between Q 6 And Q 7.

25 This circuit eliminates the common-mode problems but provides a single output with much better rejection of common-mode nput signals.

26 Large signal behavior model Fig.Active-load stage with output connected to a voltage source Load resistance is zero. bias is adjusted in order to keep Q and Q 4 in forward Active region.

27 c s be ce (exp )(1 T AN ) c3 s be 3 ce 3 (exp )(1 ) T AP c4 s be4 ce4 (exp )(1 T AP ) ce1 cc be 3 be 1 cc ce 3 BE ( on ) id be1 be

28 T id AP AN AP AN T id eff A BE cc o on tanh 1 tanh ) ( ) ( AP AN AP AN A eff ) ( T id eff A BE cc o on tanh ) ( ) ( ) ( ) ( sat CE on BE o cc where

29 A vd A( eff ) T 1 T AN AN AP AP T AN 1 T AP 1 Avd g npn pnp m ( r onpn llr opnp ),Where EarlyFactor T A Early factor is on the order of * 10-4

30 Device Mismatch Effects: Presence of Component mismatches within the Amplifier itself and drifts of component values with Temperature produce differential voltages at the output that are indistinguishable from the signal being amplified. For Transistor Differential Amplifiers the effect of mismatches is represented by two Quantities,the input offset voltage and the input offset current.

31 Circuit Containing Mismatches Equivalent Circuit with identically matched devices

32 nput Offset oltage is given by the expression where OS T c1 c kt T 6m q s s1 at 300K s represents the Saturation Current sn N A qn W i Bn D n n CB A where W b ( CB ) is the base width of the function CB N A is the acceptor density in the base and A is the emitter Area

33 nput Offset oltage of the Emitter Coupled Pair with Active Load For a Resistive Load the nput Offset oltage arises mainly due to the mismatches in s in the nput Transistors and from mismatches in the collector load Resistors. For an Active Load the input offset voltage results from mismatches in the input Transistors and load devices and from the base current of the load devices.

34 Emitter Coupled Pair with Active Load

35 nput Offset oltage of the Emitter Coupled Pair with Active Load 1 ce ce 3 ce4 ce and The Collector Current c4 is related to c3 by s s c c The Collector Current Q is equal to (-c4) and thus s s c c The Current c1 equals (- c3 ),plus the base currents in the pnp transistors f c c 1 3 1

36 The input offset voltage is given by f s s s s T oc 1 ln n a Worst Case, the Offset oltage is 0. T These Circuits have significantly higher offset oltage than the Resistively loaded case The offset oltage can be reduced by inserting resistors in the Emitters of Q3 and Q4.

37 Actively Loaded Emitter Coupled Pair for improved Offset

38 Common-Mode Rejection Ratio of the Emitter Coupled Pair with Active Load CMRR is defined as the Magnitude of the ratio of differential to Common Mode Gain. Provides conversion from a differential signal to a signal that is referenced to ground.this type of Conversion is required in all differential input,single-ended output amplifiers. Simplest differential to single-ended converter is the resistively Loaded emitter coupled pair.

39 Differential to Single ended Conversion Using resistively loaded Emitter coupled Pair Differential to Single ended Conversion Using actively loaded Emitter coupled Pair

40 The output is given by o A dm id ic CMRR CMRR g R m 1 EE 1 1 Transistor Q 3 operates at twice the current of Q 1 and Q CMRR g m r 3 o3 1 3 CMRR of the resistively loaded stage is the inverse of the of the current source Transistor when a simple current source is used as a biasing element.

41 For an active-loaded case n case of Resistively loaded case,changes in the common Mode input will cause changes in the bias current EE because of the finite output resistance of the biasing current source.this will cause a change in c and an identical change in c1. Because of the active load,the change in c1 will produce a change in the currents flowing in the pnp load transistors,which produces a change in the collecter current of Q.So the output does not change at all in response to common Mode nputs. Analytically CMRR A A dm cm os ic 1

42 Common-Source Amplifier with Active Load Common Source Amplifier using an NMOS driver and PMOS active load. When M1 and M are forward active,the small signal gain is A v g o1 g m1 g o Gain for NMOS depletion-load transistor A v g g m1 mb

43 Common-Source Amplifier with p channel transistor Current source load Transfer Characteristic

44 - Characteristic of n-channel depletion mode load transistor

45 Common Source Amplifier with depletion mode transistor load and dc transfer characteristic

46 Common Source Amplifier with Enhancement-Mode load Common-Source Amplifier with enhancement-mode load and transfer characteristic A v g g m1 m W / L1 W / L

47 Source Coupled Pair with Active load A v g o g m1 g o4 Widely used in CMOS Circuit Design

48 References: Analysis and Design of Analog ntegrated Circuits, 3 rd Edition by Paul R.Gray and Robert G.Meyer. Analog integrated circuit design,1 st edition by David Johns and Ken Martin Electronics, nd Edition, by Allan R.Hambley