Comparative Evaluation of Multi-Loop Control Schemes for a High-Bandwidth AC Power Source with a Two-Stage LC Output Filter

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1 22 IEEE Proceedings of the International Conference on Renewable Energy Research and Applications (ICRERA 22), Nagasaki, Japan, November -4, 22 Comparative Evalation of Mlti-Loop Control Schemes for a High-Bandwidth AC Power Sorce with a Two-Stage LC Otpt Filter P. Cortés, D. O. Boillat, H. Ertl, J. W. Kolar This material is pblished in order to provide access to research reslts of the Power Electronic Systems Laboratory / D-ITET / ETH Zrich. Internal or personal se of this material is permitted. However, permission to reprint/repblish this material for advertising or promotional prposes or for creating new collective works for resale or redistribtion mst be obtained from the copyright holder. By choosing to view this docment, yo agree to all provisions of the copyright laws protecting it.

2 Comparative Evalation of Mlti-Loop Control Schemes for a High-Bandwidth AC Power Sorce with a Two-Stage LC Otpt Filter Patricio Cortes, David O. Boillat, Hans Ertl, Johann W. Kolar Power Electronic Systems Laboratory, ETH Zrich, Switzerland cortes@lem.ee.ethz.ch Vienna University of Technology, Astria Abstract This paper presents a comparative evalation of for different mlti-loop control schemes for a high-bandwidth AC power sorce. The power sorce considered in this work is based on a three-level T-type inverter with a two-stage LC otpt filter. The control schemes evalated in this paper have an otpt voltage controller in the oter loop. For the inner control loop the following options are evalated: capacitor crrent feedbacks, proportional-integral and proportional inverter otpt crrent control in combination with reference voltage and load crrent feedforward, and first LC stage capacitor voltage and inverter otpt crrent feedback. The reference tracking capabilities as well as the power sorce otpt impedance are evalated. Analytical and simlation reslts are shown to be in very good agreement, and the freqency and step responses for the different control schemes are compared. The reslts show that a cascaded strctre consisting of a proportional-integral controller for the otpt voltage and a proportional controller for the inverter otpt crrent allows to achieve the best dynamic behavior in terms of otpt voltage control bandwidth and otpt impedance. Keywords AC sorce, high-bandwidth, two-stage LC filter, mlti-loop control, capacitor crrent feedback. I. INTRODUCTION A high-bandwidth power sorce is the preferred option for testing new power electronic converters [] []. It allows to test different operating conditions like the presence of harmonics and step changes in the spply voltage. These kind of tests make possible to verify the compliance to specifications and standards, as described in [] [5]. A kw three-phase power sorce is considered in this work. For a better handling of single-phase loads, each phase of the converter is controlled independently. Conseqently, for the controller adjstment and the comparative reslts presented in this paper only one phase of the system is considered. The power sorce is composed of a three-level T-type converter and a two-stage LC filter with a passive damping circit of the second stage, as shown in Fig.. The filter strctre is briefly discssed in Section II. Several control schemes have been proposed for power sorces with a single-stage LC otpt filter. The se of a mlti-loop strctre is the most common choice for these kind of converters [6], [7]. However, there are many options in the selection of the feedback variables and in the type of the controller sed in each loop. The se of more advanced control schemes like model predictive control has also been evalated [8]. A dynamic control of the switching freqency has been proposed in [9] to improve the dynamic performance of the power converter. As explained in [], the addition of a second LC stage to the otpt filter affects the behavior of the otpt voltage control and the otpt impedance of the power sorce. A second filter stage is reqired in order to increase the attenation of the switching high freqency harmonics withot significantly redcing the filter dynamics. This imposes a higher complexity in the design of a high performance control scheme. Most of the pblished works deal with the control of converters with a single stage filter. Control schemes for converters with a two-stage filter have not been well analyzed in the literatre. For different mlti-loop control schemes for the AC power sorce are evalated in this paper. The effect of the second filter stage on the otpt voltage dynamics and attenation of high freqency harmonics is discssed in Section II. The control strctres, their design and achieved performance are explained in Section III. Then, comparative simlation reslts are presented in Section IV, considering the freqency and step responses for the different control schemes. The control bandwidth of the otpt voltage and the otpt impedance of the system are the main performance indexes considered for comparison. Finally, the selection of the control scheme p U DC,p U DC,n n C DC,p C DC,n C C 2 Fig. Three-level T-type converter with a two-stage otpt LC filter. i C R D L D i i ot

3 that achieves the best performance indexes and ftre research topics are discssed in Section V. II. TWO-STAGES LC OUTPUT FILTER The design of the otpt filter for a high-bandwidth AC power sorce has been stdied in []. For a single-stage LC filter design there is a trade-off between the reqirements in dynamics of the otpt voltage and the attenation of high freqency harmonics in the otpt voltage. If the filter is designed for fast dynamics, as reqired for a high-bandwidth control of the otpt voltage, the reqired attenation of high switching freqency harmonics might not be achieved. In this paper, the standard for condcted emission levels according to IEC/EN 55 Class A is considered. The inclsion of a second LC stage allows to increase the attenation of high freqency harmonics withot redcing the filter dynamics significantly. Usally a two-stage LC filter for switched mode AC power sorces shows different indctance vales for the two stages, ths L is normally one order of magnitde higher in indctance vale than L 2 (cf. Fig. and Table I). The reasons are: firstly, the indctance L of the first filter stage is selected to be reasonably high in order to limit the inverter otpt peak-to-peak crrent ripple. Secondly, the indctance L 2 of the second filter stage is designed to achieve a reasonably low vale as a compromise between an increased additional attenation of high freqency harmonics and a redced phaseshift between the first stage capacitor voltage C and the second stage capacitor voltage. Frthermore, considering the otpt voltage dynamics and the otpt impedance of the converter with the two-stage LC filter, the first filter stage capacitor and second filter stage capacitance C 2 are in the same order of magnitde (cf. Fig. ). Conseqently, the characteristic impedance L Z = () C of the first filter stage L is higher than the one of the second filter stage L 2 C 2. It is remarked, that if a singlelc filter stage is distribted to n LC filter stages of eqal component ratings (L/n, C/n) [2], finally a lossless transmission line eqivalent circit model is obtained for n. Sch a circitry wold, however, no longer show a low-pass filter characteristic, which is reqired regarding condcted EMI noise sppression. Frthermore, the characteristic impedance of sch a transmission line wold be symmetrical which may be too low considering the inverter otpt peak-to-peak crrent ripple bt too high regarding the filter otpt impedance seen by the load. As a conseqence, mlti-stage LC filters are sally dimensioned sch that the characteristic impedances Z,i of the individal stages i are lowered from the filter inpt side towards the otpt side. In Fig. 2 the transfer fnctions of the ndamped and the damped two-stage LC filter considered in this paper (cf. Fig. ) are plotted for the filter parameters given in Table I. Magnitde (db) Phase (deg) Bandwith range of the voltage control loop Filter with passive damping Filter withot damping f f Freqency (Hz) Fig. 2 Bode plot of the two-stages LC filter with and withot the damping circit shown in Fig. and filter parameters of Table I. The bandwidth of the crrent control loop is indicated with a dashed line at f CL. A straight forward approach to control a two-stage LC filter, derived from the classical control strctre for a single-stage LC filter [6], is to employ a cascaded control strctre with an inner inverter otpt crrent and an oter otpt voltage control loop (cf. Section III.B and Section III.C). In order to actively damp the resonance of the first filter stage at f, the inverter otpt crrent control loop bandwidth mst be higher than f. Analogos, the resonance of the second filter stage at f 2 can only be actively damped if the otpt voltage control loop bandwidth is higher than f 2. The closedloop bandwidth (-db) of the otpt voltage and the inverter otpt crrent control loops designed in this paper are indicated in Fig. 2. Conclding, as can be seen from Fig. 2, the first filter stage resonance can be damped by means of the crrent control loop. Frthermore, the otpt voltage control loop bandwidth is clearly not high enogh to damp the resonance of the second filter stage, mainly becase of the high Z (indctorl ) of the first filter stage. Ths, the second filter stage is passively damped by a parallel RL damping branch, which constittes a low cost option to achieve the damping. As can be observed in Fig. 2, the resonance of the second stage is properly damped. III. MULTI-LOOP CONTROL SCHEMES The following control schemes with different nmbers of control loops are evalated and compared in this paper: A. PI( )FB(i C ): proportional-integral (PI) controller for the oter voltage control loop and feedback (FB) of the capacitor crrent i C providing active damping of the filter resonance [cf. Fig. (a)]. The capacitor crrent feedback emlates the behavior of a damping resistor in the first stage of the filter. B. PI( )PI( ): PI controller for the oter voltage control loop and PI controller for the inverter otpt crrent in the inner loop. Feedforward loops for the load f CL

4 R D L D R D L D i ot C C 2 i C i C C C 2 k k 2 PI Control A: PI( ) FB( i C ) PI Control B: PI( ) PI( ) PI (a) Cascaded control scheme with one PI controller for the otpt voltage and feedback of first stage filter capacitor crrent, PI( )FB(i C ). (b) Cascaded control scheme with two PI controllers, one for the otpt voltage and one for the inverter otpt crrent, PI( )PI( ). R D L D R D L D i ot C C C 2 C C 2 P PI K co K L - G C - KR G = s Control C: PI( ) P( ) Control D: I( ) FB( C, ) (c) Cascaded control scheme with one PI voltage controller for the otpt voltage and one proportional inverter otpt crrent controller, PI( )P( ). (d) Three-loop control scheme: otpt voltage loop, first filter stage capacitor voltage loop and inverter otpt crrent loop, I( )FB( C, ). Fig. Control schemes for the AC power sorce. crrent i ot and the reference voltage are inclded [cf. Fig. (b)]. C. PI( )P( ): PI controller for the oter voltage control loop and proportional (P) controller for the inverter otpt crrent in the inner loop. Feedforward loops for the otpt crrent and reference voltage are inclded [cf. Fig. (c)]. D. I( )FB( C, ): integral (I) controller for the oter voltage control loop and two inner feedback loops, one for the voltage across the capacitor of the first filter stage, C, and one for the inverter otpt crrent [cf. Fig. (d)]. These control schemes can be classified into three grops according to the nmber of control loops. The PI( )FB(i C ) scheme can be considered as single-loop control, with only one voltage controller for an actively damped filter. The PI( )PI( ) and PI( )P( ) schemes correspond to a two-loop strctre, with one control loop for the otpt voltage and one control loop for the inverter otpt crrent. The I( )FB( C, ) scheme is a threeloop strctre with an external otpt voltage control loop and two internal feedback loops. In order to compare the different control schemes nder similar conditions, the voltage controllers have been adjsted to obtain the fastest possible response with the limitation of a maximm overshoot of % in the otpt voltage nder different load conditions. A. PI voltage control and capacitor crrent feedback [PI( )FB(i C )] The strctre of this controller considers a single PI controller for the otpt voltage and an active damping of the first filter stage sing the capacitor crrent i C. A block diagram of this scheme is shown in Fig. (a). A single voltage control loop achieves no damping of the first filter stage. The resonance mst be damped by sing passive elements in the circit (as for the second filter stage) or actively, as shown in Fig. 4(a).

5 L R=k L L ic C C co C i C k (a) LC filter with crrent feedback. (b) Eqivalent circit. 4 x 4 k = [,2] V/A k - PI Fig. 5 Otpt voltage control with a single-stage filter. Imaginary Axis (seconds ) Btterworth Bessel x 4 Real Axis (seconds ) (c) Filter poles. Fig. 4 Poles of a single-stage LC filter for different vales of the capacitor crrent feedback gain k. The feedback gain k can be adjsted to obtain the desired behavior of the filter. If only the first filter stage is considered, the effect of k is identical to the effect of a resistance R in series with the indctor L (cf. Fig. 4(a) and Fig. 4(b)). However, the se of a crrent feedback loop only emlates the resistive behavior bt does not generate the power losses of an actal resistor added in series to the filter. By adjsting k the filter can present a Btterworth or a Bessel response, as shown in Fig. 4(c), or other type of filter response. For a Btterworth response, a feedback gain k = 2Z mst be sed, while for a Bessel response, a higher gain k = Z is reqired. Frthermore, the transfer fnction of a single-stage filter with a capacitor crrent feedback gain k can be compared to the response of a filter with two real poles: G f (s) = sk s 2 (2) L (stn)(st/n) = st(n/n)s 2 T 2, () wheret L andnis a design parameter that represents the separation of the filter poles and defines the dynamics of the filter. Then, the filter gain can be expressed in terms of n and the filter parameters k = L (n/n). (4) Considering this filter design, a PI controller (cf. Fig. 5) can be designed for compensation of the slow pole of the filter, G PI (s) = stn stn ; (5) the reslting closed loop transfer fnction from the reference to the otpt voltage is then G o (s) = G PI(s)G f (s) G PI (s)g f (s) = stns 2 T2, (6) which corresponds to a second order filter with a damping factornand a ct-off freqency/t. In this way,nis adjsted to obtain the desired behavior. As mentioned in the previos section, the overshoot in the otpt voltage is limited to a maximm vale of %. The design parameter n is adjsted accordingly and an optimal feedback gain k is obtained. Considering that the addition of the second filter stage affects the position of the dynamically dominant poles of the first filter stage, as shown in Fig. 6, n and the PI controller gain mst be slightly adjsted to flfill the overshoot reqirement. A feedback gain of k = 5 V/A is obtained in the case at hand after this procedre. The se of a feedback loop for the crrent of the second capacitori is also evalated. Here, the converter voltage is calclated from the otpt of the voltage controller and the capacitor crrents i C and i as: = k i C k 2 i, (7) where k and k 2 are the feedback gains. The feedback gains can be sed to move the filter poles and to adjst the damping of the filter resonances. The effect of the feedback gains k and k 2 on the placement of the filter poles is shown in Fig. 7. Only the inner loop is considered for these reslts (no voltage control loop). It can be observed in Fig. 7(a) that increasing k moves the filter poles to the left side of the complex plane, providing damping of the resonances of both filter stages. By increasing the feedback gain k 2 the poles of the first stage of the filter move to the left while the poles of the second stage move to the right, as shown in Fig. 7(b).

6 Imaginary Axis (seconds ) k =5 V/A 2 x 5 L i C i C k C C 2 k C Gain [db] Phase [deg] Simlation reslt Analytical model Real Axis (seconds ) x 4 Fig. 6 Poles of the filter with feedback for a single-stage filter and a two-stage filter. Both systems sing the capacitor crrent feedback with gain k = 5 V/A and no load is connected at the otpt of the filter. 2 4 Freqency [Hz] Fig. 8 Transfer fnctions from the reference to the otpt voltage for the PI()FB(i C) scheme for a resistive load of 6Ω (nominal load) Imaginary Axis (seconds ) x 5 k =[,2] V/A, k 2 = first stage filter poles Real Axis (seconds ) (a) Effect of k. second stage filter poles x 4 Imaginary Axis (seconds ) x 5 k =, k 2 =[,2]V/A first stage filter poles Real Axis (seconds ) (b) Effect of k 2. second stage filter poles Fig. 7 Effect of crrent feedback gains k and k 2 on the poles of the system (the passive damping elements of the filter are not considered for these reslts). Otpt voltage is in open loop operation (no voltage controller). No load is connected to the filter. x 4 Otpt voltage [V] Otpt voltage [V] (simlation) (analytical model ) (simlation) (analytical model ) Fig. 9 Otpt voltage step responses for the PI()FB(i C) scheme. Top: 6 Ω resistive load (nominal load),.7% overshoot. Bottom: No load,.% overshoot. Note that the poles of the second stage enter the right half plane, making the filter nstable. Considering these reslts, feedback of the capacitor crrent i is not sed in order to avoid instabilities. The controller design is verified sing a detailed analytical model of the AC sorce, considering the discrete-time implementation of the controller. A control bandwidth (- db) for the otpt voltage of 5.9 khz is achieved, as it can be observed from Fig. 8. This transfer fnction has been calclated analytically sing Matlab and then verified with simlations of the controlled power sorce sing GeckoCIRCUITS. The step responses with and withot load are shown in Fig. 9 for simlations and theoretical reslts from the analytical model. It can be observed that the highest overshoot is present dring operation withot load, for missing damping by a load resistance. B. PI voltage control and PI crrent control [PI( )PI( )] A cascaded control scheme consisting of an inner crrent control loop and an oter voltage control loop is considered as the common strctre for the control of high-bandwidth AC power sorces [6], [7]. The se of the inner loop for controlling the inverter otpt crrent gives the opportnity of crrent limitation and therefore to protect the inverter against overcrrents. The dynamic response and compensation of load crrent harmonics can be improved by the inclsion of a feedforward of the reference voltage and of the load crrenti ot. The control scheme shown in Fig. (b) illstrates the implementation of these ideas. In this scheme a PI controller is sed for the otpt voltage control loop and a second PI controller is sed for the inner crrent control loop. The controllers can be designed

7 Gain [db] Phase [deg] Simlation reslt Analytical model Freqency [Hz] Fig. Transfer fnctions from the reference to the otpt voltage for the PI()PI() scheme for a resistive load of 6Ω (nominal load). Otpt voltage [V] Otpt voltage [V] (simlation) (analytical model ) (simlation) (analytical model ) Fig. Otpt voltage step responses for the PI()PI() scheme. Top: 6 Ω resistive load (nominal load),.8% overshoot. Bottom: No load, % overshoot. independently if the inner control loop is mch faster than the oter loop. The inner control loop has been adjsted sing a simple model of the indctor of the first stage of the filter as the controlled system. Then, a detailed model, inclding the inner loop and feedforward loops, is sed for the adjstment of the voltage controller. The analytical and simlated reslts of the transfer fnction show that a small-signal control bandwidth (- db) of.7 khz is achieved (cf. Fig. ). The step responses are shown in Fig., where it can be observed that a very low overshoot occrs with nominal load, bt a rather high overshoot appears when no load is connected to the otpt of the filter. C. PI voltage control and P crrent control [PI( )P( )] In order to achieve the fastest possible response of the inner control loop, the previos control scheme can be slightly modified for sing the deadbeat control concept for the inner loop. This concept has been proposed in [] and [4] for ninterrptible power spplies with a single-stage LC filter, where deadbeat control is sed of the inner and oter loops. In this paper, a PI controller is preferred for the oter loop in order to ensre a very low steady-state error for the otpt voltage (zero error for DC references). Deadbeat control ses the system model to calclate the reqired converter voltage that makes the crrent error eqal to zero in one single sampling interval. The eqation that describes the dynamic behavior of the inverter otpt crrent is, based on the circit diagram of Fig. : L d dt = C. (8) By approximating the time derivative and assming that the desired behavior of the system is to reach a crrent error of zero after one sampling interval, i.e. (k) = i L (k), the reqired converter voltage for the deadbeat crrent controller is expressed as (k) = C (k)l i L (k) (k) T s. (9) Considering that the capacitor voltage C is not measred, and that the dynamics of the oter control loop are mch slower, it can be assmed that C and the reslting crrent controller is eqivalent to a proportional controller with voltage feedforward: (k) = (k)l i L (k) (k). () T s The block diagram for this control scheme is shown in Fig. (c). By sing a mch faster inner control loop the oter control loop bandwidth can be increased, improving the overall performance of the power sorce. The analytical and simlated reslts for the transfer fnction show that a rather high control bandwidth (- db) of 9 khz is achieved (cf. Fig. 2). However, it can be observed that a difference between the simlated and analytical reslts appears for freqencies higher than khz de to the voltage limitation of the inverter, which is not considered in the analytical model. The step responses are shown in Fig., where it can be observed that a very fast response is achieved with this scheme. The highest overshoot is observed at no load operation. D. Three-Loop Control [I( )FB( C, )] A three-loop control scheme has been proposed in [5] to improve the dynamic performance of the otpt voltage of the power sorce, compared to a two-loop control (withot feedforward loops), like the one presented in [7]. In addition to the bridge-leg crrent and otpt voltage feedback loops, a feedback loop for the capacitor voltage C is inclded, as depicted in Fig. (d). According to the gidelines provided in [5], an integrator

8 Gain [db] Simlation reslt Analytical model Gain [db] Simlation reslt Analytical model Phase [deg] Freqency [Hz]. 4 Phase [deg] Freqency [Hz]. 4 Fig. 2 Transfer fnctions from the reference to the otpt voltage for the PI()P() scheme (deadbeat control of ) for a resistive load of 6 Ω (nominal load). Satration of the controller for freqencies over khz is observed for the simlation reslts. Fig. 4 Transfer fnctions from the reference to the otpt voltage for the I()FB( C,) scheme for a resistive load of 6Ω (nominal load). Otpt voltage [V] Otpt voltage [V] (simlation) (analytical model ) (simlation) (analytical model ) Fig. Otpt voltage step responses for the PI()P() scheme (deadbeat control of ). Top: 6Ω resistive load (nominal load), 2% overshoot. Bottom: No load, % overshoot. Otpt voltage [V] Otpt voltage [V] (simlation) (analytical model ) (simlation) (analytical model ) Fig. 5 Otpt voltage step responses for the I()FB( C,) scheme. Top: 6 Ω resistive load (nominal load), 2.% overshoot. Bottom: No load, % overshoot. is sed for the otpt voltage feedback loop: G = K R s, () where the integrator gain K R determines the attenation of the closed-loop transfer fnctions in the low-freqency range. The capacitor voltage feedback loop considers a low-pass filter G C = K C st C, (2) where the filter pole is placed slightly beyond the resonance of L 2 and, i.e. at T C = L 2 /.2. For the indctor crrent feedback, the gain K L is set as high as possible withot casing instability. A control bandwidth (- db) of 4.6 khz is achieved with this control scheme, as observed from the transfer fnctions of Fig. 4. The corresponding step responses are shown in Fig. 5. The highest overshoot appears when no load is connected to the otpt filter. IV. COMPARISON OF RESULTS Simlations of the power sorce circit shown in Fig. are setp in GeckoCIRCUITS [6] where the different control schemes have been implemented digitally. One sampling time delay has been inclded in the control in order to emlate the delay introdced by the analog to digital conversion and calclation time of the control algorithms in the digital signal processor. As it is sal in a practical implementation, a delay compensation techniqe as the one presented in [7] and [8] is inclded in all the controllers. The carrier freqency for the plse-width modlation is 48 khz and the sampling freqency for the control is 96 khz

9 Gain [db] Phase [deg] 6 A. PI( ) FB( i C ) 9 B. PI( ) PI( ) 2 C. PI( ) P( ) 5 D. I( ) FB(, ) 8 C Freqency [Hz] Otpt voltage [V] A. PI( ) FB( i C ) B. PI( ) PI( ) C. PI( ) P( ) D. I( ) FB( C, ) Fig. 6 Transfer fnctions from the reference to the otpt voltage obtained by simlation for a resistive load of 6 Ω (nominal load). Fig. 7 Simlation reslts for a step change in the reference voltage for a resistive load of 6Ω (nominal load). (doble-pdate mode). The filter parameters sed in the simlations are listed in Table I. The transfer fnction from the reference to the otpt voltage is calclated from simlation reslts by sing a reference voltage composed of a DC vale pls a % AC component, i.e. = U.U sin(ωt). Simlation reslts for the different control schemes are shown in Fig. 6 for a DC voltage vale U = V. It can be observed that the highest bandwidth is obtained with the PI( )P( ) scheme, followed by the PI( )FB(i C ) scheme. For freqencies higher than khz the voltage limitation of the inverter is observed. The step responses for a nominal resistive load of 6 Ω shown in Fig. 7 illstrate the reference tracking capabilities of the different control schemes. It is observed that all control schemes present a low overshoot (below 2.%) for this loading. The fastest responses are achieved by the PI( )P( ) and PI( )FB(i C ) schemes, in concordance with the respective control bandwidths. The highest overshoot in the otpt voltage is observed nder no load operation and has been fixed by design to % for all control schemes. Simlation reslts for a step change in the reference voltage for no load operation are shown in Fig. 8. In addition to the reference tracking, another important measre of the qality of a power sorce is the rejection of distrbances coming from the load crrent, which is eqivalent TABLE I Two-stage LC otpt filter vales (cf. Fig. ) sed for the simlations. Component Vale L 28µH L 2 2µH 6.µF C 2.8µF L D.5µH R D 2.2Ω Otpt voltage [V] A. PI( ) FB( i C ) B. PI( ) PI( ) C. PI( ) P( ) D. I( ) FB( C, ) Fig. 8 Simlation reslts for a step change in the reference voltage nder no load operation. to a low otpt impedance. The otpt impedance of the power spply has been compted by simlations sing a controlled crrent sorce as a load. For a constant voltage reference a load crrent composed of a DC component and an AC sinsoidal component ĩ f,i of variable freqency f i is injected. Then, the AC component in the otpt voltage ũ f,i is measred at the corresponding freqency and the otpt impedance is calclated as z ot,i = ũ f,i ĩ f,i. () The reslts obtained in this way are shown in Fig. 9. The lowest otpt impedance is obtained with the PI( )P( ) and the PI( )FB(i C ) scheme, with an otpt impedance of.5ω and.7ω, respectively, measred at khz. The lowest peak vale is obtained with the I( )FB( C, ) scheme, with 5Ω at 5 khz. For freqencies higher than 5 khz the voltage limitation of the inverter is observed. The response to a step change in the load crrent from A to 5 A

10 TABLE II Performance indexes for the different controller strctres. Performance index PI( )FB(i C ) PI( )PI( ) PI( )P( ) I( )FB( C, ) Control bandwidth (- db) 5.9 khz.7 khz 9. khz 4.6 khz Overshoot (6 Ω nominal load).7%.8% 2.% 2.% Overshoot (no load).%.%.%.% Otpt impedance at khz.7ω 4.9Ω.5Ω.9Ω Otpt impedance (max) 8.5 Ω 5.6 Ω 6.2 Ω 5. Ω Otpt impedance [ Ω] 2 A. PI( ) FB( i C ) B. PI( ) PI( ) C. PI( ) P( ) D. I( ) FB( C, ) Freqency [Hz] Fig. 9 Otpt impedances obtained from simlation reslts. Otpt voltage [V] Load crrent [A] 5 A. PI( ) FB( i C ) B. PI( ) PI( ) 295 C. PI( ) P( ) D. I( ) FB( C, ) Fig. 2 Simlation reslts for a step change in the load crrent. is shown in Fig. 2. A voltage drop of 5.5 V is observed for the PI( )P( ) scheme. A similar voltage drop is observed for the I( )FB( C, ) scheme, bt the distrbance is sppressed with slower dynamics, compared to the PI( )P( ) scheme. A smmary of the comparative reslts is presented in Table II. From these reslts, it is clear that the highest bandwidth and lowest otpt impedance (at khz) is achieved by the PI( )P( ) scheme. The second highest bandwidth is achieved by the PI( )FB(i C ) scheme, which is also second in terms of otpt impedance. However, from the for control schemes, the PI( )FB(i C ) presents the highest peak vale of the otpt impedance. The I( )FB( C, ) scheme presents the lowest peak vale of the otpt impedance and the third highest control bandwidth. The lowest bandwidth and the highest otpt impedance is achieved with the PI( )PI( ) scheme. However, this scheme presents the lowest overshoot nder nominal load. V. CONCLUSIONS For mlti-loop control schemes for a high-bandwidth power sorce with a two-stage LC otpt filter are evalated in this paper. All these schemes have an otpt voltage controller in the oter loop, and for the inner control loop the following options are evalated: capacitor crrent feedbacks, proportional-integral crrent control, proportional (deadbeat) crrent control, and capacitor voltage and inverter otpt crrent feedbacks. The comparative evalation considers the small-signal control bandwidth, overshoot in the otpt voltage for step in the reference and load changes and otpt impedance as performance indexes. According to the obtained reslts, the best dynamic performance, with respect to the defined indexes, is obtained sing a cascaded strctre with a PI controller for the voltage control and a proportional controller for the inner crrent control loop (PI( )P( ) scheme). Another advantage of this scheme is the simplicity in the adjstment of the crrent controller, compared to the other three schemes. The sensitivity of this control scheme to errors in the applied voltage (e.g. cased by semicondctor on-state voltage drops or PWM errors) and filter parameters needs to be verified. A different concept that also presents good performance indexes is the PI( )FB(i C ) scheme. This scheme allows a more intitive approach by sing an active damping of the resonance of the first stage of the filter. In the corse of ftre research, the optimal selection of the feedback gains will be considered. Frthermore, experimental verification of the theoretical reslts will be performed for a kw laboratory prototype. REFERENCES [] R. Lohde and F. Fchs, Laboratory type PWM grid emlator for generating distrbed voltages for testing grid connected devices, in Proceedings of the th Eropean Conference on Power Electronics and Applications (EPE), Sept. 29, pp. 9.

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