HCPL-260L/060L/263L/063L High Speed LVTTL Compatible 3.3 Volt Optocouplers. Features. Applications V O1 GND

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1 HCPL-L/L/L/L High Speed LVTTL Compatible. Volt Optocouplers Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The HCPL-L/L/L/L are optically coupled gates that combine a GaAsP light emitting diode and an integrated high gain photo detector. An enable input allows the detector to be strobed. The output of the detector IC is an open collector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of kv/µs at.v. This unique design provides maximum AC and DC circuit isolation while achieving LVTTL/LVCMOS compati-bility. The optocoupler AC and DC operational parameters are guaranteed from C to + C allowing troublefree system performance. These optocouplers are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate and are recommended for use in extremely high ground or induced noise environments. Functional Diagram NC ANODE CATHODE NC HCPL-L/L SHIELD LED ENABLE ON H OFF H ON L OFF L ON NC OFF NC TRUTH TABLE (POSITIVE LOGIC) V CC V E VO OUTPUT L H H H L H ANODE CATHODE CATHODE ANODE HCPL-L/L SHIELD TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H V CC V O VO A. µf bypass capacitor must be connected between pins and. Features.V/V Dual Supply Voltages Low power consumption kv/µs minimum Common Mode Rejection (CMR) at V CM = V High speed: MBd typical LVTTL/LVCMOS compatible Low input current capability: ma Guaranteed AC and DC performance over temperature: C to + C Available in -pin DIP, SOIC- Strobable output (single channel products only) Safety approvals: UL, CSA, IEC/EN/DIN EN -- Applications Isolated line receiver Computer-peripheral interfaces Microprocessor system interfaces Digital isolation for A/D, D/A conversion Switching power supply Instrument input/output isolation Ground loop elimination Pulse transformer replacement Field buses CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Ordering Information HCPL-xxxx is UL Recognized with Vrms for minute per UL Part number HCPL-L HCPL-L HCPL-L HCPL-L RoHS Compliant Option Non RoHS Compliant -E No option Package Surface Mount Gull Wing Tape & Reel UL Vrms/ Minute rating IEC/EN/DIN EN -- Quantity per tube -E - X X per tube -E # X X X per reel -E - mil X per tube -E - DIP- X X X per tube -E - X X X X per reel -E # X per tube -E # X X X X per reel -E No option per tube -E # X X per tube -E # X X X per reel -E # mil X per tube -E - DIP- X X X per tube -E # X X X X per reel -E - X per tube -E - X X X X per reel -E No option X per tube -E # X X per reel SO- -E # X X per tube -E - X X X per reel -E No option X per tube -E # X X per reel SO- -E - X X per tube -E - X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Combination of Option and Option is not available. Example : HCPL-L-E to order product of mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN -- Safety Approval in RoHS compliant. Example : HCPL-L to order product of mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since th July and RoHS compliant option will use -XXXE.

3 UR Schematic HCPL-L/L I F ICC V CC + I O V O + V F I F HCPL-L/L I CC I O V CC V O V F SHIELD I E V E USE OF A. µf BYPASS CAPACITOR CONNECTED BETWEEN PINS AND IS RECOMMENDED (SEE NOTE ). V F SHIELD I O V O + I F SHIELD Package Outline Drawings -Pin DIP Package 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER A XXXXZ OPTION CODE* DATE CODE. ±. (. ±.) YYWW UL RECOGNITION.9 (.) MAX.. ±. (. ±.). (.) MAX.. (.) MAX. TYP (. +.) -.).9 (.) MIN.. (.) MIN.. ±. (. ±.). (.) MAX.. ±. (. ±.) DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS "V" = OPTION OPTION NUMBER NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

4 -Pin DIP Package with Gull Wing Surface Mount in Option (HCPL-L, HCPL-L) 9. ±. (. ±.) LAND PATTERN RECOMMENDATION. (.). ±. (. ±.).9 (.). (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.).... (..). ±. (. ±.). (.) BSC. ±. (. ±.). ±. (. ±.) NOM. DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES). NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. Small Outline SO- Package LAND PATTERN RECOMMENDATION.9 ±. (. ±.) PIN ONE XXXV YWW.99 ±. (. ±.). ±. (. ±.). (.) BSC TYPE NUMBER (LAST DIGITS) DATE CODE. (.).9 (.).9 (.9) *. ±. (. ±.) X. (.). ±. (. ±.). (.) ~. ±. (.9 ±.) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH). ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES) MAX.. ±. (. ±.). (.) MIN. OPTION NUMBER NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

5 Reflow Soldering Profile Recommended reflow condition as per JEDEC Standard, J-STD- (latest revision). Non-Halide Flux should be used. Regulatory Information The HCPL-L/L/L/L have been approved by the following organizations: UL Approval under UL, Component Recognition Program, File E. CSA Approval under CSA Component Acceptance Notice #, File CA. IEC/EN/DIN EN -- Insulation and Safety Related Specifications -Pin DIP ( Mil) SO- Parameter Symbol Value Value Units Conditions Minimum External Air L ()..9 mm Measured from input terminals to output Gap (External Clearance) terminals, shortest distance through air. Minimum External Tracking L ().. mm Measured from input terminals to output (External Creepage) terminals, shortest distance path along body. Minimum Internal Plastic.. mm Through insulation distance, conductor Gap (Internal Clearance) to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Tracking Resistance CTI Volts DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa IIIa Material Group (DIN VDE, /9, Table )

6 IEC/EN/DIN EN -- Insulation Characteristics* Description Symbol PDIP Option SO- Option Unit Installation classification per DIN VDE, Table for rated mains voltage Vrms for rated mains voltage Vrms for rated mains voltage Vrms Climatic Classification // // Pollution Degree (DIN VDE /9) Maximum Working Insulation Voltage V IORM Vpeak Input to Output Test Voltage, Method b* V PR Vpeak V IORM x. = V PR, % Production Test with t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a* V PR 9 Vpeak V IORM x. = V PR, Type and Sample Test, t m = sec, Partial discharge < pc Highest Allowable Overvoltage V IOTM Vpeak (Transient Overvoltage t ini = sec) Safety-limiting values maximum values allowed in the event of a failure. Case Temperature T S C Input Current I S, INPUT ma Output Power P S, OUTPUT mw Insulation Resistance at T S, V IO = V R S 9 9 W *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN --, for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. I IV I IV I III I IV I IV I III Thermal Derating Curve Figures OUTPUT POWER P S, INPUT CURRENT I S HCPL-L/HCPL-L P S (mw) I S (ma) T S CASE TEMPERATURE C OUTPUT POWER P S, INPUT CURRENT I S HCPL-L/HCPL-L P S (mw) I S (ma) T S CASE TEMPERATURE C

7 Absolute Maximum Ratings (No Derating Required up to C) Parameter Symbol Package** Min. Max. Units Note Storage Temperature T S C Operating Temperature T A C Average Forward Input Current I F Single -Pin DIP ma Single SO- Dual -Pin DIP, Dual SO- Reverse Input Voltage V R -Pin DIP, SO- V Input Power Dissipation P I mw Supply Voltage ( Minute Maximum) V CC V Enable Input Voltage (Not to Exceed V E Single -Pin DIP V CC +. V V CC by more than mv) Single SO- Enable Input Current I E ma Output Collector Current I O ma Output Collector Voltage V O V Output Collector Power Dissipation P O Single -Pin DIP mw Single SO- Dual -Pin DIP, Dual SO- **Ratings apply to all devices except otherwise noted in the Package column. Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Current, Low Level I FL * µa Input Current, High Level [] I FH ** ma Power Supply Voltage V CC.. V.. Low Level Enable Voltage V EL. V High Level Enable Voltage V EH. V CC V Operating Temperature T A C Fan Out (at R L = kω) [] N TTL Loads Output Pull-up Resistor R L k Ω *The off condition can also be guaranteed by ensuring that V FL. volts. **The initial switching threshold is ma or less. It is recommended that. ma to ma be used for best performance and to permit at least a % LED degradation guardband.

8 Electrical Specifications Over Recommended Operating Conditions (T A = C to + C,.V V CC.V) unless otherwise specified. All Typicals at V CC =. V, T A = C. All enable test conditions apply to single channel products only. See Note. Parameter Sym. Device Min. Typ. Max. Units Test Conditions Fig. Note High Level I OH *. µa V CC =. V, V E =. V,, Output Current V O =. V, I F = µa Input Threshold I TH.. ma V CC =. V, V E =. V, Current V O =. V, I OL (Sinking) = ma Low Level V OL *.. V V CC =. V, V E =. V, Output Voltage I F = ma, I OL (Sinking) = ma High Level I CCH Single.. ma V E =. V I F = ma Supply Current Dual.9. V CC =. V Low Level I CCL Single.. ma V E =. V I F = ma Supply Current Dual.. V CC =. V High Level I EH Single.. ma V CC =. V, V E =. V Enable Current Low Level I EL * Single.. ma V CC =. V, V E =. V Enable Current High Level V EH Single. V Enable Voltage Low Level V EL Single. V Enable Voltage Input Forward V F...* V T A = C, I F = ma Voltage Input Reverse BV R * V I R = µa Breakdown Voltage Input Diode V F /. mv C I F = ma Temperature T A Coefficient Input C IN pf f = MHz, V F = V Capacitance *The JEDEC Registration specifies C to + C. Avago specifies C to + C.

9 Electrical Specifications (DC) Over recommended operating conditions (T A = - C to + C,.V V DD.V) unless otherwise specified. All typicals at V CC = V, T A = C. Parameter Symbol Channel Min. Typ.* Max. Units Test Conditions Fig. Note High Level Output Current Input Threshold Current Low Level Output Voltage High Level Supply Current Low Level Supply Current High Level Enable Current Low Level Enable Current High Level Enable Voltage Low Level Enable Voltage Input Forward Voltage Input Reverse Breakdown Voltage Input Diode Temperature Coefficient I OH. ma V CC =. V, V O =. V, I FL = ma I TH Single.. ma V CC =. V, V O =. V, Dual. I OL > ma V OL.. V V CC =. V, I F = ma, I OL (Sinking) = ma I CCH Single.. ma V E =.V, V CC =. V, I F = ma. ma V E =V CC, V CC =. V, I F = ma Dual.. V CC =. V, IF = ma I CCL Single 9.. ma V E =.V, V CC =. V, I F = ma. ma V E =V CC, Vv =. V, IF = ma Dual.. ma V CC =. V, I F = ma I EH Single ma V CC =. V, V E =.V I EL Single ma V CC =. V, V E =.V, V EH Single. V V EL Single. V V F... V T A = C, I F = ma.. V IF=mA BV R V I R = μa ΔV F /ΔT A -. mv/ C I F = ma Input Capacitance C IN pf f = MHz, V F = V 9

10 Switching Specifications Over Recommended Operating Conditions (T A = C to + C,.V V CC.V), I F =. ma unless otherwise specified. All Typicals at T A = C, V CC =. V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Pulse Width Distortion Propagation Delay Skew Output Rise Time (-9%) Output Fall Time (9-%) Propagation Delay Time of Enable from V EH to V EL Propagation Delay Time of Enable from V EL to V EH t PLH 9 ns R L = Ω C L = pf t PHL ns R L = Ω C L = pf t PHL t PLH ns R L = Ω C L = pf t PSK ns R L = Ω C L = pf t r ns R L = Ω C L = pf t f ns R L = Ω C L = pf t ELH ns R L = Ω, C L = pf, V EL = V, V EH = V t EHL ns R L = Ω, C L = pf, V EL = V, V EH = V,,,,, 9,, 9,,, 9 9 Switching Specifications (AC) Over recommended operating conditions T A = - C to C,. Vcc.V, I F =. ma unless otherwise specified. All typicals at V CC = V, T A = C. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level t PLH ns T A = C, R L = W, C L = pf t PHL ns T A = C, R L = W, C L = pf Pulse Width Distortion t PHL - t PLH. ns R L = W, C L = pf Propagation Delay Skew Output Rise Time (%-9%) Output Fall Time (%-9%) Propagation Delay Time of Enable from V EH to V EL Propagation Delay Time of Enable from V EL to V EH T PSK ns R L = W, C L = pf t r ns R L = W, C L = pf t f ns R L = W, C L = pf t ELH ns R L = W, C L = pf, V EL =V, V EH =V t EHL ns R L = W, C L = pf, V EL =V, V EH =V,,,,,, 9,,9,,, 9 9

11 Parameter Sym. Device Min. Typ. Units Test Conditions Fig. Note Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity CM H CM L CM H CM L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L HCPL-L kv/ms V CC =. V, I F = ma, V O(MIN) = V, R L = W, T A = C, V CM = V and V CM = V kv/ms V CC =. V, I F =. ma, V O(MAX) =. V, R L = W, T A = C, V CM = V and V CM = V kv/ms V CC = V, I F = ma, V O(MIN) = V, R L = W, T A = C, V CM = V kv/ms V CC = V, I F =. ma, V O(MAX) =. V, R L = W, T A = C, V CM = V,,,,,,,,

12 Package Characteristics All Typicals at T A = C. Parameter Sym. Package Min. Typ. Max Units Test Conditions Fig. Note Input-Output I I-O * Single -Pin DIP µa % RH, t = s,, Insulation Single SO- V I-O = kv DC, T A = C Input-Output V ISO -Pin DIP, SO- V rms RH %, t = min,, Momentary T A = C Withstand Voltage** Input-Output R I-O -Pin, SO- Ω V I-O = V dc,, 9 Resistance Input-Output C I-O -Pin DIP, SO-. pf f = MHz, T A = C,, 9 Capacitance Input-Input I I-I Dual Channel. µa RH %, t = s, Insulation V I-I = V Leakage Current Resistance R I-I Dual Channel Ω (Input-Input) Capacitance C I-I Dual -Pin Dip. pg f = MHz (Input-Input) Dual SO-. *The JEDEC Registration specifies C to + C. Avago specifies C to + C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN -- Insulation Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note entitled "Optocoupler Input-Output Endurance Voltage." Notes:. Each channel.. Peaking circuits may produce transient input currents up to ma, ns maximum pulse width, provided average current does not exceed ma.. Peaking circuits may produce transient input currents up to ma, ns maximum pulse width, provided average current does not exceed ma.. Derate linearly above + C free-air temperature at a rate of. mw/ C for the SOIC- package.. Bypassing of the power supply line is required, with a. µf ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure. Total lead length between both ends of the capacitor and the isolator pins should not exceed mm.. The t PLH propagation delay is measured from the. ma point on the falling edge of the input pulse to the. V point on the rising edge of the output pulse.. The t PHL propagation delay is measured from the. ma point on the rising edge of the input pulse to the. V point on the falling edge of the output pulse.. t PSK is equal to the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature and specified test conditions. 9. See test circuit for measurement details.. The t ELH enable propagation delay is measured from the. V point on the falling edge of the enable input pulse to the. V point on the rising edge of the output pulse.. The t EHL enable propagation delay is measured from the. V point on the rising edge of the enable input pulse to the. V point on the falling edge of the output pulse.. CM H is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state (i.e., V o >. V).. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V o <. V).. For sinusoidal voltages, ( dv CM / dt) max = πf CM V CM (p-p).. No external pull up is required for a high logic state on the enable input. If the V E pin is not used, tying V E to V CC will result in improved CMR performance. For single channel products only. See application information provided.. Device considered a two-terminal device: pins,,, and shorted together, and pins,,, and shorted together.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (Method b) shown in the IEC/ EN/DIN EN -- Insulation Characteristics Table, if applicable.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (Method b) shown in the IEC/ EN/DIN EN -- Insulation Characteristics Table, if applicable. 9. Measured between the LED anode and cathode shorted together and pins through shorted together. For dual channel products only.. Measured between pins and shorted together, and pins and shorted together. For dual channel products only.

13 I OH HIGH LEVEL OUTPUT CURRENT µa - V CC =. V V O =. V V E =. V* I F = µa * FOR SINGLE CHANNEL PRODUCTS ONLY - - I OH HIGH LEVEL OUTPUT CURRENT µa - V CC =. V V O =. V V E =. V* I F = µa * FOR SINGLE CHANNEL PRODUCTS ONLY - - Figure. Typical high level output current vs. temperature. I TH INPUT THRESHOLD CURRENT ma -PIN DIP, SO- V CC =. V V O =. V R L = KΩ R L = KΩ R L = KΩ I TH INPUT THRESHOLD CURRENT ma V CC =. V V O =. V -PIN DIP, SO- R L = KΩ R L = Ω R L = KΩ Figure. Typical output voltage vs. forward input current. V OL LOW LEVEL OUTPUT VOLTAGE V V CC =. V V E =. V* I F =. ma -PIN DIP, SO- * FOR SINGLE CHANNEL PRODUCTS ONLY I O = ma V OL LOW LEVEL OUTPUT VOLTAGE V V CC =. V V E =. V* I F =. ma -PIN DIP, SO- I O = ma I O = 9. ma * FOR SINGLE CHANNEL PRODUCTS ONLY I O =. ma I O =. ma Figure. Typical low level output voltage vs. temperature.

14 I OL LOW LEVEL OUTPUT CURRENT ma V CC =. V V E =. V* V OL =. V * FOR SINGLE CHANNEL PRODUCTS ONLY I F =. ma I OL LOW LEVEL OUTPUT CURRENT ma V CC =. V V E =. V* V OL =. V * FOR SINGLE CHANNEL PRODUCTS ONLY I F = - ma I F =. ma Figure. Typical low level output current vs. temperature. I F FORWARD CURRENT ma PIN DIP, SO- T A = C I F + V F..... V F FORWARD VOLTAGE V Figure. Typical input diode forward characteristic. PULSE GEN. Z O = Ω t f = t r = ns INPUT MONITORING NODE I F R M SINGLE CHANNEL V CC.V or V. µf BYPASS *C L R L PULSE GEN. Z O = Ω t f = t r = ns INPUT MONITORING NODE OUTPUT V O MONITORING NODE I F R M DUAL CHANNEL V CC.V or V. µf BYPASS R L C L * OUTPUT V O MONITORING NODE *C L IS APPRO IMATELY F HICH INCLUDES PROBE AND STRAY IRING CAPACITANCE. INPUT I F I F =. A I F =. A t PHL t PLH OUTPUT V O. V Figure. Test circuit for t PHL and t PLH.

15 t P PROPAGATION DELAY ns 9 V CC =. V I F =. ma t PLH, R L = Ω t PHL, R L = Ω t P - PROPAGATION DELAY - ns V CC =. V I F =. ma t PHL, R L = Ω KΩ KΩ t PLH, R L = Ω t PLH, R L = KΩ t PLH, R L = KΩ T A - TEMPERATURE - C Figure. Typical propagation delay vs. temperature. PWD PULSE WIDTH DISTORTION ns - R L = Ω V CC =. V I F =. ma - - PWD - PULSE WIDTH DISTORTION - ns - - R L = kω R L = Ω R L = kω V CC =. V I F =. ma - - T A - TEMPERATURE - o C Figure. Typical pulse width distortion vs. temperature.

16 PULSE GEN. Z O = Ω t f = t r = ns INPUT V E MONITORING NODE.V or V. ma I F V CC. µf BYPASS R L INPUT V E t EHL t ELH. V. V *C L OUTPUT V O MONITORING NODE OUTPUT V O. V *C L IS APPROXIMATELY pf WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 9. Test circuit for t EHL and t ELH. I F I F V FF B A V CC SINGLE CHANNEL. µf BYPASS R L.V or V OUTPUT V O MONITORING NODE V FF B A DUAL CHANNEL V CC R L. µf BYPASS.V or V OUTPUT V O MONITORING NODE V CM + PULSE GENERATOR Z O = Ω V CM V CM PEA V CM + PULSE GENERATOR Z O = Ω V S ITCH AT A IF = A V V O V O MIN. S ITCH AT B I F =. A V V O MA. O. V CM H CM L Figure. Test circuit for common mode transient immunity and typical waveforms. BUS (BACK) V CC BUS (FRONT) NC.µF ENABLE NC OUTPUT mm MAX. (SEE NOTE ) SINGLE CHANNEL DEVICE ILLUSTRATED. Figure. Recommended printed circuit board layout.

17 SINGLE CHANNEL DEVICE V CC. V or V. V or V V CC Ω R L D* I F + V F SHIELD V E. µf BYPASS *DIODE D (N9 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. V CC. V or V DUAL CHANNEL DEVICE CHANNEL SHOWN. V or V V CC Ω D* I F + V F SHIELD R L. µf BYPASS Figure. Recommended LVTTL interface circuit.

18 Application Information Common-Mode Rejection for HCPL-L Families: Figure shows the recom mended drive circuit for optimal common-mode rejection performance. Two main points to note are:. The enable pin is tied to V CC rather than floating (this applies to single-channel parts only).. Two LED-current setting resistors are used instead of one. This is to balance I LED variation during commonmode transients. If the enable pin is left floating, it is possible for commonmode transients to couple to the enable pin, resulting in common-mode failure. This failure mechanism only occurs when the LED is on and the output is in the Low State. It is identified as occurring when the transient output voltage rises above. V. Therefore, the enable pin should be connected to either V CC or logic-level high for best common-mode performance with the output low (CMR L ). This failure mechanism is only present in singlechannel parts which have the enable function. Also, common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side ground causing current to be shunted away from the LED (which can be bad if the LED is on) or conversely cause current to be injected into the LED (bad if the LED is meant to be off). Figure shows the parasitic capacitances which exists between LED anode/cathode and output ground (C LA and C LC ). Also shown in Figure on the input side is an AC-equivalent circuit. For transients occurring when the LED is on, commonmode rejec tion (CMR L, since the output is in the low state) depends upon the amount of LED current drive (I F ). For conditions where I F is close to the switching threshold (I TH ), CMR L also depends on the extent which I LP and I LN balance each other. In other words, any condition where common-mode transients cause a momentary decrease in I F will cause common-mode failure for transients which are fast enough. VCC Ω * HCPL-L. µf Ω VCC+ Ω VO LS OR ANY TOTEM-POLE OUTPUT LOGIC GATE * SHIELD * HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS, TO INPUT GROUND (). Figure. Recommended drive circuit for High-CMR. V CC + / R LED. µf Ω I LP / R LED I LN C LA V O pf C LC SHIELD + V CM Figure. AC equivalent circuit.

19 Likewise for common-mode transients which occur when the LED is off (i.e. CMR H, since the output is high ), if an imbalance between I LP and I LN results in a transient I F equal to or greater than the switching threshold of the optocoupler, the transient signal may cause the output to spike below V (which consti tutes a CMR H failure). By using the recommended circuit in Figure, good CMR can be achieved. The balanced I LED -setting resistors help equalize I LP and I LN to reduce the amount by which I LED is modulated from transient coupling through C LA and C LC. CMR with Other Drive Circuits CMR performance with drive circuits other than that shown in Figure may be enhanced by following these guidelines:. Use of drive circuits where current is shunted from the LED in the LED off state (as shown in Figures and ). This is beneficial for good CMR H.. Use of I FH >. ma. This is good for high CMR L. Figure shows a circuit which can be used with any totem-pole-output TTL/LSTTL/HCMOS logic gate. The buffer PNP transistor allows the circuit to be used with logic devices which have low current-sinking capability. It also helps maintain the driving-gate power-supply current at a constant level to minimize ground shifting for other devices connected to the input-supply ground. When using an open-collector TTL or open-drain CMOS logic gate, the circuit in Figure may be used. When using a CMOS gate to drive the optocoupler, the circuit shown in Figure may be used. The diode in parallel with the R LED speeds the turn-off of the optocoupler LED. L (ANY TTL/CMOS GATE) Figure. TTL interface circuit. V CC HC (OR ANY OPEN-COLLECTOR/ OPEN-DRAIN LOGIC GATE) Ω (MAX) Figure. TTL open-collector/open drain gate drive circuit. HC (OR ANY TOTEM-POLE OUTPUT LOGIC GATE) V CC V CC N9 (ANY PNP) N Ω R HCPL-L LED HCPL-L HCPL-L LED LED Figure. CMOS gate drive circuit. For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright - Avago Technologies. All rights reserved. Obsoletes AV-EN AV-EN - May,