it2025j 30 khz to 18 GHz High-Gain Power Amplifier VCTRL2 VD2 OUT VG2 VG1 Description Features Device Diagram Recommended bias conditions:

Transcription

1 30 khz to GHz High-Gain Power Amplifier Description Features The it2j is a RoHS-6-compliant packaged broadband GaAs MMIC traveling wave amplifier designed for medium output power applications where low-frequency extension capabilities are also required. The it2j provides saturated output power greater than 2 m up to 8 GHz, greater than 23 m up to 6 GHz, and greater than m at GHz. Average gain is greater than 2. DC power consumption as low as 2. W. Input/output ports are DC coupled. Frequency range: 2 GHz GHz with low-frequency extension capability down to 30 KHz >2 m nominal Psat (30 khz 8 GHz) > m nominal Psat (30 khz GHz) >2 nominal gain up to GHz 2. W DC power consumption Nominal DC bias conditions: 8 V at 300 ma Full chip passivation for high reliability RoHS-6-compliant small-form-factor (0.0 x 0.30 x in.) SMD package Device Diagram Both gain stages and their respective RF and DC connections are shown at right. The internal coupling capacitor value between the cascaded gain stages is 0. µf. VD and VD2 are applied to the gain stages through on-chip resistors. IN VCTRL VD Gain VCTRL2 VD2 Gain OUT VG VG2 Recommended bias conditions: VD = 8 V, VG = -0.8 V to 0.9 V, VCTRL = 0 V, ID = 80 ma VD2T = 8 V, VG2 = -0. V to -0.7 V, VCTRL2 = +3. V, ID2T = 2 ma

2 30 khz to GHz High-Gain Power Amplifier Absolute Maximum Ratings Parameter Drain voltage Gate voltage Symbol V D, V D2,, V D2T V G, V G2 Min -2. Max.0 Units V V Notes Notes:. Combinations of drain voltage, drain current, and output power shall not exceed P D at package base temperature of 8 o C. Control voltage Drain current Input power Power dissipation V CTRL V CTRL2 I D, I D2 I D2T P IN P D V D -8V V D2T -8V V D V D2T V ma m W,2 2. Set VG and VG2 such that drain currents are below maximum limits. 3. See Thermal Characteristics. Junction operating temperature Mounting temperature Storage temperature Storage relative humidity T J T M T STO RH STO oc oc oc % 3 Electrical Characteristics (at 2 C) in 0-ohm system. Symbol BW S2 Parameters/conditions Frequency range * Small-signal gain Min Typ. 30 Max. Units GHz S Input return loss 2 S22 Output return loss 7 S2 Isolation 0 Psat Saturated power output (3- gain compression) 30 Hz 8 GHz 30 khz GHz 9 2 m m P Output power (- gain compression) 30 khz 8 GHz 30 khz GHz 22 7 m m OIP3 Output third-order intercept point 32 m NF Noise figure 00 MHz 2 GHz 2 GHz GHz GHz GHz (*) Low-frequency extension available with recommended choke network. 2

3 30 khz to GHz High-Gain Power Amplifier Performance Data T = 2 C Test includes effects of evaluation board. VD = 8 V VCTRL = 0 V ID = 80 ma VD2T = 8 V VCTRL2 = +3. V ID2T = 2 ma S2 () Gain S Freq (GHz) S () Input Return Loss Freq (GHz) S22 () Onput Return Loss Freq (GHz) 3

4 30 khz to GHz High-Gain Power Amplifier Output Power Performance Output Power (m) P P3 P and P3 (2 to GHz) Freq (GHz) Output power at - gain compression (low frequencies) Freq. (GHz) P3 (m) Output power at 3- gain compression (low frequencies) Freq. (GHz)

5 30 khz to GHz High-Gain Power Amplifier Output Power Performance (cont.) OIP3 (m) OIP Freq. (GHz) Noise Figure it2j Noise Figure NF () Freq. GHz

6 30 khz to GHz High-Gain Power Amplifier Circuit Design for low-frequency Extension Applications to 30 khz* Stage amplitude control VDD Stage 2 amplitude control L2 R2 C8 C C L R C3 VD2 VCTRL VD VCTRL2 VD2T C C2 VIN Gain Gain VOUT C6 VG C7 VG2 Stage gate voltage Stage 2 gate voltage Reference Designation Description Manufacturer Part Number C, C2 0. µf cap, 002, XR, V Panasonic ECJ-0EBAK C3 C8.00 µf cap, 0603, XR, 6 V Panasonic ECJ-VBCK R, R2 0 ohm resistor, 002, % Panasonic ERJ-2GEJX L 0.33 µh inductor Toko America FSLU2-R33K L2 0 µh inductor Coilcraft DO608-MLB This application circuit is used on the it2j evaluation board, which is available to customers who desire a convenient test platform for this product. The it2j design was verified with the components and configuration described above. Note that VD2 is not used in this configuration. C and C2 are coupling capacitors for the RF input and output. Highperformance capacitors (such as those manufactured by Presidio) may be substituted. C3 to C8 are power supply decoupling capacitors. L, L2, R, and R2 are the required external components for the choke network that supplies the output stage bias current for applications down to 30 khz. These components can be replaced with different values if the low-frequency cutoff is higher than 30 khz. (*) For applications in which the minimum frequency is 2 GHz, L, L2, R, and R2 can be removed and only C8 is required. 6

7 30 khz to GHz High-Gain Power Amplifier Package Details Lid Notes:. Tolerances on package length and width are ± 0.00 in. 2. Tolerance on package height is ± in. 3. Tolerances on all pad dimensions and features are ± in it2j XXnnnn. Substrate material: RO003, in.- thick, ½ oz. copper Plating: 0 to 30 µin nickel, to µin. flash gold finish. Pin indicator Package footprint available in DXF format. Contact iterra Communications for details. 7. RoHS compliant. Backward compatible with SnPb soldering Pin typ

8 30 khz to GHz High-Gain Power Amplifier Pad Details Notes:. Pad widths and heights are in mils Pads 9 to 27 are ground pads. Although they are shown as independent structures, they should all be connected to one contiguous ground pad on the application board Package footprint available in DXF format. Contact iterra Communications for details. Pad 2 Function Width Height Pad Function Width Height 3 V G 2 V D2T 3 V D2 V CTRL2 6 V G2 V D V CTRL 9 V OUT 27 V IN Thermal Characteristics The thermal impedance between the package base (ground pad 9) and each amplifier junction (θjb) is approximately 2 C/W. Consider this thermal impedance as well as thermal conditions in the final application and the desired it2j bias settings to keep internal junction temperatures below their specified limits. The following formulas may be used to calculate the operating junction temperatures (TJ and TJ2) for each of the two cascaded amplifiers in the it2j. TJ = TBASE + ( VD x ID ) x 2 o C/W TJ2 = TBASE + ( VD2T x ID2T ) x 2 C/W or TJ2 = TBASE + ( VD2 x ID2 ) x 2 C/W 8