1.2 A, 20 V, 700 khz/1.4 MHz, Nonsynchronous Step-Down Regulator ADP2300/ADP2301

Transcription

1 . A, V, 7 khz/.4 MHz, Nonsynchronous Step-Down Regulator ADP3/ADP3 FEATURES. A maximum load current ±% output accuracy over temperature range Wide input voltage range: 3. V to V 7 khz (ADP3) or.4 MHz (ADP3) switching frequency options High efficiency up to 9 Current-mode control architecture Output voltage from.8 V to.85 Automatic PFM/PWM mode switching Precision enable pin with hysteresis Integrated high-side MOSFET Integrated bootstrap diode Internal compensation and soft start Minimum external components Undervoltage lockout (UVLO) Overcurrent protection (OCP) and thermal shutdown (TSD) ADIsimPower online design tool Available in ultrasmall, 6-lead TSOT package APPLICATIONS LDO replacement for digital load applications Intermediate power rail conversion Communications and networking Industrial and instrumentation Healthcare and medical Consumer GERAL DESCRIPTION The ADP3/ADP3 are compact, constant-frequency, current-mode, step-down dc-to-dc regulators with integrated power MOSFET. The ADP3/ADP3 devices run from input voltages of 3. V to V, making them suitable for a wide range of applications. A precise, low voltage internal reference makes these devices ideal for generating a regulated output voltage as low as.8 V, with ±% accuracy, for up to. A load current. There are two frequency options: the ADP3 runs at 7 khz, and the ADP3 runs at.4 MHz. These options allow users to make decisions based on the trade-off between efficiency and EFFICICY (%) TYPICAL APPLICATIONS CIRCUIT 3.V TO V ON OFF ADP3/ ADP3 GND Figure. V OUT 65 V IN = V V OUT = 5.V I OUT (A) Figure. Efficiency vs. Output Current f =.4MHz f = 7kHz total solution size. Current-mode control provides fast and stable line and load transient performance. The ADP3/ADP3 devices include internal soft start to prevent inrush current at power-up. Other key safety features include short-circuit protection, thermal shutdown (TSD), and input undervoltage lockout (UVLO). The precision enable pin threshold voltage allows the ADP3/ADP3 to be easily sequenced from other input/ output supplies. It can also be used as a programmable UVLO input by using a resistive divider. The ADP3/ADP3 are available in a 6-lead TSOT package and are rated for the C to +5 C junction temperature range Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTTS Features... Applications... Typical Applications Circuit... General Description... Revision History... Specifications... 3 Absolute Maximum Ratings... 4 Thermal Resistance... 4 ESD Caution... 4 Pin Configuration and Function Descriptions... 5 Typical Performance Characteristics... 6 Functional Block Diagram... 3 Theory of Operation... 4 Basic Operation... 4 PWM Mode... 4 Power Saving Mode... 4 Bootstrap Circuitry... 4 Precision Enable... 4 Integrated Soft Start... 4 Current Limit... 4 Short-Circuit Protection... 5 Undervoltage Lockout (UVLO)... 5 Thermal Shutdown... 5 Control Loop... 5 Applications Information... 6 Programming the Output Voltage... 6 Voltage Conversion Limitations... 6 Low Input Voltage Considerations... 7 Programming the Precision Enable... 7 Inductor... 8 Catch Diode... 9 Input Capacitor... 9 Output Capacitor... 9 Thermal Considerations... Design Example... Switching Frequency Selection... Catch Diode Selection... Inductor Selection... Output Capacitor Selection... Resistive Voltage Divider Selection... Circuit Board Layout Recommendations... 3 Typical Application Circuits... 4 Outline Dimensions... 6 Ordering Guide... 6 REVISION HISTORY 6/ Rev. to Rev. A Changes to Figure Changes to Ordering Guide... 6 / Revision : Initial Version Rev. A Page of 8

3 SPECIFICATIONS = 3.3 V, TJ = C to +5 C for minimum/maximum specifications, and TA = 5 C for typical specifications, unless otherwise noted. Table. Parameter Symbol Test Conditions Min Typ Max Unit Voltage Range 3 V Supply Current I No switching, = V 6 μa Shutdown Current ISHDN V = V, = V 8 35 μa Undervoltage Lockout Threshold UVLO rising..95 V falling.5. V Regulation Voltage V TJ = C to +5 C V TJ = C to +5 C V Bias Current I.. μa On Resistance V V = 5 V, I = 5 ma 4 7 mω Peak Current Limit V V = 5 V, = V A Minimum On Time 35 ns Minimum Off Time ADP ns ADP3 7 ns OSCILLATOR FREQUCY ADP MHz ADP MHz SOFT START TIME ADP3 46 μs ADP3 73 μs Input Threshold V.3..7 V Input Hysteresis mv Pull-Down Current. μa BOOTSTRAP VOLTAGE VBOOT No switching, = V 5. V THERMAL SHUTDOWN Threshold C Hysteresis 5 C Pin-to-pin measurements. Guaranteed by design. Rev. A Page 3 of 8

4 ABSOLUTE MAXIMUM RATINGS Table. Parameter, to Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Rating.3 V to +8 V. V to +8 V.6 V to +6 V.3 V to +8 V.3 V to +3.3 V C to +5 C 65 C to +5 C JEDEC J-STD- Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all voltages are referenced to GND. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type θja θjc Unit 6-Lead TSOT C/W θja and θjc are measured using natural convection on a JEDEC 4-layer board. ESD CAUTION Rev. A Page 4 of 8

5 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 3 ADP3/ ADP3 TOP VIEW (Not to Scale) Figure 3. Pin Configuration 834- Table 4. Pin Function Descriptions Pin No. Mnemonic Description Boost Supply for the High-Side MOSFET Driver. A. μf capacitor is connected between the and pins to form a floating supply to drive the gate of the MOSFET switch above the supply voltage. GND Ground. Connect this pin to the ground plane. 3 Feedback Voltage Sense Input. Connect this pin to a resistive divider from VOUT. Set the voltage to.8 V for a desired VOUT. 4 Output Enable. Pull this pin high to enable the output. Pull this pin low to disable the output. This pin can also be used as a programmable UVLO input. This pin has a. μa pull-down current to GND. 5 Power Input. Connect to the input power source with a ceramic bypass capacitor to GND directly from this pin. 6 Switch Node Output. Connect an inductor to VOUT and a catch diode to GND from this pin. Rev. A Page 5 of 8

6 TYPICAL PERFORMANCE CHARACTERISTICS = 3.3 V, TA = 5 C, V =, unless otherwise noted. 9 9 INDUCTOR: LPS65-3MLC DIODE: B3A EFFICICY (%) 7 6 EFFICICY (%) V OUT = V V OUT = 9V INDUCTOR: LPS65-47MLC V OUT = 5.V DIODE: B3A V OUT = 3.3V I OUT (A) V OUT = 5.V 5 V OUT = 3.3V V OUT =.5V V OUT =.8V V OUT =.V I OUT (A) Figure 4. Efficiency Curve, = 8 V, f =.4 MHz Figure 7. Efficiency Curve, = V, f = 7 khz 9 9 INDUCTOR: LPS65-47MLC DIODE: B3A EFFICICY (%) 7 6 EFFICICY (%) V OUT = V V OUT = 9V INDUCTOR: LPS65-3MLC V OUT = 5.V DIODE: B3A V OUT = 3.3V I OUT (A) V OUT =.5V V OUT =.8V V OUT =.V I OUT (A) Figure 5. Efficiency Curve, = 8 V, f = 7 khz Figure 8. Efficiency Curve, = 5. V, f =.4 MHz 9 9 INDUCTOR: LPS65-3MLC DIODE: B3A EFFICICY (%) 7 6 EFFICICY (%) V OUT = 5.V INDUCTOR: LPS65-47MLC V OUT = 3.3V DIODE: B3A V OUT =.5V I OUT (A) Figure 6. Efficiency Curve, = V, f =.4 MHz V OUT =.5V V OUT =.8V V OUT =.V I OUT (A) Figure 9. Efficiency Curve, = 5. V, f = 7 khz Rev. A Page 6 of 8

7 EFFICICY (%) LINE REGULATION (%) f =.4MHz f = 7kHz 5 V OUT =.8V INDUCTOR: LPS65-47MLC V OUT =.V DIODE: B3A V OUT =.8V I OUT (A) Figure. Efficiency Curve, = 3.3 V with External 5. V Bootstrap Bias Voltage, f =.4 MHz V IN (V) Figure 3. Line Regulation, VOUT = 3.3 V, IOUT = 5 ma V OUT =.8V V OUT =.V V OUT =.8V 6 f =.4MHz f = 7kHz EFFICICY (%) 7 6 FREQUCY (khz) 5 INDUCTOR: LPS65-3MLC DIODE: B3A I OUT (A) Figure. Efficiency Curve, = 3.3 V with External 5. V Bootstrap Bias Voltage, f = 7 khz TEMPERATURE ( C) Figure 4. Frequency vs. Temperature F =.4MHz F = 7kHz 6 f =.4MHz f = 7kHz LOAD REGULATION (%) FREQUCY (khz) I OUT (A) Figure. Load Regulation, VOUT = 3.3 V, = V V IN (V) Figure 5. Frequency vs Rev. A Page 7 of 8

8 35 6 f =.4MHz f = 7kHz SHUTDOWN CURRT (µa) T J = C T J = +5 C T J = +5 C V IN (V) Figure 6. Shutdown Current vs MINIMUM OFF TIME (ns) TEMPERATURE ( C) Figure 9. Minimum Off Time vs. Temperature V FEEDBACK VOLTAGE (V) CURRT LIMIT (A) TEMPERATURE ( C) Figure 7..8 V Feedback Voltage vs. Temperature V IN (V) Figure. Current-Limit Threshold vs., V V = 5. V MINIMUM ON TIME (ns) 95 9 CURRT LIMIT (A) TEMPERATURE ( C) Figure 8. Minimum On Time vs. Temperature TEMPERATURE ( C) Figure. Current-Limit Threshold vs. Temperature Rev. A Page 8 of 8

9 RISING FALLING QUIESCT CURRT (µa) T J = C T J = +5 C T J = +5 C V IN (V) Figure. Quiescent Current vs UVLO THRESHOLD (V) TEMPERATURE ( C) Figure 5. UVLO Threshold vs. Temperature V OUT MOSFET R DS (ON) (mω) IL V GS = 5V V GS = 4V V GS = 3V TEMPERATURE ( C) Figure 3. MOSFET RDS(ON) vs. Temperature (Pin-to-Pin Measurements) CH 5mV B CH 5V B W W Mns A CH 7.4V CH4 5mA Ω B W Figure 6. Steady State at Heavy Load, f =.4 MHz, IOUT = A RISING FALLING.5 V OUT ABLE THRESHOLD (V) IL TEMPERATURE ( C) Figure 4. Enable Threshold vs. Temperature CH mv B W CH 5V B W Mµs A CH 8V CH4 ma Ω B W Figure 7. Steady State at Light Load, f =.4 MHz, IOUT = ma Rev. A Page 9 of 8

10 V OUT IL V OUT I OUT CH V B CH V B W W Mµs A CH3 8V CH3 V B W CH4 5mA Ω B W Figure 8. Soft Start with A Resistance Load, f =.4 MHz CH 5mV B CH V B W W Mµs A CH4 63mA CH4 5mA Ω B W Figure 3. ADP3 Load Transient,. A to. A, VOUT = 3.3 V, = V (f =.4 MHz, L = 4.7 μh, COUT = μf) V OUT V OUT IL I OUT CH V B CH V B W W Mµs A CH3 8V CH3 V B W CH4 5mA Ω B W Figure 9. Soft Start with No Load, f =.4 MHz CH mv B CH V B W W Mµs A CH4 63mA CH4 5mA Ω B W Figure 3. ADP3 Load Transient,. A to. A, VOUT = 5. V, = V (f = 7 khz, L = μh, COUT = μf) V OUT V OUT I OUT I OUT 4 4 CH mv B W CH V B W Mµs A CH4 5mA CH4 5mA Ω B W Figure 3. ADP3 Load Transient,. A to. A, VOUT = 5. V, = V (f =.4 MHz, L = 4.7 μh, COUT = μf) CH mv B CH V B W W Mµs A CH4 63mA CH4 5mA Ω B W Figure 33. ADP3 Load Transient,. A to. A, VOUT = 3.3 V, = V (f = 7 khz, L = μh, COUT = μf) Rev. A Page of 8

11 V OUT CH 5mV CH3 5V B W V IN CH V B W Mms A CH3.4V Figure 34. ADP3 Line Transient, 7 V to 5 V, VOUT = 3.3 V, IOUT =. A, f =.4 MHz MAGNITUDE [B/A] (db) 6 CROSS FREQUCY: 7kHz PHASE MARGIN: 53 k k k M FREQUCY (Hz) Figure 37. ADP3 Bode Plot, VOUT = 5. V, = V (f =.4 MHz, L = 4.7 μh, COUT = μf) 6 PHASE [B/A] (Degrees) V OUT IL MAGNITUDE [B/A] (db) 6 PHASE [B/A] (Degrees) CH V B W CH V B W Mµs A CH.56V CH4 A Ω B W Figure 35. ADP3 Short-Circuit Entry, VOUT = 3.3 V (f =.4 MHz) CROSS FREQUCY: khz PHASE MARGIN: 68 k k k FREQUCY (Hz) M Figure 38. ADP3 Bode Plot, VOUT = 3.3 V, = V (f =.4 MHz, L = 4.7 μh, COUT = μf) V OUT IL MAGNITUDE [B/A] (db) 6 PHASE [B/A] (Degrees) CH V B W CH V B W Mµs A CH.V CH4 A Ω B W Figure 36. ADP3 Short-Circuit Recovery, VOUT = 3.3 V (f =.4 MHz) CROSS FREQUCY: 7kHz PHASE MARGIN: 76 k k k M FREQUCY (Hz) Figure 39. ADP3 Bode Plot, VOUT = 5. V, = V (f = 7 khz, L = μh, COUT = μf) Rev. A Page of 8

12 MAGNITUDE [B/A] (db) PHASE [B/A] (Degrees) CROSS FREQUCY: 47kHz PHASE MARGIN: 77 k k k FREQUCY (Hz) M Figure. ADP3 Bode Plot, VOUT = 3.3 V, = V (f = 7 khz, L = μh, COUT = μf) Rev. A Page of 8

13 FUNCTIONAL BLOCK DIAGRAM V IN 5 THERMAL SHUTDOWN.V SHUTDOWN LOGIC UVLO SHUTDOWN IC ON OFF 4.9V.µA OVP.5V OCP 5mV/A BOOT REGULATOR R Q V BIAS =.V S 6 V OUT.8V RAMP GERATOR CLK GERATOR 3 kω.7pf V FREQUCY FOLDBACK (f, ½ f, ¼ f ) GND 9pF ADP3/ADP Figure 4. ADP3/ADP3 Functional Block Diagram Rev. A Page 3 of 8

14 THEORY OF OPERATION The ADP3/ADP3 are nonsynchronous, step-down dc-to-dc regulators, each with an integrated high-side power MOSFET. A high switching frequency and ultrasmall, 6-lead TSOT package allow small step-down dc-to-dc regulator solutions. The ADP3/ADP3 can operate with an input voltage from 3. V to V while regulating an output voltage down to.8 V. The ADP3/ADP3 are available in two fixed-frequency options: 7 khz (ADP3) and.4 MHz (ADP3). BASIC OPERATION The ADP3/ADP3 use the fixed-frequency, peak currentmode PWM control architecture at medium to high loads, but shift to a pulse-skip mode control scheme at light loads to reduce the switching power losses and improve efficiency. When the devices operate in fixed-frequency PWM mode, output regulation is achieved by controlling the duty cycle of the integrated MOSFET. When the devices operate in pulse-skip mode at light loads, the output voltage is controlled in a hysteretic manner with higher output ripple. In this mode of operation, the regulator periodically stops switching for a few cycles, thus keeping the conversion losses minimal to improve efficiency. PWM MODE In PWM mode, the ADP3/ADP3 operate at a fixed frequency, set by an internal oscillator. At the start of each oscillator cycle, the MOSFET switch is turned on, sending a positive voltage across the inductor. The inductor current increases until the current-sense signal crosses the peak inductor current threshold that turns off the MOSFET switch; this threshold is set by the error amplifier output. During the MOSFET off time, the inductor current declines through the external diode until the next oscillator clock pulse starts a new cycle. The ADP3/ADP3 regulate the output voltage by adjusting the peak inductor current threshold. POWER SAG MODE To achieve higher efficiency, the ADP3/ADP3 smoothly transition to the pulse-skip mode when the output load decreases below the pulse-skip current threshold. When the output voltage dips below regulation, the ADP3/ADP3 enter PWM mode for a few oscillator cycles until the voltage increases to within regulation. During the idle time between bursts, the MOSFET switch is turned off, and the output capacitor supplies all the output current. Since the pulse-skip mode comparator monitors the internal compensation node, which represents the peak inductor current information, the average pulse-skip load current threshold depends on the input voltage (), the output voltage (VOUT), the inductor, and the output capacitor. Because the output voltage occasionally dips below regulation and then recovers, the output voltage ripple in the power saving mode is larger than the ripple in the PWM mode of operation. BOOTSTRAP CIRCUITRY The ADP3/ADP3 each have an integrated boot regulator, which requires that a. μf ceramic capacitor (X5R or X7R) be placed between the and pins to provide the gate drive voltage for the high-side MOSFET. There must be at least a. V difference between the and pins to turn on the high-side MOSFET. This voltage should not exceed 5.5 V in case the pin is supplied with an external voltage source through a diode. The ADP3/ADP3 generate a typical 5. V bootstrap voltage for a gate drive circuit by differentially sensing and regulating the voltage between the and pins. A diode integrated on the chip blocks the reverse voltage between the and pins when the MOSFET switch is turned on. PRECISION ABLE The ADP3/ADP3 feature a precision enable circuit that has a. V reference voltage with mv hysteresis. When the voltage at the pin is greater than. V, the part is enabled. If the voltage falls below. V, the chip is disabled. The precision enable threshold voltage allows the ADP3/ADP3 to be easily sequenced from other input/output supplies. It can also be used as programmable UVLO input by using a resistive divider. An internal. μa pull-down current prevents errors if the pin is floating. INTEGRATED SOFT START The ADP3/ADP3 include internal soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. The soft start time is typically fixed at 46 μs for the ADP3 and at 73 μs for the ADP3. CURRT LIMIT The ADP3/ADP3 include current-limit protection circuitry to limit the amount of positive current flowing through the highside MOSFET switch. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. Rev. A Page 4 of 8

15 SHORT-CIRCUIT PROTECTION The ADP3/ADP3 include frequency foldback to prevent output current runaway when there is a hard short on the output. The switching frequency is reduced when the voltage at the pin drops below a certain value, which allows more time for the inductor current to decline, but increases the ripple current while regulating the peak current. This results in a reduction in average output current and prevents output current runaway. The correlation between the switching frequency and the pin voltage is shown in Table 5. Table 5. Correlation Between the Switching Frequency and the Pin Voltage Pin Voltage Switching Frequency V.6 V f.6 V > V >. V ½ f V. V ¼ f When a hard short (V. V) is removed, a soft start cycle is initiated to regulate the output back to its level during normal operation, which helps to limit the inrush current and prevent possible overshoot on the output voltage. UNDERVOLTAGE LOCKOUT (UVLO) The ADP3/ADP3 have fixed, internally set undervoltage lockout circuitry. If the input voltage drops below.4 V, the ADP3/ADP3 shut down and the MOSFET switch turns off. After the voltage rises again above.8 V, the soft start period is initiated, and the part is enabled. THERMAL SHUTDOWN If the ADP3/ADP3 junction temperature rises above C, the thermal shutdown circuit disables the chip. Extreme junction temperature can be the result of high current operation, poor circuit board design, or high ambient temperature. A 5 C hysteresis is included so that when thermal shutdown occurs, the ADP3/ADP3 do not return to operation until the onchip temperature drops below 5 C. After the devices recover from thermal shutdown, a soft start is initiated. CONTROL LOOP The ADP3/ADP3 are internally compensated to minimize external component count and cost. In addition, the built-in slope compensation helps to prevent subharmonic oscillations when the ADP3/ADP3 operate at a duty cycle greater than or close to 5%. Rev. A Page 5 of 8

16 APPLICATIONS INFORMATION PROGRAMMING THE OUTPUT VOLTAGE The output voltage of the ADP3/ADP3 is externally set by a resistive voltage divider from the output voltage to the pin, as shown in Figure 4. Suggested resistor values for the typical output voltage setting are listed in Table 6. The equation for the output voltage setting is V where: R. V + R = OUT VOUT is the output voltage. R is the feedback resistor from VOUT to. R is the feedback resistor from to GND. ADP3/ ADP3 R R V OUT Figure 4. Programming the Output Voltage Using a Resistive Voltage Divider Table 6. Suggested Values for Resistive Voltage Divider VOUT (V) R (kω), ± R (kω), ± VOLTAGE CONVERSION LIMITATIONS There are both lower and upper output voltage limitations for a given input voltage due to the minimum on time, the minimum off time, and the bootstrap dropout voltage. The lower limit of the output voltage is constrained by the finite, controllable minimum on time, which can be as high as 35 ns for the worst case. By considering the variation of both the switching frequency and the input voltage, the equation for the lower limit of the output voltage is V OUT(min) = t f + V ) V MIN-ON (max) ( (max) where: (max) is the maximum input voltage. f(max) is the maximum switching frequency for the worst case. tmin-on is the minimum controllable on time. VD is the diode forward drop. The upper limit of the output voltage is constrained by the minimum controllable off time, which can be as high as ns in the ADP3 for the worst case. By considering the variation of both the switching frequency and the input voltage, the equation for the upper limit of the output voltage is V OUT(max) = + V ) V ( t MIN-OFF f (max) ) ( (min) where: (min) is the minimum input voltage. f(max) is the maximum switching frequency for the worst case. VD is the diode forward drop. tmin-off is the minimum controllable off time. In addition, the bootstrap circuit limits the minimum input voltage for the desired output due to internal dropout voltage. To attain stable operation at light loads and ensure proper startup for the prebias condition, the ADP3/ADP3 require the voltage difference between the input voltage and the regulated output voltage (or between the input voltage and the prebias voltage) to be greater than. V for the worst case. If the voltage difference is smaller, the bootstrap circuit relies on some minimum load current to charge the boost capacitor for startup. Figure 43 shows the typical required minimum input voltage vs. load current for the 3.3 V output voltage. D D D D Rev. A Page 6 of 8

17 MINIMUM V IN (V) FOR STARTUP FOR RUNNING 3.7 V OUT = 3.3V f =.4MHz 3.5 k LOAD CURRT (ma) Figure 43. Minimum Input Voltage vs. Load Current Based on three conversion limitations (the minimum on time, the minimum off time, and the bootstrap dropout voltage), Figure 44 shows the voltage conversion limitations. PROGRAMMING THE PRECISION ABLE Generally, the pin can be easily tied to the pin so that the device automatically starts up when the input power is applied. However, the precision enable feature allows the ADP3/ ADP3 to be used as a programmable UVLO by connecting a resistive voltage divider to, as shown in Figure 46. This configuration prevents the start-up problems that can occur when ramps up slowly in soft start with a relatively high load current. V IN R R ADP3/ ADP3 Figure 46. Precision Enable Used as a Programmable UVLO The precision enable feature also allows the ADP3/ADP3 to be sequenced precisely by using a resistive voltage divider with another dc-to-dc output supply, as shown in Figure V IN (V) 7 MAXIMUM INPUT FOR ADP3 MAXIMUM INPUT FOR ADP3 MINIMUM INPUT FOR ADP3/ADP V OUT (V) Figure 44. Voltage Conversion Limitations LOW INPUT VOLTAGE CONSIDERATIONS For low input voltage between 3 V and 5 V, the internal boot regulator cannot provide enough 5. V bootstrap voltage due to the internal dropout voltage. As a result, the increased MOSFET RDS(ON) reduces the available load current. To prevent this, add an external small-signal Schottky diode from a 5. V external bootstrap bias voltage. Because the absolute maximum rating between the and pins is 6. V, the bias voltage should be less than 5.5 V. Figure 45 shows the application diagram for the external bootstrap circuit. 3V ~ 5V ADP3/ ADP3 SCHOTTKY DIODE 5V BIAS VOLTAGE OTHER DC-TO-DC OUTPUT R R ADP3/ ADP3 Figure 47. Precision Enable Used as a Sequencing Control from Another DC-to-DC Output With a. μa pull-down current on the pin, the equation for the start-up voltage in Figure 46 and Figure 47 is V. V. μa + R R STARTUP = +. V where: VSTARTUP is the start-up voltage to enable the chip. R is the resistor from the dc source to. R is the resistor from to GND ON GND OFF Figure 45. External Bootstrap Circuit for Low Input Voltage Application Rev. A Page 7 of 8

18 INDUCTOR The high switching frequency of the ADP3/ADP3 allows the use of small inductors. For best performance, use inductor values between μh and μh for ADP3, and use inductor values between μh and μh for ADP3. The peak-to-peak inductor current ripple is calculated using the following equation: ΔI RIPPLE ( V = IN V L f OUT sw ) V V OUT IN + V + V where: f is the switching frequency. L is the inductor value. VD is the diode forward drop. is the input voltage. VOUT is the output voltage. Inductors of smaller values are usually smaller in size and less expensive, but increase the ripple current and the output voltage ripple. As a guideline, the inductor peak-to-peak current ripple should typically be set to 3% of the maximum load current for optimal transient response and efficiency. Therefore, the inductor value is calculated using the following equation: ( V V ) IN OUT VOUT + VD L =.3 I LOAD(max) f sw + VD where ILOAD(max) is the maximum load current. D D The inductor peak current is calculated using the following equation: ΔI RIPPLE I PEAK = I LOAD(max) + The minimum current rating of the inductor must be greater than the inductor peak current. For ferrite core inductors with a quick saturation characteristic, the inductor saturation current rating should be higher than the switch current-limit threshold to prevent the inductor from reaching its saturation point. Be sure to validate the worst-case condition, in which there is a shorted output, over the intended temperature range. Inductor conduction losses are caused by the flow of current through the inductor, which is associated with the internal dc resistance (DCR). Larger sized inductors have smaller DCR and, therefore, may reduce inductor conduction losses. However, inductor core losses are also related to the core material and the ac flux swing, which are affected by the peak-to-peak inductor ripple current. Because the ADP3/ADP3 are high switching frequency regulators, shielded ferrite core materials are recommended for their low core losses and low EMI. Some recommended inductors are shown in Table 7. Table 7. Recommended Inductors Vendor Value (μh) Part No. DCR (mω) ISAT (A) Dimensions L W H (mm) Coilcraft 4.7 LPS65-47MLC LPS65-68MLC LPS65-3MLC Sumida 4.7 CDRH5D8RHPNP-4R7N CDRH5D6NP-4R7N CDRH5D8RHPNP-6R8N CDRH5D6NP-6R8N CDRH5D8RHPNP-M Cooper Bussmann 4.7 SD53-4R7-R SD53-6R8-R DR73--R Toko 4.7 B77AS-4R7N B77AS-6R8N B77AS-M TDK 4.7 VLC545T-4R7M VLC545T-6R8M VLC545T-M Rev. A Page 8 of 8

19 CATCH DIODE The catch diode conducts the inductor current during the off time of the internal MOSFET. The average current of the diode in normal operation is, therefore, dependent on the duty cycle of the regulator as well as the output load current. V + V I OUT D DIODE( AVG) = I LOAD(max) + VD where VD is the diode forward drop. The only reason to select a diode with a higher current rating than necessary in normal operation is for the worst-case condition, in which there is a shorted output. In this case, the diode current increases up to the typical peak current-limit threshold. Be sure to consult the diode data sheet to ensure that the diode can operate well within the thermal and electrical limits. The reverse breakdown voltage rating of the diode must be higher than the highest input voltage and allow an appropriate margin for the ringing that may be present on the node. A Schottky diode is recommended for best efficiency because it has a low forward voltage drop and fast switching speed. Table 8 provides a list of recommended Schottky diodes. Table 8. Recommended Schottky Diodes Vendor Part No. VRRM (V) ON Semiconductor MBRS3LT3 3 MBRSLT3 Diodes Inc. B3A 3 BA Vishay SL3 3 SS4 IAVG (A) INPUT CAPACITOR The input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. The maximum rms input current flowing through the input capacitor is ILOAD(max)/. Select an input capacitor capable of withstanding the rms input current for an application s maximum load current using the following equation: OUTPUT CAPACITOR The output capacitor selection affects both the output voltage ripple and the loop dynamics of the regulator. The ADP3/ADP3 are designed to operate with small ceramic capacitors that have low equivalent series resistance (ESR) and equivalent series inductance (ESL) and are, therefore, easily able to meet stringent output voltage ripple specifications. When the regulator operates in forced continuous conduction mode, the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor. ΔV RIPPLE = ΔI RIPPLE 8 f sw C OUT + ESR C OUT Capacitors with lower ESR are preferable to guarantee low output voltage ripple, as shown in the following equation: ESR COUT ΔV ΔI RIPPLE RIPPLE Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. X5R or X7R dielectrics are recommended for best performance, due to their low ESR and small temperature coefficients. Y5V and Z5U dielectrics are not recommended because of their poor temperature and dc bias characteristics. In general, most applications using the ADP3 (.4 MHz switching frequency) require a minimum output capacitor value of μf, whereas most applications using the ADP3 (7 khz switching frequency) require a minimum output capacitor value of μf. Some recommended output capacitors for VOUT 5. V are listed in Table 9. Table 9. Recommended Capacitors for VOUT 5. V Dimensions Vendor Value Part No. L W H (mm) Murata μf, 6.3 V GRM3MR6J6KE μf, 6.3 V GRM3CR6J6KE TDK μf, 6.3 V C36X5RJ6K μf, 6.3 V C36X5RJ6M I IN ( RMS) = I LOAD(max) D ( D) where D is the duty cycle and is equal to VOUT + VD D = V + V IN D The recommended input capacitor is ceramic with X5R or X7R dielectrics due to its low ESR and small temperature coefficients. A capacitance of μf should be adequate for most applications. To minimize supply noise, place the input capacitor as close to the pin of the ADP3/ADP3 as possible. Rev. A Page 9 of 8

20 THERMAL CONSIDERATIONS The ADP3/ADP3 store the value of the inductor current only during the on time of the internal MOSFET. Therefore, a small amount of power is dissipated inside the ADP3/ADP3 package, which reduces thermal constraints. However, when the application is operating under maximum load with high ambient temperature and high duty cycle, the heat dissipated within the package may cause the junction temperature of the die to exceed the maximum junction temperature of 5 C. If the junction temperature exceeds C, the regulator goes into thermal shutdown and recovers when the junction temperature drops below 5 C. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, as indicated in the following equation: The rise in temperature of the package is directly proportional to the power dissipation in the package. The proportionality constant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: TR = θja PD where: TR is the rise in temperature of the package. θja is the thermal resistance from the junction of the die to the ambient temperature of the package. PD is the power dissipation in the package. TJ = TA + TR where: TJ is the junction temperature. TA is the ambient temperature. TR is the rise in temperature of the package due to power dissipation. Rev. A Page of 8

21 DESIGN EXAMPLE This section provides the procedures to select the external components, based on the example specifications listed in Table. The schematic for this design example is shown in Figure 48. Table. Step-Down DC-to-DC Regulator Requirements Additional Parameter Specification Requirements Input Voltage,. V ± % None Output Voltage, VOUT 3.3 V,. A, VOUT None ripple at CCM mode Programmable UVLO Voltage start-up voltage approximately 7.8 V None ITCHING FREQUCY SELECTION Select the switching frequency 7 khz (ADP3) or.4 MHz (ADP3) using the conversion limitation curve shown in Figure 44 to assess the conversion limitations (the minimum on time, the minimum off time, and the bootstrap dropout voltage). For example, in Figure 44 = V ± % is within the conversion limitation for both the 7 khz and.4 MHz switching frequencies for an output voltage of 3.3 V, but choosing the.4 MHz switching frequency provides the smallest sized solution. If higher efficiency is required, choose the 7 khz option; however, the PCB footprint area of the regulator will be larger because of the bigger inductor and output capacitors. CATCH DIODE SELECTION Select the catch diode. A Schottky diode is recommended for best efficiency because it has a low forward voltage drop and faster switching speed. The average current of the catch diode in normal operation, with a typical Schottky diode forward voltage, can be calculated using the following equation: I V + + OUT V DIODE( AVG) = D I LOAD(max) VD where: VOUT = 3.3 V. = V. ILOAD(max) =. A. VD =.4 V. Therefore, IDIODE(AVG) =.85 A. However, for the worst-case condition, in which there is a shorted output, the diode current would be increased to A typical, determined by the peak switch current limit (see Table ). In this case, selecting a B3A,. A/3 V surface-mount Schottky diode would result in more reliable operation. INDUCTOR SELECTION Select the inductor by using the following equation: L =.3 I ( V V ) IN OUT LOAD(max) f sw V V OUT IN + V + V where: VOUT = 3.3 V. = V. ILOAD(max) =. A. VD =.4 V. f =.4 MHz. This results in L = 5.5 μh. The closest standard value is 4.7 μh; therefore, ΔIRIPPLE =.394 A. The inductor peak current is calculated using the following equation: ΔI RIPPLE I PEAK = I LOAD(max) + where: ILOAD(max) =. A. ΔIRIPPLE =.394 A. Therefore, the calculated peak current for the inductor is.397 A. However, to protect the inductor from reaching its saturation point in the current-limit condition, the inductor should be rated for at least a. A saturation current for reliable operation. OUTPUT CAPACITOR SELECTION Select the output capacitor based on the output voltage ripple requirement, according to the following equation: ΔV RIPPLE = ΔI RIPPLE 8 f sw C OUT D D + ESR where: ΔIRIPPLE =.394 A. f =.4 MHz. ΔVRIPPLE = 33 mv. If the ESR of the ceramic capacitor is 3 mω, then COUT =. μf. Because the output capacitor is one of the two external components that control the loop stability, most applications using the ADP3 (.4 MHz switching frequency) require a minimum μf capacitance to ensure stability. According to the recommended external components in Table, choose μf with a 6.3 V voltage rating for this example. C OUT Rev. A Page of 8

22 RESISTIVE VOLTAGE DIVIDER SELECTION To select the appropriate resistive voltage divider, first calculate the output feedback resistive voltage divider, and then calculate the resistive voltage divider for the programmable start-up voltage. The output feedback resistive voltage divider is V R. V + R = OUT The resistive voltage divider for the programmable start-up voltage is V. V. μa + R R STARTUP = +. V If VSTARTUP = 7.8 V, choose R =. kω, and then calculate R, which in this case is 56 kω. For the 3.3 V output voltage, choose R = 3.6 kω and R =. kω as the feedback resistive voltage divider, according to the recommended values in Table. V IN = V C µf 5V R3 56kΩ R4.kΩ ADP3 (.4MHz) GND C3.µF D B3A L 4.7µH.A Figure 48. Schematic for the Design Example R 3.6kΩ R.kΩ V OUT = 3.3V.A C µf Table. Recommended External Components for Typical Applications at. A Output Load Part Number (V) VOUT (V) IOUT (A) L (μh) COUT (μf) R (kω), ± R (kω), ± ADP3 (7 khz) ADP3 (.4 MHz) Rev. A Page of 8

23 CIRCUIT BOARD LAYOUT RECOMMDATIONS Good circuit board layout is essential to obtain the best performance from the ADP3/ADP3. Poor layout can affect the regulation and stability, as well as the electromagnetic interface (EMI) and electromagnetic compatibility (EMC) performance. A PCB layout example is shown in Figure 5. Refer to the following guidelines for a good PCB layout: Place the input capacitor, inductor, catch diode, output capacitor, and bootstrap capacitor close to the IC using short traces. Ensure that the high current loop traces are as short and wide as possible. The high current path is shown in Figure 49. Maximize the size of ground metal on the component side to improve thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. Minimize the length of the trace connecting the top of the feedback resistive voltage divider to the output. In addition, keep these traces away from the high current traces and the switch node to avoid noise pickup. ADP3/ ADP3 GND Figure 49. Typical Application Circuit with High Current Traces Shown in Blue INDUC TOR L C3 OUTPUT CAP R CAP C CATCH DIODE D C R ADP3/ADP3 INPUT CAP Figure 5. Recommended PCB Layout for the ADP3/ADP Rev. A Page 3 of 8

24 TYPICAL APPLICATION CIRCUITS V IN = V C µf 5V R3 kω 5% ON OFF ADP3 (7kHz) GND C4.µF L 6.8µH.A D B3A R 4.99kΩ R kω V OUT =.V.A C µf C3 µf Figure 5. ADP3 7 khz Typical Application, = V, VOUT =. V/. A with External Enabling C µf 5V V IN = V R3 kω 5% ON OFF ADP3 (7kHz) GND C4.µF D B3A L 6.8µH.A R.7kΩ R.kΩ V OUT =.8V.A C µf C3 µf Figure 5. ADP3 7 khz Typical Application, = V, VOUT =.8 V/. A with External Enabling V IN = V C µf 5V R3 kω 5% ON OFF ADP3 (7kHz) GND C3.µF D B3A L µh.a R.5kΩ R.kΩ V OUT =.5V.A C µf Figure 53. ADP3 7 khz Typical Application, = V, VOUT =.5 V/. A with External Enabling Rev. A Page 4 of 8

25 V IN = V C µf 5V R3 56kΩ R4.kΩ ADP3 (.4MHz) GND C3.µF L 4.7µH.A D B3A R 3.6kΩ R.kΩ V OUT = 3.3V.A Figure 54. ADP3.4 MHz Typical Application, = V, VOUT = 3.3 V/. A (with Programmable 7.8 V Start-Up Input Voltage) C µf V IN = V C µf 5V R3 kω 5% ON OFF ADP3 (.4MHz) GND C3.µF D B3A L 4.7µH.A R 5.3kΩ R kω V OUT = 5V.A C µf Figure 55. ADP3.4 MHz Typical Application, = V, VOUT = 5. V/. A with External Enabling V IN = 8V C µf 5V R3 kω 5% ON OFF ADP3 (.4MHz) GND C3.µF D B3A L 6.8µH.A R 5.3kΩ R.kΩ V OUT = 5.V.A C µf Figure 56. ADP3.4 MHz Typical Application, = 8 V, VOUT = 5. V/. A with External Enabling V IN = 9V C µf 5V R3 kω 5% ON OFF ADP3 (.4MHz) GND C3.µF D B3A L 4.7µH.A R 3.6kΩ R.kΩ V OUT = 3.3V.A C µf Figure 57. ADP3.4 MHz Typical Application, = 9 V, VOUT = 3.3 V/. A with External Enabling V IN = 5V C µf 5V R3 kω 5% ON OFF ADP3 (.4MHz) GND C4.µF D B3A Rev. A Page 5 of 8 L.µH.A R.7kΩ R.kΩ V OUT =.8V.A C µf C3 µf Figure 58. ADP3.4 MHz Typical Application, = 5 V, VOUT =.8 V/. A with External Enabling 834-9

26 OUTLINE DIMSIONS.9 BSC.6 BSC BSC 3 PIN INDICATOR.95 BSC.9 BSC * *. MAX..8. MAX.5.3 SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-93-AA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure Lead Thin Small Outline Transistor Package [TSOT] (UJ-6) Dimensions shown in millimeters 8-A ORDERING GUIDE Model Switching Frequency Temperature Range Package Description Package Option Branding ADP3AUJZ-R7 7 khz C to +5 C 6-Lead Thin Small Outline Transistor Package [TSOT] UJ-6 L87 ADP3-EVALZ Evaluation Board ADP3AUJZ-R7.4 MHz C to +5 C 6-Lead Thin Small Outline Transistor Package [TSOT] UJ-6 L86 ADP3-EVALZ Evaluation Board Z = RoHS Compliant Part. Rev. A Page 6 of 8

27 NOTES Rev. A Page 7 of 8

28 NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D834--6/(A) Rev. A Page 8 of 8