DC-DC Converter Design for Battery-Operated Systems

Transcription

1 DC-DC Converter Design for Battery-Operated Systems Harry Arbetter. Robert Erickson. and Dragan Maksimovid Power Electronics Group Department of Electrical and Computer Engineering University of Colorado, Boulder, CO USA Abstrurt - This paper describes performance, design and optimization of de-dc converters for energy limited, battery operated systems. Variable-frequency operation is used to achieve voltage regulation and high efficiency for an extremely wide range of load currents. An experimental 15W, 3.3V buck converter has been constructed to demonstrate design and optimization techniques. The converter employs synchronous rectification to reduce conduction losses, and discontinuous, variable-frequency, current-mode control with optimum peak current to maximize efficiency for a wide range of loads. Applications include portable computers, hand-held instruments, and telecommunications. 1. NTRODUCTON Energy limited, battery powered systems require the utmost in efficiency in order to provide full system capability and maximum battery life. The use of low voltage power supplies (3.3 volts or less) can reduce power consumption at the expense of lower noise margins and a requirement for better voltage regulation. Elements which require high instantaneous power. such as transmitters. microprocessors, backlit displays, and flash memory, can be switched to a low power standby mode when not needed. Applications include portable computers, hand-held instruments. and wireless telecommunications. To fully realize such systems, dc-dc converters are needed which can: (a) regulate the load voltage with (ideally) zero load current; (b) operate at high efficiency with many orders of magnitude variation in the load current; (c) operate efficiently at low output voltages (3.3 volts or less). Losses in a switch-mode converter can be classified as: - loud dependent conduction losses (due to transistor onresistance, diode forward voltage drop, inductor winding resistance, capacitor equivalent series resistance); - freyuencj, dependent switchrng losses (due to transistor and diode output capacitance charge and discharge, gatedrive losses, voltage/current overlap at switching transitions, inductor core losses, and controller frequencydependent power consumption); - $xed losses (due to controller standby current, and leakage currents of transistors, diodes, etc.). The loss budget for a conventional fixed-frequency dc-dc converter is shown in Fig. 1 t is clear that the converter cannot meet the requirements in battery-operated systems be- cause the switching losses do not scale with load, and the light-load efficiency is poor. Also, it is difficult to maintain output voltage regulation when the converter-is unloaded. An approach to the above problems is to allow variable frequency operation, at least at light loads. This approach has been shown to yield significantly improved efficiency in a wide load range, and is currently supported by dedicated controllers [1,2]. Fig. shows how the variable-frequency approach offers reduced losses at light loads by reducing both conduction and switching losses in proportion to the load. The performance at zero load is ultimately limited by fixed losses. The purpose of this paper is to describe analysis, design, and optimization of a variable frequency converter for battery powered applications, and to suggest techniques to further improve efficiency and noise performance. The paper describes a variable-frequency, current-controlled buck converter which utilizes synchronous rectification and is operating the discontinuous mode at light loads. The input voltage range is 4 to 15 volts and the output voltage is 3.3 volts. Fixed Frequency Converter Load Currenl Variable Frequency Converter.._ Loaa urrent Fixed Fig 1 Losses in fixed-frequency and variablefrequency switch-mode corwertets $ EEE 103

2 +._ 'E A Ctn - "E, - DRVERS AND CONTROL CRCUT -'L. B D Fig. 2. Synchronous Buck Converter with Current Mode Control. Transistors are SMP60N05. Schottky diode is MBR1035, L=24pH, C,, = 300pF. 4V VBB < 15V. V, = 3.3V. Load Power 0-15 \hi DC analysis of the converter is presented in Section 11, together with an account of various losses. These results are used in Section 11 to facilitate design optimization for maximum efficiency. The AC model and the converter closedloop operation are discussed in Section V. Experimental results of narrow-band noise mitigation via spreading the noise spectrum are presented in Section V.. DC ANALYSS OF A VARABLE-FREQUENCY, CURRENT- MODE CONTROLLED SYNCHRONOUS BUCK CONVERTER OPER- ATNG N THE DSCONTNUOUS MODE circuitry sends a low signal on output B and Qz turns off. The process repeats on the next clock pulse. A. DCAnaysis Referring to the waveforms of Fig. 3, tl = F* L VBB - Vo The converter is shown in Fig.2. Since the output voltage is low, a synchronous rectifier is used to reduce loaddependent conduction losses. The converter at light loads operates in the discontinuous conduction mode with constant peak current and variable frequency. deal waveforms are shown in Fig. 3. Control circuitry has been constructed to allow independent control over the switching frequency, the peak inductor current, the inductor current level at which the synchronous rectifier turns off, and the delay time when one switch turns off until the next switch turns on. The circuit works as follows: At the beginning of the switching cycle, both transistors are off and there is no current in the inductor. A clock pulse causes the control circuitry to send a high signal on output A of the MOS gate driver to cause the Q, transistor to turn on. The voltage across L causes the current to increase linearly with time. The current sense resistor $, senses the current in Q, and the inductor. When the current gets to a pre-set value,, the control circuitry causes A to go low and Q to tum off. After a short time, called the delay time, tdclss, the control circuitry sends a high signal on output B of the MOS gate driver to cause transistor Q2 to turn on. The voltage across Q2 is smaller than the voltage across the Schottky diode would be, thus improving efficiency. During normal operation, the Schottky diode never tums on. The inductor current is sensed by R,,,,,. When the current gets to zero amps, the control Compute the average inductor current: B.. 4 K ; t, : t,! i time 4 k Ts Fig. 3. deal waveforms for variable frequency current-mode controlled converter.

3 peak( tl + t2) peak( tl + t2)fs (i.) = - 2 Ts - 3 Combining (), (2), and (3): (il) =?pcal L fs VBB 2 Vo(VRB-VVo) The average load current is equal to the average inductor current: (3) (4) The capacitor equivalent series resistance (ESR) loss is computed using the current waveshape shown in Fig. 4: Pes, = VBB Lfs VO(VBB - VO) 2. Switching LOSJ Equation (5) gives the steady-state behavior of the system. The maximum load current in the discontinuous mode occurs when t, + t, = T, Switching losses include: inductor core loss. switch voltagekurrent overlap loss, and various capacitor ChargeJdischarge losses. nductor core loss can be approximated as being proportional to the switching frequency, and the peak inductor current squared. The proportionality is k,,,,. At higher load currents, the converter is designed to operate in the continuous conduction mode. B. Power Loss Analysis There are three types of power loss mechanisms in the converter: conduction losses, switching losses, and fixed losses.. Conduction Loss The main sources of conduction loss are due to the on resistance of the two transistors, the inductor winding resistance, the current sense resistor, and the equivalent series resistance of the capacitor: (7) (9) n the discontinuous mode, transistor Q1 will have a voltagekurrent overlap loss when it is turned off. When Q, turns on, the inductor current is zero. When transistor Qz is turned on, the voltage across it is approximately zero, and when it is turned off, the inductor current is zero. f tfallq, is the fall time of the transistor, then the overlap power loss is approximately given by: Figure 5 shows the parasitic capacitances of the converter circuit. C,, = Cdsl + Cschonky. The losses due to charging the cd,, C,,, and C,, capacitances will generally depend on the voltage at v,, when the switching occurs. Fig. 6 shows measured inductor current and vsw waveforms. Energy resonates between the inductor and C,, capacitance, eventually being dissipated due to conduction losses and transformer core losses. The following t 'CO", fsl,, 3 L VBB - Rsensc ''sense 3 V,(VBB-VO) (10) Fig 4 Current through CO", 105

4 Cds rill ponents of efficiency optimization are: A. gate-drive timing for the main and the rectifier switching transistors; B. inductor design, choosing the optimum inductance value. n addition. an appropriate value of output capacitance needs to be chosen for acceptable output ripple. Fig. 5. Parasitic capacitances in the converter circuit analysis assumes v, is approximately zero volts. This situation is the maximum loss case and occurs on the border between continuous and discontinuous modes or when transistor Q turns on when v,, is ringing close to zero volts. Losses due to charging Cgs do not depend on vsw. n the following formulas, AQxl$!~al is the charge needed to charge C, from Vinitial to Vfinal volts. VGG is the maximum amplitude of the gate drive pulses. A Optimization of Gate-Drive Timing 1 The efficiency q =. From (5), the load power +-- = PLoss PLoad Plosd is proportional to f,. From (7) to (15). the loss poher components are also proportional to fs, with the exception of Pes, and P,,,,, which are approximately proportional to f,. Therefore, the efficiency is nearly independent of load and switching frequency, which is the main benefit of operating the converter in the discontinuous conduction mode. As a result, the optimization for any load reduces to minimizing the energy loss in the converter over a switching cycle. Using current-mode control, the fixed peak inductor current, becomes a convenient optimization parameter. f lpeak is higher, conduction losses are higher, but switching losses are lower due to a lower switching frequency. The optimum peak current, where the efficiency is maximum, is approximately independent of load. Fig. 7 shows experiniental results for two loads in the buck converter of Fig. 2. Note the maximum efficiency occurs when lfak =. 1 SA. Optimum Delay Time 111. DESGN AND OPTMZATON The delay time, shown in Fig. 3, can have an effect on efficiency. f the delay time is too short, cross-conduction occurs as both transistors are on at the same time. f the delay time is too long, extra conduction loss through the schottky diode occurs The optimum delay time for a given V,, is the time it 94 With the results of Section 11, it is possible to optimize the converter for maximum efficiency. The most important com- 8o / -+-l0=05a lpeak [A] Fig. 6. Measured inductor current and Vsw waveforms Fig. 7. Efficiency vi. Load Current for two Load Currents 106

5 takes for the inductor current to discharge the C,, capacitance to zero volts. f Q,, is the charge required to do this: Table shows power converter efficiency vs. delay time for two different supply voltages: the maximum input voltage of 15 volts and a nominal voltage of 6 volts. The load power is 0.37 watts and the output voltage is 3.3 volts. pcali is 1.4 amps. A delay time of ns is optimum. A. A C Model Output Circuit The AC small-signal model is shown in Fig. 8. Values for the current sources and resistors can be obtained by perturbing and linearizing <i,>, where <il> is given in (4). The results are: - v2.,. B. nductor Design To design the inductor, the inductance value and the peak current need to be known. The peak current is determined by the efficiency optimization. The inductance value determines the operating frequency range in the discontinuous mode. The maximum frequency that the converter can run at and still stay in the discontinuous mode can be calculated (for a given supply voltage and output voltage), from (5) and (6): B. AC Model nput Circuit From Fig. 3, the input current ib is equal to il during the t, interval of the switching cycle, and zero during the rest of the cycle. The average input current is thus 4, > = (peak From (1), one gets the following results. Determining the value of capacitunce for C,,,, From the CO,, current waveform of Fig. 4, the peak-to-peak voltage ripple, AV, pp on the output capacitor can be calculated (not counting the effect of the equivalent series resistance). Perturbing and linearizing this equation yields the ing results for the ac small-signal input circuit model. Usually, however, the peak-to-peak voltage ripple is determined by the the equivalent series resistance: v. AC SMALL-SGNAL ANALYSS OF A VARABLE- FREQUENCY. CURRENT-MODE CONTROLLED SYNCHRONOUS BJCK CONVERTER OPERATNG N THE DSCONTNUOUS MODE + C. Frequency response and Closed-Loop Operation + TABLE Efficiency [Yo) vs delay time with Load Power = 0 37 watts 6 VBB R A Vo '- SUPP\ delay time ns] Voltage C V V Fig. 8. AC small-signal model 107

6 From the model, the control-to-output transfer function is often inserted into the error amplifier network to improve the low frequency gain. This is done, and the output response is shown in Fig. 1. To maintain adequate phase margin. the zero in the lag-lead network should be at or below the closed loop pole of the converter. No stability problems are evident. v. ELECTRONC NOSE MTGATON t is interesting to note that the converter becomes unstable when up < 0, i.e. when V, 2 (2/3)VBB. This is a result of the current-mode control in the discontinuous conduction mode. The circuit can be made stable at any input voltage when feedback is applied to regulate the output voltage. Fig. 9 shows the block diagram of the feedback loop used in the circuit. The loop gain T(s) is given by L vb0 R ',e& A,, = 2 v, (2 VBB - 3v0) The closed loop pole, which is the zero of 1 + T(s) is: (30) apcl = Up ( + k* k,,o A") (31) For frequency selective portable systems, such as cellular phones, a variable frequency power supply might cause noise problems if the switching frequency or one of its harmonics was in the sensitive bandwidth of the circuit. A technique for spreading the energy of the switching frequency [3] across a wide bandwidth, thus mitigating potential in-band noise, is shown in Fig. 12. During each clock frequency, a different number from the ROM chip is applied to the input of a Digital-to-Analog Converter (DAC). The reference voltage of the DAC is the error voltage from the feedback loop. Thus the output of the DAC is proportional to the number from the ROM and the error voltage. The ROM chip contains numbers which are designed to provide a pseudo random sequence. The DAC output S added to the error voltage, thus modulating the switching frequency, and the modulation is proportona1 to the unmodulated switching frequency. Fig. 13 shows the unmodulated frequency spectrum of the output voltage, and Fig. 14 shows the spectrum with the modulation added. The in-band noise power is attenuated by =1/9 with only a slight increase in output voltage ripple. The number of elements in the ROM is 128. f k,,, k,,, A, >>, the closed loop pole becomes Therefore. the closed-loop converter is stable for all input voltages. Fig. 10 shows the output voltage (ac coupled) transient response of the converter for a current load switching between 0.55 A to 0.1 l A. The output capacitor CO,, is 200pF, V,, is 5 V and V, is 3.3 V. The value for k, is constant with frequency. For good DC regulation, a lag-lead network is Fig. 10. Output voltage (ac) transient response, kfb, is constant Fig. 1. Output voltage (ac) transient response, Fie - 9 Feedback LOOD Bloch Diagram uith lag-lead network on error amplifier 108

7 t should also be noted that the ringing of the vs, voltage, shown in Fig. 6, may also contribute to noise. Care should be taken so that the ringing frequency is not in the bandwidth of the frequency selective circuit. v. CONCLUSONS For applications that operate with a very wide range of load currents, a variable-frequency dc-dc converter is more efficient than a similar fixed frequency converter because the switching loss is proportional to frequency. A variable-frequency current-mode controlled buck converter with synchronous rectification is analyzed and experimentally verified in this paper. The loss mechanisms were found to scale with frequency to a good approximation. Since the load current and power also scale with switching frequency, the efficiency was found to be approximately independent of load. Current-mode control is used to maintain a constant inductor peak current value over the entire discontinuous conduction operation range. The peak current value is selected to maximize efficiency. Efficiency above 92% was measured for a wide range of loads where the converter operates in the variable-frequency, discontinuous conduction mode. An AC small signal model is derived to facilitate feedback loop design. t was found that the converter is open-loop unstable when the output voltage is greater than or equal to two thirds of the supply voltage. However, the voltage feedback loop can be designed so that the converter is stable under all operating conditions. The variable-frequency operation may cause problems in frequency selective applications. As a potential solution to the problem. a method of spreading the noise spectrum was applied and verified experimentally. ACKNOWLEDGEMENT This work was supported in part by the Center for Advanced Manufacturing and Packaging of Microwave, Optical and Digital Electronics (CAMPmode) at the University of Colorado, Boulder. REFERENCES U R --L, DAC Fig. 12. Block Diagram of Electronic Noise Mitigation Technique.-, ,.o *- "._.....DO Do0 *. Fig. 13 Unmodulated switching frequency spectrum of the output voltage "CC [] B.Huffman, R. Flatness, " Power conversion from milliamps to amps at ultra-high effiency (up to 95%), "Linear Technology, Apllication Note 54. March "Battery management and dc-dc converter circuit collection - a power supply application guide for portable equipment." MAXM ntegrated Products A.C Wang, S.R.Sanders. "Programmed pulsewidth modulator waveforms for electromagnetic interference mitigation in DC-DC converters." EEE Trans. on Power Electronics, Vo1.8. No 4. Oct.93, pp Fig. 14. Modulated switching frequency spectrum of the output voltage. 109