AN1616 APPLICATION NOTE

Transcription

1 AN66 APPLICATION NOTE THD-OPTIMIZER CIRCUITS FOR PFC PRE-REGULATORS by Claudio Adragna Although THD (Total Harmonic Distortion) is not explicitly considered in IEC 6-- standards, neither it needs to be very low in order for a piece of equipment to get the presumption of conformity, however it has become established to require an ultra-low THD in some applications such as electronic lamp ballast. This application note, after reviewing some basic theory regarding the main causes of distortion of the current drawn from the mains by PFC pre-regulators, suggests a couple of simple and inexpensive circuits that offer significant benefits in terms of THD reduction. The study has been carried out on a TM (Transition Mode) PFC stage using the L66 IC and the experimental results are presented. Introduction: a little theory THD (Total Harmonic Distortion) is a convenient way of specifying how much a periodic waveform strays from a sinusoid with just a number. Mathematically: THD A RMS A , A where A n is the RMS amplitude of the n th (n=,, ) harmonic component of the waveform, according to Fourier's analysis, and A RMS is the overall effective amplitude. In other words, it is the ratio of the energy associated to higher order harmonics (n>) to the energy of the fundamental component (n=), which has the same frequency as the waveform under consideration. THD is often expressed in %. Figure. Vector diagram and fundamental relationships between quantities involved in PFC A n n = = = A θ ϕ P = Active (Real) Power F = Fundamental App. Power Q = Reactive Power F = P + A = F + Q D A = Total Apparent Power D = Distortion Power THD D = = tan F P PF = = cos ϕ cos θ A Note: for sinusoidal voltage the same vectors represent currents θ The above definition is obviously applicable to any waveforms, however it makes much sense to invoke THD when the waveform is supposed to be close to a sinusoid. Such is the case of the current drawn from the mains by a PFC pre-regulator and its THD may be used as an indicator of how well the pre-regulator is performing. November /6

2 And actually, the real task of PFC pre-regulators is to minimize the THD of the mains current and not maximize the Power Factor (PF), in spite of the name. There are at least two good reasons for that. First, the regulations that a PFC is supposed to help comply with (the well-known IEC 6--) consider PF marginally (it is mentioned only to set a limit in class C equipment); rather, they are concerned about the effective amplitude of each harmonic component. A low THD, although in principle not sufficient to guarantee that each harmonic falls within its own limit, makes this event practically certain: the distortion power (refer to fig. ) is very unlikely to be concentrated on one or few high-order components only, where the limit is low. Second, although related to THD, the PF depends also on elements external to the PFC pre-regulator, such as the capacitors of the input EMI filter. It is quite common, especially at high line and light load, to achieve an excellent THD and yet measure a PF, though high, not so close to unity as one could expect. To clarify this point, the diagram and the basic relationships shown in figure can be helpful. After some trigonometry it is possible to find: cos( ϕ ) PF = () + THD where ϕ is the displacement angle between the input voltage and the fundamental component of the input current. This relationship is graphically shown in figure. Figure. Relationship between THD and PF ϕ = π/ ϕ = PF.9.9 ϕ = π/. THD% It is possible to see that THD degrades very rapidly even with a near unity PF and no phase shift between line voltage and current (with ϕ = and PF=.9, THD is %) and, on the other hand, even with THD= the Power Factor can be low anyway, provided there is enough phase shift (with ϕ = π/ rad =, PF.9), like in reactive linear circuits. PFC pre-regulators introduce no significant phase-shift in the average inductor current, yet it is possible to see the mains current leading the mains voltage by a phase angle that is as larger as the mains voltage is higher and/or the output load is lower. This angle is practically ϕ (it is true that ϕ refers to the first harmonic only but the mains current is basically first harmonic since a PFC is, by definition, a low-thd system). This phase lead is mostly due to the input EMI filter, always to be used to comply with EMC regulations, that makes the low frequency impedance of the converter appear capacitive. Note that only the leakage inductance of the common-mode inductors (and not their self-inductance) or the differential-mode inductors, if used, could give an inductive contribution to the input impedance. This is, however, negligible at the mains frequency and the effect of the X-caps is by far dominant, whence the phase lead. With good approximation, then, ϕ can be expressed as: ϕ tan ( πf L R in C in ) tan V in = πf L C P in, in where f L is the mains frequency, V in the RMS mains voltage and P in the input power of the PFC pre-regulator; C in is the sum of all the X-caps of the EMI filter, plus the capacitor placed after the bridge rectifier, /6

3 C b ; R in = V in/pin is the equivalent large-signal resistance seen from the input of the pre-regulator. There are two major contributors the THD of PFC pre-regulators. The first one is the so-called "Crossover Distortion", which shows up as a small plateau (conduction dead-angle) in coincidence to the zero-crossings of the line voltage. The second contributor is the distortion of the current reference generated by the control IC, which equally reflects on the current drawn from the mains. Both of them will be looked closely. The X-caps of the EMI filter just divert some mains current, giving origin to the voltage-current phase shift, but do not usually have any significant effect on the mains current distortion, i.e. on the THD, neither on the conduction losses of the bridge rectifier. The capacitor after the bridge rectifier C b, instead, has a twofold role: not only it contributes to the phase-shift by adding its capacitance to that of the X-caps, but also worsens the THD by maintaining a residual voltage on the DC side of the bridge rectifier. There is always a residual voltage across C b, which increases with larger C b values, a higher mains voltage and a lower load (i.e. a higher R in ). This residual voltage reverse-biases the diodes of the bridge rectifier as long as the instantaneous mains voltage is lower and blocks current flow from the mains. This phenomenon, exactly identical to that occurring in non-power-factor-corrected systems, gives origin to a small flat portion in the current waveform, that is to a conduction dead-angle. This will be referred to as the "crossover distortion". This deadangle cannot be eliminated completely even with C b = because of the threshold voltage of the bridge rectifier. To complete the picture another effect, interacting and often dominant on that of C b, must be considered. It is the lack of input-to-output energy transfer close to the zero crossings of the mains voltage. This has been already discussed in [] but will be looked more closely here. Near zero-crossings the energy that can be stored in the boost inductor is very low, not enough to charge the total capacitance of the drain node C drain (basically, MOSFET's C oss, boost inductor's parasitic intrawinding capacitance and boost diode's junction capacitance) up to the output voltage V out. As a result, the boost diode will not be turned on for a number of switching cycles (see fig. ) and energy will be confined in the tank circuit made up of the drain capacitance and the boost inductor. C b will be discharged at a lower rate, essentially determined by the losses of the switch and the tank circuit. This can be seen as a sudden rise of R in that may cause the flat portion in the current waveform to anticipate and last longer. In figure the two effects are separated and their impact on the voltage across C b is shown in detail. With reference to figure (C drain = curve), the voltage on C b strays from the ideal haversine when the line phase angle is θ radians away from π, where: θ tan θ = πf L C b R in. Again with reference to figure (C drain = pf curve), input-to-output energy transfer is lacking as long as: -- L P in sin( π ψ) -- C V in drain V out where L is the inductance of the boost inductor. Solving this inequality for ψ, yields:, ψ = sinψ = V out V in P in C drain L. Figure. Voltage on C b in the neighborhood of a zero-crossing θ Cb = nf 6 ψ V(Cb) Cdrain = pf Cdrain = Haversine π π fl t /6

4 The voltage on C b will stray from the haversine slightly after the line phase angle equals π - ψ (the point marked by the circle), depending on how much R in increases. If θ>ψ, which happens for large values of C b, the energy lack phenomenon is hidden by the effect of the residual voltage on C b ; if ψ>θ, it is the energy-transfer lack that is dominant and essentially determines the amount of crossover distortion. It is easy to show that the condition ψ>θ is true as long as C b fulfills the following inequality: V out C b πf L V in C drain L Approximately, the duration T d of the flat portion around the zero-crossings can be considered equal to: α T d , π f L where α (with α = θ or α = ψ, whichever is larger), is assumed as the conduction dead-angle. Figure illustrates the relationship between T d and THD, which, in the range shown (<T d f L <.), can be approximated by: THD% 9T d f L T d f L Figure. Contribution of the current flat portion duration to THD THD% Td fl. A significant contribution to THD, besides that due to crossover distortion, is also given by the distortion of the current reference, used for determining either the envelope of the peak inductor current or its lowfrequency average value, depending on the control scheme adopted by the PFC controller. The current reference is obtained from the rectified mains voltage, properly scaled down, by multiplication to the error signal of the voltage control loop, for consistency: the higher the mains voltage, the lower the current reference needs to be, and vice versa in order for the output voltage to be kept constant. Provided the rectified mains voltage is a perfect haversine, to get an undistorted current reference, the error signal (i.e. the output of the error amplifier of the PFC controller) must be a DC voltage: any AC component, multiplied by the haversine (which is fed into PFC controller's multiplier input, through a resistor divider) would give origin to higher order harmonic components. This is what actually happens. As a matter of facts, the output voltage of a PFC stage has a twice-mains-frequency ( f L ) ripple component V OUT superimposed on top of the DC regulated value and the error amplifier has a gain, though low, however not zero at that frequency (G fl ). Hence a portion of that ripple, V COMP = G fl V OUT, will appear at the error amplifier output, superimposed on top of the DC value V COMP. With some simple algebra, it is possible to show that this ripple originates an additional mains-frequency component and a third-harmonic component in the current reference, both of amplitude equal to V COMP / and with the same phase-shift (depending on loop's phase margin) with respect to the mains current. Obviously, this current reference distortion reflects on the current drawn by the PFC pre-regulator from the mains in the same way, hence increasing THD. /6

5 The contribution to THD, with good approximation, is given by: V COMP THD% V COMP V COMP where V COMP is the error amplifier output for duty cycle (.V in the L66 [],.V in the L9 []). Like the THD originated by crossover distortion, also this contribution gets bigger at high input voltage (because V COMP gets lower and G fl increases, thus making V COMP larger). Lighter loads result in a lower V COMP as well, however the ripple at the PFC output, and thereby V COMP, decrease proportionally. Thus, ideally, there is no dependence on the load. Figure. Effect of error amplifier output ripple on the current-reference ( rd harmonic distortion) current reference reference distorted by rd harmonic undistorted reference t An example of the effect of the rd harmonic distortion on the current reference is illustrated in figure (the THD of the distorted waveform is.). As previously said, the amplitude of the f L ripple depends on the gain of the error amplifier at that frequency and, therefore, on how the error amplifier is compensated. In this respect, the addition of a zero in the error amplifier gain, to improve stability by a larger phase margin and reduce the tendency to over/undershooting following on step-load changes, flattens out the gain at f L, whereas the gain obtained with just a single pole is still rolling off at - db/decade. Thus a PFC pre-regulator compensated for a constant-power load [] exhibits a THD higher than that of a PFC compensated for a resistive load, with the same crossover frequency. To get a quantitative idea, let us consider the f L gain of the error amplifier compensated with a single pole at the origin (one capacitor between E/A input and output); it is approximately given by: G fl f c ---, A c f L where A c is the gain of the boost power c and f c is the open-loop crossover frequency (e.g. Hz). By using a compensation network like that considered in [], with the zero placed at the crossover frequency so as to achieve phase margin, the f L gain will be: G fl A c Considering what the typical values for f c and f L are, G fl can be about three to four times higher than in the previous case. In systems comprising line voltage feedforward (/V correction) to keep the power stage gain constant over the mains voltage range, the residual f L ripple ( V FF ) superimposed on the DC value (V FF ) representing the RMS line voltage and that is fed into a multiplier input is another source of distortion for the current reference. This is the case, for instance, of the L9 []. Again with some simple algebraic manipulations, it is possible to show that this residual ripple originates an additional mains-frequency component and a third-harmonic component in the current reference, both of amplitude equal to V FF and in phase with the mains current. The contribution to THD (which will be summed to that caused by the E/A /6

6 residual ripple), with good approximation, is given by: THD% V FF V FF In systems working in Transition Mode (TM), like those controlled by the L66, another non-ideality is that they do not work exactly on the boundary between Continuous and Discontinuous Conduction Mode, as as-sumed for the sake of simplicity.they are actually Discontinuous Mode systems because of the dead time T ( T = π LC drain in case of optimum ZCD adjustment, see []) occurring after inductor's demagnetization and before MOSFET's turn-on, during which the drain voltage drops to its minimum value as a result of the boost inductor ringing with the parasitic drain capacitance. The presence of the dead-time results in a not exactly sinusoidal low-frequency component of the inductor current even with a perfectly sinusoidal reference. This contribution worsens THD when T is not or no longer negligible as compared to MOSFET's ON-time, that is at light load or when the system is designed with a low L (i.e. high switching frequency). Other minor contributions are given by non-idealities present in the system: for example, the voltage offset of the PWM comparator inside TM PFC controller IC's emphasizes crossover distortion if positive, especially at light load, where the signal-to-offset ratio is lower. Need for THD optimization There is usually plenty of room between the limits to be respected in order for a piece of equipment to pass the regulatory requirements of IEC 6-- and the actual harmonic contents resulting from the action of a PFC pre-regulator. As a reference, an upgraded version of the W wide-range typical application circuit shown in figure of the L66 datasheet [] will be considered. The circuit has been modified according to the recommendations given in []: C, called C b in the previous discussion, has been reduced from µf to nf, an STTA6 has been used in place of the BYT-6 as D and the STPNA has been replaced with an STPNC. The electrical schematic is shown in figure 6 and the changes are highlighted by bold italic characters. Figure 6. W, wide-range L66-based PFC pre-regulator: electrical schematic D STTA6 FUSE A/V Vac (V to 6V) + - BRIDGE x N7 C. µf V R kω R9. MΩ D N D NB C6 nf R Ω R 6 kω 6 T C µf L66 7 R7 99 kω R Ω MOS STPNC Vo=V Po=W C 7µF V NTC R kω C µf V C7 nf R6.Ω W R 6. kω - 6/6

7 Figure 7. W, wide-range L66-based PFC pre-regulator: harmonic measurement W, Vac) Harmonic Current [ma] Measurement Class C limits Class D limits Harmonic Order [n] Vin = Vac, Pout = W THD =.% PF =.9 Figure 7 shows the harmonic measurement result along with the limits envisaged by IEC 6-- standard for both class C and class D equipment and it is possible to see that it is by far within. With the above-mentioned changes the THD has been reduced by about % (@ Vac). The design tips in [] also make easier to handle a wider input voltage range (e.g. including also the 77 Vac mains) or a load that can change in a limited interval with acceptable results. However in some cases, those recommendations cannot be put into practice for some reason or might not be enough to meet some special design target that, although exceeding regulatory requirements, may be required to the designer or have become established in some particular area. Additionally, there might be some special design cases that cannot be handled easily. Typical examples are: a) In electronic lamp ballast there is a market requirement calling for THD<% and sometimes less. In case of multiple lamp supply, low THD is desired even if one or more lamps are disconnected. b) In some power supplies with wide-range mains operation, presumption of conformity is required not only at the rated load but in a range (sometimes broad) of load conditions. c) Some power supplies are specified for a maximum continuous output power and required to deliver a peak power level, sometimes considerably higher, for a limited time. In this case it makes sense to require presumption of conformity under the maximum continuous load conditions rather than the peak load. This is practically equivalent to point b), since the system will be designed for the peak level, except for the thermal point of view. THD optimization: the crossover distortion reducer The first THD-optimizer circuit is shown in figure, highlighted by the boxed area. The purpose of this circuit is to minimize the crossover distortion. It will not give ant benefit against the rd harmonic distortion caused by the residual f L ripple on the output of the error amplifier, which will be handled by the second THD optimizer circuit considered in this note. It will also give no aid in counteracting the PF drop at light load or high line, since this is mostly due to the increase of ϕ but, as previously said, this is of little concern. The idea behind this circuit is to force the system to handle some excess energy near the zero-crossings so as to meet the double target of minimizing the number of cycles where the energy in the boost inductor is not passed on to the output and of fully discharging C. This can be done by artificially increasing the ON-time of the power switch with either a positive offset on the multiplier input (Pin, MULT) or a negative offset on the current sense input (pin, CS). The latter choice has turned out to be more effective [6]. This circuit will be maximally effective when crossover distortion is mostly due to energy transfer lack, that is for the case ψ>θ. 7/6

8 Figure. W, wide-range PFC pre-regulator with crossover distortion reducer: electrical schematic D STTA6 R D N C6 R T R7 99 kω Vo=V Po=W FUSE A/V Vac (V to 6V) + - BRIDGE x N7 C. µf V kω R9. MΩ D NB nf A 6 Ω R 6 kω C µf L66 7 R Ω MOS STPNC C 7µF V NTC R kω C µf V C7 nf A N kω µf V Ω R6.Ω W R 6. kω - Crossover dist. reducer The N and the µf cap generate a negative bus proportional to the mains voltage, depending on the turn ratio of the auxiliary winding of the boost inductor. Then a summing node is created on the current sense input (pin, CS) with a Ω resistor between the sense resistor R6 and pin and another resistor to the negative voltage. This resistor needs to be adjusted experimentally to find the optimum condition. The fine-tuning will be done at maximum mains voltage, which is usually the worst-case condition, until the value that provides the minimum THD is found. The offset added in these conditions is typically about mv. Summarizing the result, the THD reduction offered by the circuit at full load goes from 6% at low mains (where THD is already very low) to % at maximum mains. The improvement at half load is even more noteworthy, from % to 7%, resulting in THD below all over the entire input voltage range both at full and half load. The oscilloscope pictures of figure 9 show the mains current and the voltage after the bridge diode (across C) in the circuit of figure 6. In figure it is possible to note the effect of the optimizer circuit of figure : the flat portion is much reduced and C is nearly fully discharged. The pictures in figures and allow comparing the behavior near the zero-crossings (note the almost straight mains current, the much longer ON-time, the negative offset on the current sense and the much fewer cycles where the drain stays below the output voltage during the OFF-time). Figures, and show the improvement in terms of THD reduction and harmonic contents distribution. Figure 9. Mains current and voltage on Vac: a) Pout= W; b) Pout = W (not optimized) Imains Imains V (C) V (C) a) b) /6

9 Figure. Mains current and voltage on Vac: a) Pout= W; b) Pout = W (optimized) Imains Imains V (C) V (C) a) b) Figure. Not optimized Vac, W: a) Crossover distortion; b) Zoom of a) Imains Vcs Vdrain Vdrain a) b) Figure. Optimized Vac, W: a) Residual crossover distortion; b) Zoom of a) Imains Vcs Vdrain Vdrain a) b) 9/6

10 Figure. THD measurements at full and half load THD [%] THD vs. Pout = W THD [%] THD vs. Pout = W O timized Not o timized O timized Not o timized 7 6 Figure. Comparison of Harmonic Contents at full load H [%] Harmonic Pout = W (% of fundamental) (NOT OPTIMIZED) H [%] Harmonic Pout = W (% of fundamental) (OPTIMIZED) 7 6 rd th 7th Others 7 6 rd th 7th Others Figure. Comparison of Harmonic Contents at half load H [%] Harmonic Pout = W (% of fundamental) (NOT OPTIMIZED) H [%] Harmonic Pout = W % of fundamental OPTIMIZED 7 6 rd th 7th Others rd th 7th Others 7 6 THD optimization: the ripple compensator The purpose of this second circuit is to minimize the rd harmonic distortion caused by the residual f L ripple superimposed on the output of the error amplifier. Like the first circuit, it has negligible effect on PF. The idea behind this circuit is to inject a voltage ripple in the error amplifier that counteracts the one across the output bulk capacitor of the PFC pre-regulator and coming from the high-side resistor of the output divider. The other sinusoidal-like signal in the circuit is that fed into the multiplier input (Pin, MULT) to generate the sinusoidal current reference, hence it will be used. The circuit, shown in the schematic of figure 6, will be referred to as the "ripple compensator" circuit. /6

11 Figure 6. W, wide-range PFC pre-regulator with both THD-optimizer circuits: electrical schematic D STTA6 FUSE A/V Vac (V to 6V) + - BRIDGE x N7 C. µf V R kω R9. MΩ D N D NB C6 nf A 6 R Ω R 6 kω T C µf L66 7 R7 99 kω R Ω MOS STPNC Vo=V Po=W C 7µF V NTC R kω C µf V C7 nf A N kω µf V Ω R6.Ω W R 6. kω - Crossover dist. reducer Ripple compensator kω CC= nf The compensator capacitor, C c, injects a current 9 out-of-phase with respect to the one coming from the high-side resistor of the output divider R7. The average value of this additional current is zero, thus the output voltage setting will not be altered. The purpose of the series resistor is to limit high-frequency currents that would otherwise find a low-impedance path to pin through C c and C, and that could falsely trigger the dynamic OVP of the L66, if over µa. The resistor value has little effect on the ripple compensation, provided its impedance is much smaller than that of C c at the mains frequency (say, less than /). In the specific case, few kω were enough to avoid any malfunctioning due to improper OVP activation and a kω resistor has been chosen to have a good safety margin. Without going into complex calculation to find the optimum value of C c, that is the one giving the minimum ripple amplitude at the output of the error amplifier and then the minimum THD, it is reasonable to assume that the optimum will be achieved when the amplitudes of the injected currents are equal, that is when: V out = π f, R7 L Cc opt V MULTpk pk which, solved for Cc opt, yields: V out Cc opt = πf L V MULTpk pk R7 In the above equations, V out is the peak amplitude of the f L output ripple and V MULTpk-pk is the peakto-valley amplitude of the signal at pin MULT. The calculation will be done at maximum mains voltage where the loop gain is maximum and the (uncompensated) ripple amplitude is maximum as well. The experimental results confirm the initial intuitive assumption: selecting the available capacitance standard value closest to the result of the above calculation gives actually minimum THD. The ripple compensator circuit can be used both alone and in conjunction with the crossover distortion reducer, as in the schematic of figure 6. Its effect, qualitatively and quantitatively, will not change significantly. Note, however, that the ripple compensator circuit has a loading effect on the resistor divider that feeds pin MULT. Hence, the valley voltage of the multiplier input will be a bit larger, which goes in the same direction as the crossover distortion reducer. To avoid overcompensation, which would result in small current spikes near the zero-crossings at low line, the negative offset provided by the crossover distortion reducer must be slightly diminished. In the schematic of figure 6 it is possible to notice that the resistor /6

12 connecting the negative bus to the current sense pin has been increased from to kω. The ripple compensator offers an additional - THD reduction at full load in the European mains range while giving little contribution in the US mains range. As a result the THD has been kept below % over the entire mains range. The oscilloscope picture of figure shows how the ripple at the output of the error amplifier is reduced by about 6% by the compensator circuit. Figure 9 illustrates THD improvement while figures and show how harmonic component are distributed. All of them are referred to the circuit of figure 6 compared to that of figure. The effect of the ripple compensator is more apparent when the control loop of a PFC pre-regulator is compensated with a pole-zero couple [], as shown in the schematic of figure 7. In this case, as previously said, the rd harmonic contribution to THD is considerably larger, then its mitigation leads to more conspicuous results. Figure 7. W PFC pre-regulator with both THD-optimizer circuits and pole-zero loop compensation D STTA6 R D N C6 R T R7 99 kω Vo=V Po=W FUSE A/V Vac (V to 6V) + - BRIDGE x N7 C. µf V kω R9. MΩ D NB nf A 6 Ω R 6 kω µf 7 kω L66 7 kω R Ω MOS STPNC C 7µF V N kω NTC R kω C µf V C7 nf A µf V Ω R6.Ω W R 6. kω - Crossover dist. reducer Ripple compensator kω CC= nf In this case, the additional THD reduction by the compensator can be from to at full load, all over the entire mains range, leading to results very close to those of the system compensated with a single pole at the origin. Figure shows THD in the circuit of figure 7 with and without the use of the ripple compensator. Figure. L66 E/A output ripple reduction with the ripple compensator circuit (@ Vac, W) compensated not compensated /6

13 Figure 9. THD measurements at full and half load: circuit of fig. 6 vs. circuit of fig. THD [%] THD vs. Pout = W THD [%] THD vs. Pout = W Optimized and compensated Optimized, not compensated Optimized and compensated Optimized, not compensated Figure. Comparison of Harmonic Contents at full load (circuit of fig. 6 vs. circuit of fig. ) H [%] Harmonic Pout = W (% of fundamental) (OPTIMIZED, NOT COMPENSATED) H [%] Harmonic Pout = W (% of fundamental) (OPTIMIZED AND COMPENSATED) rd th 7th Others rd th 7th Others Figure. Comparison of Harmonic Contents at half load (circuit of fig. 6 vs. circuit of fig. ) H [%] Harmonic Pout = W (% of fundamental) (OPTIMIZED, NOT COMPENSATED) H [%] Harmonic Pout = W (% of fundamental) (OPTIMIZED AND COMPENSATED) rd th 7th Others rd th 7th Others Figure. THD measurements at full and half load: circuit of fig. 7 w and w/o ripple compensator THD [%] THD vs. Pout = W (pole-zero voltage loop compensation) THD [%] THD vs. Pout = W (pole-zero voltage loop compensation) Optimized and compensated 6 Optimized, not compensated 7 6 Optimized and compensated 6 Optimized, not compensated 7 6 /6

14 EMI Filter All of the measurements have been done connecting the PFC pre-regulator to the AC source through the EMI filter illustrated in figure. This filter, although not tested for compliance with EMC regulations, attenuates the level of high frequency appearing on the mains current waveform that could mislead the measurement system. Figure. EMI filter used for the measurements to the AC source 7 nf X 7 nf X. nf Y. nf Y to the L66 board 7 mh Conclusions Two simple and inexpensive THD-optimizer circuits, the crossover distortion reducer and the ripple compensator, have been presented. They have been applied to an L66-based PFC pre-regulator and, with their combined action, the THD has been kept below % at full load, all over the input voltage range. Also at half load the benefit is considerable since the measured THD has been below for any input voltage. Their usage, although not necessary in a number of applications, can be advantageous in some cases such as lamp ballast or SMPS where quality requirements call for presumption of conformity on a broad load range. REFERENCES [] "L66, Power Factor Corrector" (DATASHEET) [] "Design Tips for L66 Power Factor Corrector in Wide Range" (AN) [] "Control loop Modeling of L66-based TM PFC" (AN9) [] "L66 Enhanced Transition Mode Power Factor Corrector) (AN966) [] "L9, Power Factor Corrector" (DATASHEET) [6] "Transition Mode Power Factor Correction Device in Switching Power Supplies", STMicroelectronics' European Patent Application. [7] Nalbant, M. K. "Power Factor Calculations and Measurements", Applied Power Electronics Conference and Exposition, 99. APEC '9. Conference Proceedings 99. /6

15 APPENDIX Derivation of the THD vs. T d relationship Following the approach outlined in [7] it is possible to arrive at the following expression of the PF as a function of the angle φ, which is half the conduction dead-angle defined in this context: PF This expression can be re-written entirely in terms of the conduction dead-angle φ: PF Solving eqn. for THD with ϕ = : = π φ sinφ π ( π φ)sin φ -- φ sin + -- π φ π φ sinφ = π[ ( π φ) ( cosφ) sinφ] THD , PF substituting the above expression of PF and expressing in percent yields: THD% = π ( π φ) ( cosφ) sinφ. ( π φ sinφ) Figure A shows graphically the relationships of PF and THD% vs. the conduction dead-angle φ. Note that these expressions can be applied even to the input current of non-power-factor-corrected AC/DC converters. Figure A. Relationships of PF and THD as functions of the conduction dead-angle = PF.7.. THD% - π/ π/ π/ π - π/ π/ π/ π φ φ The exact expression can be approximated by the following best-fit function: 9 φ π -- THD% φ π -- (see the dotted line in the right diagram of figure A) that provides less than % error in the range <φ<π/ and less than % error in the range <φ<π/. Being φ the conduction dead-angle, the duration of the flat portion in the mains current is: φ φ T d = = π f L π f L Combining this expression with that of THD% the result is: THD% 9T d f L T d f L /6

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