CPU-Modul Documentation. Fujitsu Microelectronics Europe GmbH Am Siebenstein Dreieich-Buchschlag, Germany

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1 CPU-Modul Documentation Fujitsu Microelectronics Europe GmbH Am Siebenstein -0 0 Dreieich-Buchschlag, Germany

2 History Revision Date Comment V New Document

3 Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for all products delivered free of charge (e.g. software include or header files, application examples, target boards, evaluation boards, engineering samples of IC s etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, all these products are intended and must only be used in an evaluation laboratory environment.. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 0 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of year from the date of receipt by the customer.. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH entire liability and the customer s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated.. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH and its suppliers liability is restricted to intention and gross negligence. NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law, in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect.

4 Important notice This Starterkit contains an evaluation board, documentation and software on a CD-ROM. For documentation or software updates, please refer to our web site Fujitsu reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice V.0

5 . Introduction The Fujitsu CPU-Modul is a low cost multifunctional evaluation board for Fujitsu -Bit Flash microcontroller that makes it easy to evaluate and demonstrate almost all features of the MB0 microcontroller series. It can be used stand alone for software development and testing as a simple target board to work with the emulator system. It gives you the possibility to develop and evaluate applications with devices of the new embedded-graphic-controller family. Its modular concept makes it available to use one of several graphic device subboards just by plugging them to the CPU board. The board allows the designer immediately to start the software development before his own final target system is available.. Features Socket QFP0 for Microcontroller MBF (or emulation socket), surrounded by headers for test-pins etc. MHz or khz crystal selectable DC Power supply circuit (incl. testpins for VCC,, power LED and switch) MB external SRAM available for user code and data External Reset Button for MCU Buttons for ext. Interrupt (USER_0 = ext. Interrupt0, USER_ = ext. Interrupt) MAX + DB (female) connector for internal UART CAN transceiver and DB (male) for internal CAN0 LEDs (on Port J) All peripheral pins are available by the connectors Peripheral_ and Peripheral_ Graphic controller interface

6 . Jumpers and Switches This chapter describes all jumpers and switches which can be modified on the evaluation board. The default setting is shown with a gray shaded area. All jumpers and switches are named directly on the board by its meaning, so it is very easy to set the jumpers according to the features.. Power Supply Voltage (SW, JP, JP, JP, JP, JP, JP) Switch setting Power supply voltage - Power ON (SW) - Power OFF V power supply ON (closed) Power supply (JP) OFF (open) NO Power supply V0 power supply ON (closed) Power supply (JP) OFF (open) NO Power supply Bypass Capacitor Pin ON (closed) Voltage regulator enable (JP) OFF (open) Voltage regulator disable Power supply for SMT ON (closed) Power supply (JP) OFF (open) NO Power supply V0 Power supply ON (closed) Analog Power supply (JP) OFF (open) NO Analog Power supply Power supply for LEDs ON (closed) Power supply (JP) OFF (open) NO Power supply NOTE: The supply voltage for the core and the IO Pins must be set. Otherwise it could happen that the controller does not work correctly!

7 . Operating Mode (SW) SW Boot signal (SW/) DIP switch setting ON Logical value 0 (low) Boot signal MD (SW/) ON 0 (low) MD (SW/) ON 0 (low) Internal ROM mode MD0 (SW/) ON 0 (low). UART (JP, JP) SOT_0 ON (closed) UART0 Output enable (JP) OFF (open) UART0 Output disable SIN_0 ON (closed) UART0 Input enable (JP) OFF (open) UART0 Input disable Reserved future extension: SIN_ (JP) UART Input enable SOT_ (JP) UART Output enable UART clock (JP) UART clock enable. Chip select enable for FLASH (JP0) CS CS ON (closed -) Ext. Flash Chip-Select CS ON (closed -) Ext. Flash Chip-Select

8 . Hardware Standby (JP) HSTX (JP) - - HSTX request is released. Clock Select (JP, JP, JP, JP0) SELCLK - Clock enable (JP) - Clock disable MHz clock - MHz clock enable (JP) - MHz clock disable khz clock - khz clock enable (JP) - khz clock disable Low pass filter (JP0) - - Low pass filter for clock enable Low pass filter for clock disable. CAN controller interface (JP, JP) CAN transmit ON (closed) Transmit data enable (JP) OFF (open) Transmit data disable CAN receive ON (closed) Receive data enable (JP) OFF (open) Receive data disable

9 Header for Debug Signals Power supply voltage (JP, JP, JP, JP, JP, JP) JP - V JP - V JP -.V JP -._V JP -._V separated voltage JP -._V separated voltage MCU Peripheral Signals Peripheral_ BUS_PH-0 - A/D Converter input [:0] BUS_PG-0 - A/D Converter input [:] PI - ATGX A/D converter Trigger input DA0 - D/A Converter output 0 DA - D/A Converter output ALARM - Alarm comparator input BUS_PK- - External Interrupt [:] BUS_PL-0 - Input Capture Unit input [:0] BUS_PL- - Output Compare Unit output [:] Peripheral_ PM0 - Sound Generator SGO PM - Sound Generator SGA BUS_PN-0 - Serial I/O Interface signals (SOT-, SIN-, SCK-) BUS_PO-0 - PPG output [:0] PP- - CAN Controller Signals (TX0-, RX0-) PQ- - Serial I/O Interface signals (SOT-, SIN-) BUS_PR-0 - PWM Pulse Generator Signals for Stepper Motor Controller For more information please look at the Hardware Manual of the microcontroller and the Data Sheet of the SRAM LV00TC.

10 . Connectors. Serial Interface Connector P The following diagram shows the connection of the -pin D-Sub female connector P which is used for the serial interfaces. DTR RXD TXD NC o o o o o o o o o CTS RTS DSR TXD is the transmit output, RXD is the receive input. The DTR signal is used as an input,which can be connected to generate a reset.. Power Connector J The following figure shows the power connection jack J. This connector is used to connect an external regulated DC power supply voltage (.V-V DC) to the evaluation board. It is recommended to use.v to keep the power dissipation to a minimum. Otherwise an additional heat sink for the linear voltage regulator might be necessary. Shield is connected to positive voltage supply (+) Centre is connected to ground (). CAN Interface Connector The following diagram shows the connection of the -pin D-Sub male connector P which is used for the CAN interface. CANL o o o o o o o o o CANH For the CAN interface the resistor trimmer R is used to adjust the slew rate. Take care that the slew rate is adjusted according to the local environment (CAN network configuration, transfer rate) NOTE: To use the board as target for the In-Circuit-Emulator, unscrew the socket and remove the MBF from the socket. Be careful not to bend any pins of the chip! Using a vacuum chiphandler is highly recommended. Then mount the emulator probe-cable on top of the QFP-socket. Use the provided screws and make sure the cable has the right orientation. Follow the emulator set-up manual on the CD-ROM for any further steps. 0

11 . Schematics and Drawings

12 V VccV_ VccV V VD VSTBY PM0 PM SDA SCL BUS_PN[0:] BUS_PO[0:] Tx_0 Rx_0 PP PP PP PP SIN_0 SOT_0 PQ PQ PQ PQ BUS_PR[0:] BUS_PortS[0:] D PM0 PM BUS_PN0 BUS_PN BUS_PN BUS_PN BUS_PN BUS_PN BUS_PO0 BUS_PO BUS_PO BUS_PO BUS_PO BUS_PO BUS_PO BUS_PO Tx_0 Rx_0 SIN_0 SOT_0 BUS_PR0 BUS_PR BUS_PR BUS_PR BUS_PR BUS_PR BUS_PR BUS_PR BUS_PortS0 BUS_PortS BUS_PortS BUS_PortS BUS_PortS BUS_PortS BUS_PortS BUS_PortS D VccV0 VccV0 MD0 MD0 User_0 User_ C B VccV VccV_ VccV_ VccV_ BUS_A[0:0] Flash_enable ULB_RDX ULB_WRX BUS_A[0:0] Flash_enable ULB_RDX ULB_WRX0 VccV VccV_ VccV_ VccV_ BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A0 BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A VccV Flash_enable VccV VccV BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A0 BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A VccV Flash_enable VccV VccV 0 0 MD MD SIN0 SOT0 U AMLV00/SO A0 DQ0 A DQ A DQ A DQ A DQ A DQ A DQ A DQ A DQ A DQ A0 DQ0 A DQ A DQ A DQ A DQ A DQ/A- A A RY/BY BYTE CE OE RESET WE VCC U AMLV00/SO A0 DQ0 A DQ A DQ A DQ A DQ A DQ A DQ A DQ A DQ A DQ A0 DQ0 A DQ A DQ A DQ A DQ A DQ/A- A A RY/BY BYTE CE OE RESET WE VCC User_ MD BOOT MD Tx0 SIN_0 Rx0 SOT_0 BUS_D0 BUS_D BUS_D BUS_D BUS_D 0 BUS_D BUS_D BUS_D 0 BUS_D BUS_D BUS_D0 BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D0 0 BUS_D BUS_D BUS_D 0 BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D0 BUS_D User_ BOOT TX_0 RX_0 BUS_D[0:] BUS_D[0:] LED0 LED0 LED LED LED LED LED LED LED LED LED LED LED LED LED LED BUS_PH0 BUS_PH BUS_PH BUS_PH BUS_PH BUS_PH BUS_PH BUS_PH BUS_PH[0:] BUS_PG0 BUS_PG BUS_PG BUS_PG BUS_PG BUS_PG BUS_PG BUS_PG BUS_PG[0:] PI DA0 DA ALARM User_0 User_0 User_ User_ Interrupt_A Interrupt_A Interrupt_B Interrupt_B BUS_PK BUS_PK BUS_PK BUS_PK BUS_PK[0:] BUS_PL0 BUS_PL BUS_PL BUS_PL BUS_PL BUS_PL BUS_PL BUS_PL BUS_PL[0:] ULB_CS CS CS CS CS CS CS CS CS CS CS CS CS ULB_DREQ ULB_DACK DEOP_0 DEOP_ LED0/PJ0 LED/PJ LED/PJ LED/PJ LED/PJ LED/PJ LED/PJ LED/PJ AN0/PH0 AN/PH AN/PH AN/PH AN/PH AN/PH AN/PH AN/PH AN/PG0 AN/PG AN0/PG AN/PG AN/PG AN/PG AN/PG AN/PG ATGX / PI DA0 DA ALARM INT0 / PK0 INT / PK INT / PK INT / PK INT / PK INT / PK INT / PK INT / PK IN0 / PL0 IN / PL IN / PL IN / PL OUT0 / PL OUT / PL OUT / PL OUT / PL CS0X / P CSX / P CSX / P CSX / P CSX / P CSX / P CSX / P DREQ0 / PB0 DACK0 / PB DEOP0 / PB TESTX CPUTESTX LTESTX MD0 MD MD0 MD MD MD SGO / PM0 SGA / PM SDA / PM HSTX SCL / PM RES INITX SOT / PN0 SIN / PN SCK / PN SIN / PN SOT / PN SCK / PN OCPA0 / PO0 OCPA / PO OCPA / PO OCPA / PO OCPA / PO OCPA / PO OCPA / PO OCPA / PO MONCLK SELCLK X0 X X0A XA CPO VCI VccVcut-0 VccVcut- VccVcut- VccVcut- MONCLK 0 FRV FRV TP CLK D0 D D D D D D D D D D0 D D D D D D D D D D0 D D D D D D D D D D0 D U A0 A MBF A A A A A A A A A0 A A A A A A A A A A0 RDY BGRNTX / P BRQ / P RDX AS / P0 ALE / P CLK Remark: AH/BOOT / P Numbers_behind_the_Vcc-Pins_only_to_seperate_them_in_the_DesignRuleCheck! WR0X WRX WRX WRX JP V TX0 / PP0 RX0 / PP TX / PP RX / PP TX / PP RX / PP Vdd-0 Vdd- Vdd- SIN0 / PQ0 SOT0 / PQ SIN / PQ SOT / PQ SIN / PQ SOT / PQ 0 Vdd-int VddX Vcc/C Vss-0 Vss- Vss- Vss- 0 Vss- Vss- Vss- Vss- Vss- HVss-0 HVss- HVss- HVdd-0 HVdd- AVcc AVRH AVss, AVRL PWMP0 / PR0 PWMM0 / PR PWMP0 / PR PWMM0 / PR PWMP / PR PWMM / PR PWMP / PR PWMM / PR JP Vcc/C JP JP JP HVdd AVdd V0 C0 00nF PWMP / PS0 PWMM / PS PWMP / PS PWMM / PS PWMP / PS PWMM / PS PWMP / PS PWMM / PS VccV BUS_D0 BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D0 BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D0 BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D0 BUS_D BUS_A0 BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A0 BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A0 BGRNT BRQ AS ALE BOOT BUS_D[0:] BUS_A[0:0] ULB_RDY BGRNT BRQ ULB_RDX AS ALE ULB_CLK BOOT ULB_WRX0 ULB_WRX ULB_WRX ULB_WRX C B A FRV R x k CS0 CS CS CS CS CS CS ULB_CS CS CS CS CS CS CS ULB_RDY C 00nF FRV C VccV C 00nF C 00nF FRV C 00nF C 00nF C 00nF C 00nF C 00nF C 00nF C 00nF C0 00nF JP HSTX JP SELCLK JP MHz Y MHz C pf C pf JP khz Y khz C pf C pf R 0k R k C 0nF JP0 VCI A Title CPU-BOARD (CREMSON-Starterkit) Thomas Menzl, May 000 Size Document Number Rev C CPU-Board / FR.0 Monday, May, 000 Date: Sheet of

13 JP JP SOT_0 SIN_0 TxD U RxD SIN0 P V VccV_ SOT0 V ROUT ROUT TOUT TOUT VCC RIN RIN TIN TIN 0 C + uf C+ C- VccV D D C C+ C- VD VSTBY V+ uf V- UART_0 R R MAX k k C C SW C C User_0 User_0 0.uF uf 0.uF 0.uF User_ SW User_ User_ P User_ + C 0.uF + C 0.uF U0 JP TX_0 CAN_Tx0 Tx0 Rx0 Txd CANH C C JP RxD CANL RX_0 Vcc Vref CAN_Rx0 Rs CAN_0 c0 R k R k R k D LED0 LED0 LED0 D LED LED D B B LED SW RESET R R0 R R D U LED LED 0k 0k 0k 0k RESET MR RESET RES JP R LED + C MD0 MD MD0 D0 VCC LED MD MD 0.uF LED LEDs on/off MD LED MAX BOOT BOOT D LED LED LED D C LED LED x k SW MODE0.. / BOOT LED D LED LED LED D A LED A LED LED Title CPU-BOARD (CREMSON-Starterkit) Thomas Menzl, May 000 Size Document Number Rev B CPU-Board / Periphery.0 Date: Monday, May, 000 Sheet of

14 D N00 TP & TP: VccV0 schraubbare Klemmen, um Netzteil anzuschliessen! JP V0 D D J DC in SW VD VSTBY Power On/Off TP U D LT V N00 VIN VOUT VccV R ADJ/ C + C C 0 JP uf + C V 0uF D U D LT V N00 VIN VOUT VccV_ ADJ/ B B D N00 VccV_ + C0 uf VccV_ A A 0uF D Title CPU-BOARD (CREMSON-Starterkit) Thomas Menzl, May 000 Size Document Number Rev C CPU-Board / PowerSupply.0 Monday, May, 000 Date: Sheet of TP TP DC in C 0uF D N00 D N00 U L0 ( Amp) VIN VOUT + C 0uF + C 00uF + C 0.uF C 00nF R k JP V0 D N00 R k (%) R k (%) D N00 + C uf + C 0uF R k (%) R k (%) U D LT N00 VIN VOUT ADJ/ + C 0uF R0 0 JP V_ D V0 D0 JP V_ V D R k (%) V D N00 U D LT N00 VIN VOUT + C uf ADJ/ R k (%) R k (%) V + V R 0 VccV_ R k (%) + C R 0 JP V_ VccV_

15 D D C C B B A A CPU-Board / Modul-Connectors.0 CPU-BOARD (CREMSON-Starterkit) Thomas Menzl, May 000 A Monday, May, 000 Title Size Document Number Rev Date: Sheet of BUS_PR BUS_PO BUS_PR BUS_PR BUS_PR BUS_PR BUS_PO BUS_PO BUS_PO0 BUS_PO BUS_PO BUS_PO BUS_PO BUS_PR BUS_PR BUS_PH0 BUS_PH BUS_PH BUS_PH BUS_PH BUS_PH BUS_PH BUS_PG BUS_PG BUS_PG BUS_PG BUS_PG BUS_PG BUS_PG PI DA0 DA ALARM BUS_PK BUS_PK BUS_PK BUS_PK BUS_PL0 BUS_PL BUS_PL BUS_PL BUS_PL BUS_PL BUS_PL BUS_PL PQ PQ CS CS BUS_PortS BUS_PortS BUS_D BUS_D BUS_D BUS_D BUS_D BUS_A BUS_A BUS_A BUS_A0 BUS_A BUS_A BUS_A BUS_PortS BUS_PortS BUS_PortS Interrupt_B VccV_ VccV BUS_D BUS_D BUS_D BUS_D BUS_A0 BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_PortS0 BUS_PortS UART_RxD CS CS CS BRQ VccV_ BUS_D0 BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D0 VccV_ VccV VccV_ VccV BUS_D BUS_D BUS_D0 BUS_D BUS_D BUS_D VccV_ BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A BUS_A0 BUS_D BUS_D BUS_D BUS_D0 BUS_D BUS_D BUS_D BUS_D BUS_D BUS_D BUS_PH BUS_PG0 BUS_PR0 CS CS AS UART_TxD UART_Clock BGRNT ALE DEOP_0 CS BUS_PortS VccV Flash_enable BUS_PN BUS_PN BUS_PN BUS_PN BUS_PN BUS_PN BUS_PN BUS_PN0 BUS_PN UART_RxD UART_TxD UART_Clock Interrupt_A V V VD VSTBY JH Peripheral JH Peripheral JDHA DIN _ABC-H A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A JDHB DIN _ABC-H B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B JDHC DIN _ABC-H C C C C C C C C C C0 C C C C C C C C C C0 C C C C C C C C C C0 C C C C C C C C C C C C0 C C C C C C C C C C0 C C C C C C C C C C0 C C JDHA DIN _ABC-H A A A A A A A A A A A A A A0 A A A0 A0 A0 A0 A0 A0 A0 A0 A A A A A A0 A0 A JDHB DIN _ABC-H B B B B B B B0 B B B B B B B B B B B B B B B B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 JDHC DIN _ABC-H C C C C C C C0 C C C C C C C C C C C C C C C C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 JP UART_RxD JP UART_Clock JP UART_TxD JP0 Flash enable R k BUS_A[0:0] VccV_ VccV BUS_D[0:] VccV_ VccV VccV_ VccV BUS_D[0:] BUS_A[0:0] VccV_ VccV_ BUS_A[0:0] BUS_D[0:] VccV VccV_ RES ULB_CS ULB_RDX ULB_WRX ULB_WRX ULB_DREQ ULB_RDY ULB_WRX0 ULB_WRX ULB_CLK ULB_DACK SDA SCL BUS_PH[0:] BUS_PG[0:] BUS_PK[0:] BUS_PL[0:] DA DA0 ALARM PM0 PM PP PP PP PP PQ PQ PQ PQ BUS_PR[0:] BUS_PO[0:] BUS_PN[0:] PI CS CS CS BRQ AS UART_TxD UART_Clock CS CS BGRNT ALE DEOP_0 Interrupt_B UART_RxD CS BUS_PortS[0:] BUS_PortS[0:] BUS_PortS[0:] CS CS Flash_enable UART_RxD UART_TxD UART_Clock BUS_PN[0:] PQ PQ Interrupt_A

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