Fujitsu Microelectronics Europe Application Note FMEMCU-AN F²MC-16LX FAMILY 16-BIT MICROCONTROLLER ALL SERIES LIN-UART APPLICATION NOTE

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1 Fujitsu Microelectronics Europe Application Note FMEMCU-AN F²MC-16LX FAMILY 16-BIT MICROCONTROLLER ALL SERIES LIN-UART APPLICATION NOTE

2 Revision History Revision History Date First version Interrupt effort added Upgraded UPCL note added Issue This document contains 18 pages. AN Fujitsu Microelectronics Europe GmbH

3 Warranty and Disclaimer Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for all products delivered free of charge (eg. software include or header files, application examples, target boards, evaluation boards, engineering samples of IC s etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, all these products are intended and must only be used in an evaluation laboratory environment. 1. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer. 2. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH s entire liability and the customer s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH s sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH. 3. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated. 4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH s and its suppliers liability is restricted to intention and gross negligence. NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law, in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect Fujitsu Microelectronics Europe GmbH AN

4 Contents Contents REVISION HISTORY... 2 WARRANTY AND DISCLAIMER... 3 CONTENTS INTRODUCTION LIN-BUS Short LIN Specification LIN-MASTER LIN Master Example code C Code Assembly Code LIN-SLAVE LIN Slave Detecting LIN Synchronization Break Baud Rate Measurement Example Code C Code Assembly Code OVERVIEW ABOUT INTERRUPT EFFORT LIN-UART as LIN Master LIN-UART as LIN Slave ERROR HANDLING Bus broken Bus shortened to V CC Bus shortened to GND NOTES ON USING UART PROGRAMMABLE CLEAR (UPCL) UPCL Handling AN Fujitsu Microelectronics Europe GmbH

5 Introduction 0 Introduction This application note describes how to use the Fujitsu-LIN-UART for LIN-Master- and LIN- Slave-Functionality. This note is intended for implementing a low level hardware driver. It neither gives information of the protocol level nor uses LIN-API. Fujitsu Microelectronics Europe GmbH AN

6 Chapter 1 LIN-Bus 1 LIN-Bus SHORT SPECIFICATION 1.1 Short LIN Specification LIN uses NRZ-8N1L data format in a baud rate range from 9600 Bit/s to Bit/s. A LIN bus is a 1 master to n slaves bus. A LIN message frame consists of a header and a response like in the graphic below: LIN Message Frame Message Frame Header Response Synch Break Synch Field Ident Field Data Field(s) Data Field Checksum Field In-frame response Interbyte space Except for the Synchronization Break all Fields are simple 8N1L data, this means 1 start bit, 8 data bits (LSB first), no parity, 1 stop bit. This Break is specified as follows: SYNCH BREAK FIELD SYNCH FIELD T SYNBRK T SYNDEL SYNCH BREAK FIELD LOGICAL NAME MIN [T bit ] Nom [T bit ] SYNCH BREAK LOW PHASE dominant TSYNBRK 13 a - SYNCH BREAK DELIMITER recessive TSYNDEL 1 a - SYNCH BREAK THROSHOLD SLAVE dominant TSBRKTS 11 b MAX [T bit ] a based on master time base b based on own slave time base AN Fujitsu Microelectronics Europe GmbH

7 Chapter 1 LIN-Bus The Synchronization Field is a simple 0x55 byte (LSB first). Thus it consists of alternately 5 dominant and 5 recessive bits: SYNCH FIELD 8 T bit START STOP BIT BIT All other fields are also simple 8N1L data which contents do not need to be handled specially by the hardware. Fujitsu Microelectronics Europe GmbH AN

8 Chapter 2 LIN-Master 2 LIN-Master HOW TO USE LIN-UART AS MASTER 2.1 LIN Master The LIN master controls the whole sub bus. The master starts a LIN message frame with the LIN synchronization break. After the follow the synchronization field 0x55 and the identifier field. The length of the break can be set with the control bits LBL0, LBL1 of the Extended Status/Control Register (ESCR) of the LIN-UART. Setting LBL0 LBL1 Length* No T bit T bit T bit T bit The following graphics show the timing depending on the setting: * based on master s own time base Setting 1 Setting 2 Setting 3 Setting 4 For sending this break LIN-UART has to be in LIN-Mode (mode 3), and the LBR control bit of the Extended Communication Control Register (ECCR) has to be set to 1 (Note: Bit-access to ECCR is forbidden for MB90390 and MB90340 series, to set the break, write 0x40 to ECCR). At the next internal serial clock the break signal will be generated. At this moment normal 8N1L transmission is blocked, but the 0x55 byte for the synchronization field can be set at this time. After the break a recessive level is set to the serial output and is held for 1 bit time. Then the synchronization field (0x55) starts. The following graphic illustrates this timing: AN Fujitsu Microelectronics Europe GmbH

9 Chapter 2 LIN-Master End of Break Space Synchronization field (0x55) Start of Identifier 1 T bit Because LIN is a single wire network, the master can read back its own transmissions. Therefore enabling the reception after a LIN-Break detection (which was set by the master itself) is recommended. The master then receives the synchronization field as a normal 0x55 data and thus is synchronized to the protocol. Note, that after a complete LIN-Message the reception has to be disabled again, so that the LIN-Break can be detected without getting a framing error. 2.2 Example code The following short example shows how to generate the synch break and field. Note that n is the number of the used UART C Code void InitUARTn(void) SMRn_MD0 = 1; // Set LIN mode SMRn_MD1 = 1; SMRn_SOE = 1; // Enable output SMRn_SCKE = 1; // Set internal clock ESCRn_LBL0 = 1; // Set Break length to 16 Tbit ESCRn_LBL1 = 1; BGRn = 832; // MHz SMRn_UPCL = 1; // Set UART to initial state SCRn_TXE = 1; // Enable transmission void SetBreak(void) ECCRn = 0x40; // Generate LIN Break (LBR = 1) TDRn = 0x55; // Send Synch Field afterwards interrupt void LINBreakDetection (void) ESCRn_LBD = 0; // Clear LIN Break detection flag SCRn_RXE = 1; // enable Reception Fujitsu Microelectronics Europe GmbH AN

10 Chapter 2 LIN-Master Assembly Code #set MD0 6 #set MD1 7 #set SOE 0 #set SCKE 1 #set TXE 0 #set RXE 1 #set LBL0 4 #set LBL1 5 #set UPCL 2 #set LBD 6 ; Bit position definitions InitUARTn: SETB SMRn:MD0 ; Set LIN mode SETB SMRn:MD1 SETB SMRn:SOE ; Enable output SETB SMRn:SCKE ; Set internal clock SETB ESCRn:LBL0 ; Set Break length to 16 Tbit SETB ESCRn:LBL1 MOVW BGRn,#0340 ; MHz SETB SMRn:UPCL ; Set UART to initial state SETB SCRn:TXE ; Enable transmission RETP SetBreak: MOV ECCRn,#40 ; Generate LIN Break MOV TDRn,#55 ; Send Synch Field afterwards RETP ; Interrupt handler irqlbd: CLRB ESCRn:LBD ; Clear LIN Break detection flag SETB SCRn:RXE ; Enable Reception RETI AN Fujitsu Microelectronics Europe GmbH

11 Chapter 3 LIN-Slave 3 LIN-Slave HOW TO USE LIN-UART AS SLAVE 3.1 LIN Slave Any LIN slave is connected to the entire LIN sub bus. To react to a LIN break is stringent. The identifier field then locates a specified slave for responding. To receive the identifier correctly each slave has to adjust to the LIN master s baud rate. Therefore the slave has to measure the LIN synchronization field. The result of this measurement is used for the slave baud rate s adjustment. Note, that this measurement is only necessary, if the slave baud rate can be differ up to ±15% from the master baud rate (e. g. when RC oscillator used for slave clock). Because the LIN-UART is synchronizing its internal clock to the falling edge of the start bit, and samples each bit in the middle of the bit time, a theoretical deviation of about ±5% is tolerable (for 8N1 data format). The following illustration shows an example for 115.2k Bits/s: 3.2 Detecting LIN Synchronization Break The threshold time of the detection is 11 1/2 dominant bits: Bit time Serial Input LBD Fujitsu Microelectronics Europe GmbH AN

12 Chapter 3 LIN-Slave If LIN break detection interrupt is enabled (ESCR_LBIE = 1) and normal data reception is disabled (SCR_RXE = 0), a reception interrupt is generated when the ESCR_LBD bit is set by hardware. Note, the data reception has to be disabled to avoid a framing error (and an additional interrupt) at bit time 9, when a recessive stop bit is expected normally. The LBD flag has to be cleared by writing 0 to it after a break was detected, even if no interrupts are used. 3.3 Baud Rate Measurement If the LIN-UART has detected a LIN Break it waits for the synchronization field. Within this field an internal signal is generated from the first falling edge to the 5 th falling edge. The following graphic illustrates this: Synchronization Field LIN Bus Internal Signal to ICU 8 T bit This internal signal is connected to an Input Capture Unit (ICU) of the MCU. Please refer to the hardware manual, which ICU is connectable to which LIN-UART. The ICU has to be set to both edge detection (). At edge 1 an interrupt is initiated. The user program has to store the actual value of the ICU counter. At edge 5 the second interrupt is initiated. The actual value minus the stored divided by 8 is the new baud rate. This simple algorithm without rounding is accurate enough, so that the calculation result directly can be stored into the baud rate reload counter register. The uncertainty is about 1 LSB anyway, but always within the allowed ±5% tolerance. Note, that the clock divider of the ICU related 16 Bit I/O-Timer has to disabled, i.e. division factor 1, so that the ICU and the UART baud rate generator have the same time base. If other division factors used, the calculation has to be adapted. But be aware that the accuracy decreases with increasing division factor. If high MCU clocks and low speed LIN baud rates are used, the 16 bit of the timer counter will not be sufficient for counting 8 bits. Either division factors have to be used or the calculation has to regard counter overflows. Important Note: After updating the baud rate, the normal data reception must be enabled again to receive the next LIN message fields! This enabling has to be done within 2 bit times. AN Fujitsu Microelectronics Europe GmbH

13 Chapter 3 LIN-Slave 3.4 Example Code In the following an example code for handling the LIN message start is given. Note, that the ICU- and UART-Interrupt masks and vectors have to be initialized C Code void InitUARTn(void) // Initialize UARTn asynchronous LIN mode BGRn = 1666; // 1666 => 16MHz SMRn = 0xCE; // Reset, LIN mode SCRn_RXE = 0; // No reception SSRn_RIE = 1; //... but Reception Interrupt void InitICUj(void) // Initialize Input Capture Unit j for LIN-Synch-Field measurement ICEij_ICUSj = 1; // Connect ICUj to UARTn ICSij_EGj0 = 1; // Both edge detection ICSij_EGj1 = 1; ICSij_ICPj = 0; // Clear possible ICUj-IRQ ICU_State = 0; // State flag char LIN_State; // Flag for LIN message state void Main(void) InitIrqLevels(); // (vectors.c) set_il(7); // allow all levels EI(); // globaly enable interrupts LIN_State = 0; InitUARTn(); InitICUij(); interrupt void UARTn_IRQHandler(void) if (ESCRn_LBD) // LIN-Break detected? ICSij_ICPj = 0; // Clear possible ICUj-IRQ ICSij_ICEj = 1; // Enable ICUj-Interrupt ESCRn_LBD = 0; // Clear detection flag LIN_State = 1; // Update LIN message state Fujitsu Microelectronics Europe GmbH AN

14 Chapter 3 LIN-Slave // Handle other reception irq causes interrupt void ICUij_IRQHandler(void) int ICU_Value1, ICU_Value2; if (LIN_State == 1) // Rising edge detected? ICU_Value1 = IPCPj; LIN_State = 2; else // Falling edge (last edge) detected! ICU_Value2 = IPCPj; LIN_State = 0; // (or other states) // Calculate and set new Baud rate BGRn = (ICU_Value2 - ICU_Value1) / 8; ICSij_ICPj = 0; // Clear ICUj-IRQ // enable data reception RXE= Assembly Code #set RXE 0 ; Bit positions #set RIE 0 #set ICUSj 4 #set EGj0 2 #set EGj1 3 #set ICPj 7 #set LBD 6 InitUARTn: MOVW BRGn,#0682 ; 1666 => MHz MOV SMRn,#CE ; Reset, Lin mode CLRB SCRn:RXE ; No reception STEB SSRn:RIE ;... but reception interrupt RETP InitICUj: SETB I:ICEij:ICUSj ; Connect ICUj to UARTn SETB I:ICSij:EGj0 ; Both edge detection SETB I:ICSij:EGj1 CLRB I:ICSij:ICPj ; Clear possible ICUj-IRQ RETP Main: CALLP \InitIrqLevels ; initialize IRQ vectors and levels MOV ILM,#07 ; allow all levels OR CCR,#40 ; globally enable interrupts MOV A,#0 AN Fujitsu Microelectronics Europe GmbH

15 Chapter 3 LIN-Slave MOV LIN_State,A ; (somewhere in RAM area) CALLP \InitUARTn CALLP \InitICUj ; interrupt handler for UARTn reception irquartn: BBC ESCRn:LBD,NoBreak CLRB ICSij:ICPj ; Clear possible ICUj-IRQ SETB ICSij:ICEj ; enable ICUj-Interrupt CLRB ESCRn:LBD ; Clear detection flag MOV A,#1 MOV LIN_State,A RETI NoBreak: ; Handle other reception IRQ cause ; interrupt handler for ICUj irqicuj: MOV A,LIN_State MOVN A,#1 CMPW A BNZ FallEdge MOVW A,IPCPj ; rising edge MOVW ICU_Value1,A ; (somewhere in RAM area) INC LIN_State BRA irqend FallEdge: PUSHW RW4 ; falling edge MOVW A,IPCPj ; calculate and set new baud rate MOVW RW4,ICU_Value1 ; (ICU_new ICU_old) -> A SUBW A,RW4 LSRW A ; (A / 8) -> A LSRW A LSRW A MOVW BGRn,A ; A -> BGRn POPW INC RW4 LIN_State IrqEnd: CLRB ICSij:ICPj ; clear ICUj-IRQ RETI Fujitsu Microelectronics Europe GmbH AN

16 Chapter 4 Overview about Interrupt Effort 4 Overview about Interrupt Effort INTERRUPTS DURING LIN FRAME 4.1 LIN-UART as LIN Master The following illustration gives an overview about the interrupt effort when LIN-UART is bus master: Master Frame Slave Respond LIN-Bus Set LBR TDR=0x55 Reception-IRQ: LBD RXE = 1 Reception-IRQ: RDRF RDR= data Reception-IRQ: RDRF RDR= checksum RXE = LIN-UART as LIN Slave The following illustration gives an overview about the interrupt effort when LIN-UART is bus slave: Master Frame Slave Respond LIN-Bus Reception-IRQ: LBD ICU-IRQ No. 1 ICU-IRQ No. 2 Transmission-IRQ: TDRE TDR= Data Reception-IRQ: RDRF RDR= Header Transmission-IRQ: TDRE TDR= Checksum AN Fujitsu Microelectronics Europe GmbH

17 Chapter 5 Error Handling 5 Error Handling HOW TO HANDLE HARDWARE ERRORS 5.1 Bus broken If the LIN-Bus is broken, the master gets no response from the slaves. In this case the application will indicate a no-slave-response error. 5.2 Bus shortened to V CC If the LIN-Bus is shortened to the supply voltage, the bus is every time recessive. The application can indicate this error by the missing master-synch-break-read back or also noslave response error. 5.3 Bus shortened to GND If the LIN-Bus is shortened to the ground, the bus is every time dominant. The LIN-Master would read-back the LIN-Synch-Break, but no read-back the 0x55 byte of the Synch Field. The application can indicate this error by wrong read-back* or no-slave-response. Important note: If the serial input of the LIN-UART is connected to ground, the internal LIN- Break-detection circuit will always set the LBD (LIN Break Detection) Flag after each 11 bit times. Be careful using interrupts. Be sure to clear all reception interrupt causes in the interrupt handler routine. * since LIN Specification V 2.0 master read back is not enjoined anymore. Fujitsu Microelectronics Europe GmbH AN

18 Chapter 6 Notes on using UART Programmable Clear (UPCL) 6 Notes on using UART Programmable Clear (UPCL) HOW TO USE UPCL 6.1 UPCL Handling Generally don t set the UPCL-Bit ( Software Reset ) of the Serial Mode Register (SMR) when TXE-Bit of the Serial Control Register (SCR) is 1. AN Fujitsu Microelectronics Europe GmbH