FUJITSU APIX DEVICES APIX FIR SET UP REV 1.0 APPLICATION NOTE GRAPHICS COMPETENCE CENTER. Fujitsu Semiconductor Europe Application Note

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1 Fujitsu Semiconductor Europe Application Note an-apix-fir-setup-rev1.0 FUJITSU APIX DEVICES APIX FIR SET UP REV 1.0 APPLICATION NOTE GRAPHICS COMPETENCE CENTER

2 Revision History Revision History Date Rev AP Initial Issue This document contains 10 pages. an-apix-fir-filter-setup-rev Fujitsu Semiconductor Europe GmbH

3 Warranty and Disclaimer Warranty and Disclaimer The use of the deliverables (e.g. software, application examples, target boards, evaluation boards, starter kits, schematics, engineering samples of IC s etc.) is subject to the conditions of Fujitsu Semiconductor Europe GmbH ( FSEU ) as set out in (i) the terms of the License Agreement and/or the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. Please note that the deliverables are intended for and must only be used for reference in an evaluation laboratory environment. The software deliverables are provided on an as-is basis without charge and are subject to alterations. It is the user s obligation to fully test the software in its environment and to ensure proper functionality, qualification and compliance with component specifications. Regarding hardware deliverables, FSEU warrants that they will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer. Should a hardware deliverable turn out to be defect, FSEU s entire liability and the customer s exclusive remedy shall be, at FSEU s sole discretion, either return of the purchase price and the license fee, or replacement of the hardware deliverable or parts thereof, if the deliverable is returned to FSEU in original packing and without further defects resulting from the customer s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to FSEU, or abuse or misapplication attributable to the customer or any other third party not relating to FSEU or to unauthorised decompiling and/or reverse engineering and/or disassembling. FSEU does not warrant that the deliverables do not infringe any third party intellectual property right (IPR). In the event that the deliverables infringe a third party IPR it is the sole responsibility of the customer to obtain necessary licenses to continue the usage of the deliverable. In the event the software deliverables include the use of open source components, the provisions of the governing open source license agreement shall apply with respect to such software deliverables. To the maximum extent permitted by applicable law FSEU disclaims all other warranties, whether express or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the deliverables are not designated. To the maximum extent permitted by applicable law, FSEU s liability is restricted to intention and gross negligence. FSEU is not liable for consequential damages. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect. The contents of this document are subject to change without a prior notice, thus contact FSEU about the latest one. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect Fujitsu Semiconductor Europe GmbH an-apix-fir-filter-setup-rev1.0

4 Contents Contents REVISION HISTORY... 2 WARRANTY AND DISCLAIMER... 3 CONTENTS INTRODUCTION FIR AND DFE DESCRIPTION Transmitter FIR Filter Receiver DFE FIR FILTER SETUP Concept: Signals Transmitter FIR coefficients Receiver DFE coefficients Steps Cable length up to 5m Cable length greater than 5m APPENDIX Predefined FIR Settings an-apix-fir-filter-setup-rev Fujitsu Semiconductor Europe GmbH

5 Chapter 1 Introduction 1 Introduction For the APIX2 3Gbps mode it is not sufficient to send the data without any pre-emphasis. Frequency dependent transmission line losses (caused mainly by dielectric losses and skin effect) and reflections (caused by impedance discontinuities) cause inter-symbolinterference (ISI) which reduces the eye opening at the receiver. A finite-impulse-response (FIR) filter is implemented in the Fujitsu APIX transmitters to compensate ISI. This application note describes the setup of the APIX FIR filters in the APIX2 3Gbps mode. The setup procedure uses the EmeraldP as the APIX transmitter, and the Indigo2 as the APIX receiver. Nevertheless this application note can be used for all devices with an APIX interface. Fujitsu Semiconductor Europe GmbH an-apix-fir-filter-setup-rev1.0

6 Chapter 2 FIR and DFE Description 2 FIR and DFE Description 2.1 Transmitter FIR Filter The Fujitsu APIX2 transmitter output buffers have implemented FIR filters with 4 taps for signal preconditioning. For the 500Mbps and 1Gbps mode the data can be sent without preemphasis (d1=d2=d3=1). For the 3Gbps mode the filter has to be configured as a shift register (d1=d2=d3=0, b2=b3=0). The delay per tap is 1 unit interval (UI). Every tap can be configured with its individual drive current. Figure 1: FIR filter block diagram 2.2 Receiver DFE The APIX receiver uses a decision feedback equalizer (DFE) to compensate for transmission line impairments like frequency dependent phase and amplitude distortion. Figure 2: RX DFE block diagram an-apix-fir-filter-setup-rev Fujitsu Semiconductor Europe GmbH

7 Chapter 3 FIR Filter Setup 3 FIR Filter Setup The goal of the FIR setup is to find optimal TX FIR settings for the best signal at the RX input. FIR filter coefficients should be optimized for minimum DFE coefficients. Lab measurements have shown that scope optimized FIR coefficients (wide eye opening) do not correspond to DFE optimized FIR coefficients. 3.1 Concept: Cable length up to 5m: The drive strength of one tap is sufficient for driving signals over cable up to 5m. The other taps can be used for signal preconditioning. The FIR is configured as a shift register with 4 taps. C0 C1 C2 C3 Signal at receiver without preconditioning Ideal signal at receiver Signal at transmitter with preconditioning Tap 0: pre cursor Tap 1: nominal current Tap 2: post cursor Tap 3: corrections Figure 3: Signal preconditioning Cable length greater than 5m: The drive strength of one tap is not sufficient to achieve a good signal with high cable attenuations. Two taps are required for driving the appropriate drive current. The two remaining taps can be used for signal preconditioning. C0 C1+C2 C3 Signal at receiver without preconditioning Ideal signal at receiver Signal at transmitter with preconditioning Tap 0: pre cursor Tap 1+2: nominal current Tap 3: corrections Figure 4: Signal preconditioning Fujitsu Semiconductor Europe GmbH an-apix-fir-filter-setup-rev1.0

8 Chapter 3 FIR Filter Setup 3.2 Signals Transmitter FIR coefficients Device Module Register Description EmeraldP Triton ApCo Indigo2 Loopthrough APIX TX LINK FIR_filter_0 filter coefficients CH* FIR_filter_1 FIR input/output coefficients APIX TX LINK FIR_filter_0 filter coefficients CH* FIR_filter_1 FIR input/output coefficients APIX TX LINK FIR_filter_0 filter coefficients CH* FIR_filter_1 FIR input/output coefficients APIX2_PHY PHY_LT_CFG_CTRL_1 filter coefficients PHY_LT_CFG_CTRL_2 FIR input/output coefficients Table 1: Transmitter FIR registers Receiver DFE coefficients Device Module Address Register Description Indigo2 APIX2_PHY 0x000200EC OBS_RX_1 [4..10] obs_agc_coeff 0x000200F0 OBS_RX_2 [8..14] obs_dfe_fir_c0 0x000200F0 OBS_RX_2 [16..22] obs_dfe_fir_c1 0x000200F0 OBS_RX_2 [24.30] obs_dfe_fir_c2 or APIX2_RX 0x C DBG_STAT_4 [16..22] dbg_rx_agc_coeff 0x C DBG_STAT_4 [24..30] dbg_rx_fir_coeff_0 0x DBG_STAT_5 [0..6] dbg_rx_fir_coeff_1 0x DBG_STAT_5 [8..14] dbg_rx_fir_coeff_2 EmeraldP APIX RX 0x3A DBG_ STS_DATA _4 dbg_rx_agc_coeff Triton LINK [16..22] 0x3A DBG_ STS_DATA _4 dbg_rx_fir_coeff_0 [24..30] 0x3A DBG_ STS_DATA _5 dbg_rx_fir_coeff_1 [0..6] 0x3A DBG_ STS_DATA _5 dbg_rx_fir_coeff_2 [8..14] ApCo APIX RX 0x DBG_ STS_DATA _4 dbg_rx_agc_coeff LINK [16..22] 0x DBG_ STS_DATA _4 dbg_rx_fir_coeff_0 [24..30] 0x DBG_ STS_DATA _5 dbg_rx_fir_coeff_1 [0..6] 0x DBG_ STS_DATA _5 [8..14] dbg_rx_fir_coeff_2 Table 2: Observable receiver registers Note: MSB of fir coefficients is the sign value. an-apix-fir-filter-setup-rev Fujitsu Semiconductor Europe GmbH

9 Chapter 3 FIR Filter Setup 3.3 Steps Cable length up to 5m 1. Setup APIX TX and RX register for APIX2 3Gbps 2. Set initial FIR values a. Set b=0 (FIR input coefficients), d=0 (FIR output coefficients) b. Use predefined start values (see appendix), or c1=0x30, c0=c2=c3=0 3. Adjust c1 to get amplitude around 100mV at receiver 4. Adjust c2 to minimize DFE0 (negative value) 5. Adjust c3 to minimize other DFE coefficients 6. Adjust c0 for minor corrections 7. c1, c2, c3 may be adjusted again to adjust amplitude and DFE coefficients Cable length greater than 5m 1. Setup APIX TX and RX register for APIX2 3Gbps 2. Set initial FIR values a. Set b2=1, b3=0 (FIR input coefficients), d=0 (FIR output coefficients) b. Use predefined start values (see appendix), or c1=c2=0x30, c0=c3=0 3. Adjust c1and c2 to get amplitude around 100mV at receiver 4. Adjust c3 to minimize other DFE0 coefficient 5. Adjust c0 for minor corrections 6. c1, c2, c3 may be adjusted again to adjust amplitude and DFE coefficients Fujitsu Semiconductor Europe GmbH an-apix-fir-filter-setup-rev1.0

10 Chapter 4 Appendix 4 Appendix 4.1 Predefined FIR Settings Following values for the FIR coefficients can be used as initial values. They are tested for the link between EmeraldP and Indigo2 on Fujitsu validation boards. These settings give a receiver input amplitude of about 100mVpp. Note: values are in hex. cable length (m) c0 c1 c2 c3 b d FIR_filter_0 FIR_filter_ B x B 0x A 27 4B x424B275A 0x x x x x F 5E x415E3F56 0x B 0 1 0x6B x A 3A 7F 0 1 0x7F3A3A76 0x Table 3: Predefined FIR settings an-apix-fir-filter-setup-rev Fujitsu Semiconductor Europe GmbH