THE demand of high step-up conversion technique is gradually

Transcription

1 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY Nonisolated High Step-Up Stacked Converter Based on Boost-Integrated Isolated Converter Ki-Bum Park, Student Member, IEEE, Gun-Woo Moon, Member, IEEE, and Myung-Joong Youn, Senior Member, IEEE Abstract Toobtainahighstep-upgainwithhighefficiency in nonisolated applications, a high step-up technique based on isolated-type converters is introduced in this paper. By stacking the secondary side of an isolated converter in addition to its primary side, a high step-up conversion ratio and a distributed voltage stress can be achieved. Moreover, a careful choice of an isolated converter can provide zero-voltage switching, continuous input current, and reduced reverse recovery on diodes. Based on a conventional voltage-doubler-rectifier boost-integrated half-bridge converter, the derived converter satisfies all these features, which make it suitable for high step-up applications. The operational principle and characteristics of the proposed converter are presented, and verified experimentally with a 135-W, 24-V input, 250-V output prototype converter for a LED driver. Index Terms Boost converter, boost-integrated half bridge (BHB) converter, high step-up converter, isolated converter, zerovoltage switching (ZVS). I. INTRODUCTION THE demand of high step-up conversion technique is gradually increased according to the growth of battery-powered applications and low-voltage renewable sources such as electric vehicles, uninterrupted power supplies, photovoltaic system, and fuel cell system [4] [13]. For nonisolated applications, a classical boost converter has been a popular choice because of a simple structure and a continuous input current. When an extreme high-voltage gain is required, however, it is hard for a boost converter to achieve both high-voltage conversion ratio and high efficiency at the same time, due to the parasitic resistances, which cause a serious degradation in the step-up ratio and efficiency as the operating duty cycle is increased [1]. Moreover, as an output voltage is increased, a usage of highvoltage device is inevitable, which gives a detrimental effect on a converter s performance. That is, a high-voltage diode causes a severe reverse-recovery problem requiring an additional current snubber [2], [3] and a high-voltage switch increases a conduction loss. To achieve a high step-up gain and a low-voltage stress Manuscript received April 23, 2010; revised July 13, 2010; accepted August 6, Date of current version February 9, This work was supported by the Brain Korea 21 Project, School of Information Technology, Korea Advanced Institute of Science and Technology, Daejeon, Korea. This paper was presented in part at the International Telecommunications Energy Conference, Seoul, Korea, October 18 22, Recommended for publication by Associate Editor H. S. H. Chung. The authors are with the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon , Korea ( parky@rainbow.kaist.ac.kr; gwmoon@ee.kaist.ac.kr; mmyoun@ee. kaist.ac.kr). Digital Object Identifier /TPEL Fig. 1. Conventional high step-up techniques based on classical boost converter. (a) Cascaded structure. (b) Coupled-inductor-employed structure. (c) Multiplier-cell-employed structure. on devices, as shown in Fig. 1, various types of step-up converters have been developed based on a classical boost converter, which utilizes a cascaded structure, a coupled inductor, or a multiplier cell [4] [13]. Cascading a boost converter, shown in Fig. 1(a), is one of the easy approaches to achieve a high step-up gain, however it requires lots of components and a final output stage still suffers from a high-voltage stress [4]. A boost converter with a coupled-inductor shown in Fig. 1(b) is a favorable candidate in low-to-medium power applications for its simple structure and a low switch-voltage stress. Moreover, a leakage inductance of the coupled-inductor provides a current-snubbing effect. As the auxiliary turns of a coupled inductor are increased to raise a voltage gain further, however, an input current ripple becomes larger in return, requiring more input filter. Moreover, an auxiliary voltage clamp circuit is also required to suppress the switch-voltage spike caused by the leakage inductance of a coupled inductor [5] [10], [28], [36]. A voltage multiplier cell is also a useful approach to increase a step-up gain in collaboration with classical converter topologies, as shown in Fig. 3(c) [11] [13], [33], [35], [36]. As the output voltage is increased, however, the number of a multiplier stage is increased, requiring more capacitors and diodes. Besides, a current snubber is required to reduce the excessive di/dt on devices caused by a capacitor charging operation of the multiplier cell. With regard to utilizing isolated-type converters for high step-up applications, current-fed converters, an isolated version of a boost converter, easily offer a high step-up gain using a transformer. Moreover, it has a continuous input current and a voltage stress on rectifier is clamped to the output voltage. Therefore, it is inherently suitable for high step-up applications [14] [18], [29], [30]. At the price of utilizing a transformer, however, a voltage snubber is needed to limit the switch-voltage /$ IEEE

2 578 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011 Fig. 2. Nonisolated high step-up structure based on isolated converter. (a) Basic isolated structure. (b) Stacked structure with source as lower output. (c) Stacked structure based on boost-integrated structure with primary link capacitor as lower output. spike caused by the transformer leakage inductance, resulting in an additional loss. Besides, an auxiliary circuit is needed for below 0.5 duty operation. The recently developed currentfed converter for nonisolated applications relieves these limitations with a simple structure, though a hard switching still remains [16]. Active clamping approaches also resolve these problems and reduce switching losses, but leads to a complex structure with increased number of switches [17], [18]. In this paper, to obtain a high step-up capability with high efficiency, an alternative structure based on isolated-type converters is investigated, since some of isolated converters have been proved to be suitable for high step-up application such as current-fed converters mentioned before. To further utilize their advantages, stacking the secondary side on the top of its primary side, as shown in Fig. 2, can be considered. This structure would distribute a voltage stress on devices and contribute to a high step-up gain as well. Moreover, a careful choice of topology can inherently provide the zero-voltage switching (ZVS), continuous input current, and alleviated reverse recovery on diode. II. HIGH STEP-UP CONVERTER BASED ON BOOST-INTEGRATED ISOLATED CONVERTER The simplest approach for the stacked structure is just putting the secondary output upon the input source V S,asshownin Fig. 2(b) [19]. Some portion of the power is directly transferred to the output from the source and only the rest of the power is handled by the converter. Therefore, as the converter manages less power, more improved efficiency can be achieved. In addition, the voltage stress on the secondary can be reduced, since it only has to provide the difference between the output voltage V O and the input voltage V S. When an extremely high step-up gain is required, however, the effect of voltage stress distribution becomes ignorable, since most of the voltage stress would be impressed on the secondary side. Besides, as the input source is directly connected to the output, the input noise can pass through the output, i.e., it has very sensitive audio susceptibility. To further distribute the voltage stress between primary and secondary sides while relieving the input noise problem, a boostintegrated isolated converter, where a boost converter is topologically integrated in the primary side [20] [23], can be converted to the stacked structure, as shown in Fig. 2(c). Since a general boost-integrated structure possesses a link capacitor in the primary side, it can be served as a lower output voltage V Po.This lower output voltage is boosted from the input source, therefore, less upper output voltage V So is required and a secondary side burden can be reduced accordingly. That is, more fair distributed voltage stresses can be achieved between primary and secondary sides compared with the structure shown in Fig. 2(b). Till now, various types of boost-integrated structure have been developed [20] [23]. Among them, as a basic topology for the stacked structure, the voltage-doubler-rectifier boost-integrated half-bridge (VDRBHB) converter shown in Fig. 3(a) is one of the fine candidates [22]. Combining the boost-integrated half-bridge (BHB) converter [20], [21] with the voltage-doubler rectifier (VDR) in the secondary side [31] [36], this converter has ZVS capability, continuous input current, and low voltage stress on switch and diode, and all these features make it inherently suitable for high step-up applications with high efficiency. Therefore, it is converted to the stacked structure in this paper. The proposed nonisolated high step-up converter obtained from the VDRBHB converter with some modification is presented in Fig. 3(b). In the primary side, a link capacitor C link and a half-bridge balancing capacitor C R are repositioned to the output side to serve as the output capacitors C Po1 and C Po2. Then, the secondary VDR is stacked in addition to the primary BHB module to obtain an additional step-up gain. In addition, to simplify the circuit, the boost inductor L B and the transformer can be integrated as shown in Fig. 3(c) since the shapes of the applied voltages on the boost inductor and the transformer are the same [23] [26]. As a result, the magnetizing inductor of the transformer L M can be served as a boost inductor. At the price of magnetic integration, however, an input current ripple becomes larger, since both the boost-inductor current and the transformer current come from the input terminal. The fundamental operations and characteristics of circuits shown in Fig. 3(b) and (c) are the same, except for an input current. Therefore, the following analysis of the proposed converter is based on the circuit in Fig. 3(b). III. OPERATION PRINCIPLES A. Operational Mode Analysis The basic operation of a proposed converter shown in Fig. 2(b) is a combined operation between a boost converter and an asymmetric-controlled half-bridge converter employing VDR. With a switching action of the main switch Q M, a boosted voltage is generated as the primary output voltage V L, i.e., V Po1 + V Po2. Then, regarding V Po1 and V Po2 as a source, a power is delivered to the secondary side through the transformer by a switching action of Q M and Q A. Here, a complementary switching enables ZVS and the transformer leakage inductance L lkg functions as a current-driving impedance in the half-bridge converter. The key waveforms and topological states of a proposed converter are presented in Figs. 4 and 5, respectively. A magnetizing

3 PARK et al.: NONISOLATED HIGH STEP-UP STACKED CONVERTER BASED ON BOOST-INTEGRATED ISOLATED CONVERTER 579 Fig. 3. Nonisolated high step-up converter based on VDRBHB converter. (a) Conventional VDRBHB converter. (b) Stacked structure. (c) Stacked structure with integrated magnetics. current of the transformer has zero offset in the circuit of Fig. 3(b), therefore, it is neglected to simplify the analysis. One switching period is subdivided into six modes and the detailed operation is presented as follows. Mode 1 [t 0 t 1 ]: Q M conducts. The input voltage V S is applied to the boost indictor L B, thus I Lb is increased linearly with a boosting operation. At the same time, the primary lower output voltage V Po1 is applied to the transformer primary side, i.e., V ab. Therefore, the powering path is formed to the secondary side through the secondary lower side diode D s1. The difference between V Po1 and the reflected secondary output voltage nv So1 is applied to L lkg.thel lkg acts as a current-driving impedance and the transformer primary current I lkg is increased linearly. Both I Lb and I lkg flow through Q M. Mode 2 [t 1 t 2 ]: Q M is turned off at t 1. Since D s1 is still conducting, V pri is fixed by nv So1, and L lkg is resonated with the switch output capacitances C M and C A. Therefore, C M is charged by I lkg as well as I Lb while C A is discharged. I lkg and V Q M can be expressed as follows: I lkg (t) =(I lkg (t 1 )+I Lb (t 1 )) cos (ω 0 (t t 1 )) I Lb (t 1 ) ω 0 = 1 Llkg (C M + C A ) V Q M (t) =(I Lb (t 1 )+I lkg (t 1 )) (1) Llkg C M + C A sin (ω 0 (t t 1 )). (2) Fig. 4. Key waveforms of proposed converter. Mode 3 [t 2 t 3 ]: At t 2, V Q M is clamped to V Po1 + V Po2 and V Q A reaches zero. Both I Lb and I lkg flow through the antiparallel diode of Q A, i.e., d A. To achieve ZVS, Q A should be turned on while d A conducts. Since V pri is still fixed to nv So1,the

4 580 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011 Fig. 5. Topological states for mode analysis. (a) Mode 1 [t 0 t 1 ]. (b) Mode 2 [t 1 t 2 ]. (c) Mode 3 [t 2 t 3 ]. (d) Mode 4 [t 3 t 4 ]. (e) Mode 5 [t 4 t 5 ]. (f) Mode 6 [t 5 t 6 ]. entire voltage V Po2 + nv So1 is impressed on L lkg. Therefore, I lkg is decreased linearly, which leads I Ds1 to be decreased linearly. Mode 4 [t 3 t 4 ]: At t 3, I Ds1 reaches zero. Q A is conducting and the primary upper output voltage V Po2 is applied to V ab. The powering path is formed to the secondary side through the secondary upper side diode D s2. The difference between V Po2 and the reflected secondary output voltage nv So2 is applied to L lkg, therefore, I lkg is decreased linearly. V S V Po1 V Po2 is applied to L B and I Lb is decreased linearly and flows to the output side through Q A in reverse direction. The difference between I lkg and I Lb flows through Q A. Mode 5 [t 4 t 5 ]: Q A is turned off at t 4. Since D s2 is still conducting, V pri is fixed to nv So2, and L lkg is resonated with the switch output capacitances C M and C A. Therefore, C A is charged by the difference between I lkg and I Lb. I lkg and V Q A can be expressed as follows: I lkg (t) = ( I lkg (t 4 ) I Lb (t 4 )) cos (ω 0 (t t 4 )) I Lb (t 4 ) (3) L lkg V Q A (t) =( I lkg (t 4 ) I Lb (t 4 )+) (C M + C A ) sin (ω 0 (t t 4 )). (4) Mode 6 [t 5 t 6 ]: At t 5, V Q A is clamped to V Po1 + V Po2 and V Q M reaches zero. The difference between I Lb and I lkg flows through the antiparallel diode of Q M, i.e., d M. To achieve ZVS, Q M should be turned on while d M conducts. Since V pri is still fixed to nv So2, the entire voltage V Po1 + nv So2 is impressed on L lkg. Therefore, I lkg is increased and I Ds2 is decreased linearly. B. Input Output Voltage Conversion Ratio The proposed converter consists of a boost converter and a half-bridge converter with VDR, and each converter operates individually except for the common shared parts, i.e., Q M and Q A. Thus, in view of a boost converter, its voltage conversion ratio V L /V S is 1/(1 D). For the sake of analysis on the half-bridge converter with VDR, Fig. 6 shows the simplified current waveforms neglecting the switching transitions and assuming that I Lb is constant. Since the each average current of I Ds1 and I Ds2 is the same as I o, this relation can be expressed as (5). Then, using the voltage-second balance across the transformer and (5), the voltage conversion ratio of the half-bridge stage, V So /V L, can be expressed as (6). Both V L /V S and V So /V L are presented in Fig. 7(a) with a function of the damping factor Q. The shape of V So /V L is symmetric and Q provides a damping effect to the gain curve. Therefore, as Q is increased, the voltage gain is reduced and the dead zone, where the gain is zero, is increased. The total output voltage conversion ratio V O /V S can be expressed as (7) and is shown in Fig. 7(b). Normally this gain curve follows (7) except for the case when V So /V L is zero. In this case, both D s1 and D s2 conduct simultaneously, i.e., the secondary side does not affect the total gain, and V O /V S follow the boost conversion ratio V L /V S. Provided that Q is small enough, V O /V S can be

5 PARK et al.: NONISOLATED HIGH STEP-UP STACKED CONVERTER BASED ON BOOST-INTEGRATED ISOLATED CONVERTER 581 Fig. 6. Simplified current waveforms according to n. (a)n > 1 (ZVS condition of Q M ). (b) n<1 (Hard switching of Q M ). Fig. 7. Input output voltage conversion ratio (n =1). (a) V L /V S and V So /V L. (b) V O /V S. approximated as (1 + n)/(1 D). When D becomes zero, i.e., the converter does not operate, all series connected diodes d A, D s1, and D s2 conduct, and V O follows V S such as in a classical boost converter I o = V L + V So R O = (V Po1 V So1 /n) D 2 T S 2nL lkg = (V Po2 V So2 /n)(1 D) 2 T S 2nL lkg (5) V So = n 1 nq ( (1/D 2 )+1/(1 D) 2) V L 1+n 2 Q ((1/D 2 )+1/(1 D) 2 ) Q = 2L lkg R O T S (6) V O = 1 ( V So 1+ V ) L 1+n (Q 0). V S 1 D V L V So 1 D (7) C. Voltage and Current Stress on Devices With the assumption that Q =0, the primary output capacitor voltages V Po1 and V Po2 can be approximated to V S and D V S /(1 D), respectively. Fig. 8 shows the output capacitor voltage stress normalized by V S. In the secondary, V So1 and V So2 can accordingly be obtained as nv S and nd V S /(1 D), respectively. That is, the capacitor voltages of upper module, V So1 and V So2,are n time higher than those of lower module. Fig. 8. Voltage stress on lower output capacitors. The voltage stresses on primary switches and secondary diodes are clamped to V L and V So, respectively. From (8) and (9), the switch peak current stress normalized by I O according to a variation of n can be illustrated as shown in Fig. 9. Here, n = 0 represents a classical boost converter, where the secondary side is ignored and Q A only acts as a diode. As n is increased, both current stresses of switches are increased. The current stress of Q M consists of I Lb and ni Ds1, where I Lb is increased and I Ds1 is decreased according to an increase in the duty cycle. The current stress of Q A is the difference between I Lb and ni Ds2, therefore, it can be a negative value if n is less than 1. Fig. 10 shows the switch current stress according to a

6 582 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011 Fig. 9. Switch peak current stress normalized by I o according to variation of n. (a) Peak current stress of Q M. (b) Peak current stress of Q A. Fig. 10. Switch peak current stress normalized by I o according to variation of M. (a) Peak current stress of Q M. (b) Peak current stress of Q A. are expressed as in (10) and (11), and which also represent the reflected secondary diode currents I Ds1 and I Ds2 to the primary side. When D =0.5, I lkgp and I lkgn are equal, and as the duty cycle is increased, the overall current stresses are decreased I lkgp = ni Ds1p = 2n D I 2(M (1 D) 1) O = I O (10) D I lkgn = ni Ds2p = 2n ( 1 D I O =2 M 1 ) I O. (11) 1 D Fig. 11. Transformer primary current stress normalized by I o according to variation of M. variation of the input output voltage conversion ratio M. AsM is increased, the current stress is increased. In the same M, an increase in the duty cycle, which implies a decrease in n, reduces a current stress on switches I Q M p = ( 1+n 1 D + 2n D ) I O = ( M + ) 2M (1 D) 2 I O D (8) I Q A p = n 1 ( ) M (1 D) 2 1 D I O = I O. (9) 1 D Fig. 11 presents peak the current stress on the transformer according to a function of M. I lkgp and I lkgn denote positive peak value and negative peak value of the transformer currents, which D. ZVS Condition As explained in mode 2 of Section II, at first, ZVS of Q A is achieved by the energy stored in L lkg. Unless this energy for ZVS is sufficient, the boost inductor current I Lb, which can be considered as a current source, would discharge the rest of the charge in C A. Therefore, ZVS of Q A can always be achieved if the dead time is sufficient. The minimum dead time for ensuring ZVS can be expressed as (12). In a similar way, ZVS of Q M is achieved by the energy stored in L lkg with the peak switch current of Q A showninfig.9(b). The ZVS condition can be expressed as (13). Since I QA I Q A (t 4 ) can be negative as shown in Fig. 6(b), which causes a hard-switching if n is less than 1, n should be selected at least higher than 1 to perform ZVS. Fig. 12 shows the simplified current waveform considering the current ripples of I Lb and the transformer magnetizing current I Lm. In this case, I Q A (t 4 ) can be expressed as (14) and it is higher than that shown in Fig. 6(a) owing to the current ripple of I Lb and I Lm. Therefore, I Q A (t 4 )

7 PARK et al.: NONISOLATED HIGH STEP-UP STACKED CONVERTER BASED ON BOOST-INTEGRATED ISOLATED CONVERTER 583 Fig. 12. I Lb. Simplified current waveform considering current ripples of I Lm and Fig. 14. RMS current of main switch Q M. Fig. 13. LED driver with a large number of LEDs in one string. is increased as L b and the transformer magnetizing inductance L m is reduced. That is, a larger ripple of I Lb and I Lm is of benefit to ZVS of Q A T d V L (C M + C A ) I Lb (t 1 ) V S (C M + C A ) (1 + n)i o (12) (C M + C A ) V 2 L L lkg I QA (t 4 ) 2 (13) I Q A (t 4 )=I lkg (t 4 ) I Lb (t 4 )= n 1 1 D I O + ΔI Lb +ΔI Lm 2 = n 1 1 D I O + V S DT S 2 ( 1 L b + 1 L m IV. EXPERIMENT ). (14) A. Design Guideline To verify the proposed converter, a prototype for an LED drive application [27], where a large number of LEDs are connected in series and in a string, as shown in Fig. 13, is implemented. The high step-up converter boosts an input voltage to a high output voltage, and following current regulators control each current of LED string. To illustrate the design procedure, the high stepup converter has following specification; input voltage V S = 24 V, output voltage V O = V, rated output current I o =0.54 A, and switching frequency F S =85kHz. The output voltage and the output current are varied according to the number of LEDs in one string and the number of strings, respectively. The following design is focused on 250-V 0.54-A output and Fig. 15. Transformer turn ratio n according to variation of M. the required input output voltage gain M is 10.4 (=250/[24]), i.e., about 10. In the converter design, a selection of the main switch Q M, which is rather burdened by the sum of the large input current I Lb and the transformer current I lkg, is primarily considered in view of the cost and the efficiency. As presented in (15) and Fig. 14, for the same M, an rms value of switch current is slowly decreased as a duty cycle is increased. That is, a switch conduction loss would be rarely affected by the operating duty cycle. On the other hand, a switch-voltage stress, V S /(1 D), is decreased as the duty cycle is decreased, which lead to a use of lower voltage switch having a smaller on-resistance. However, a smaller duty cycle results in a larger turn ratio n from (7), which increases a handling power of the secondary side. As shown in Fig. 11, consequently, a smaller duty cycle increases a peak current stress on the transformer and would increase the transformer conduction loss accordingly. Therefore, a duty cycle should be selected to accommodate a low-voltage stress as much as possible while not to increase the transformer conduction loss too much. To utilize a 100-V switch with a sufficient margin, the nominal duty cycle D nom is selected as about 0.5. (n ) 2 + D I Q M rms I O + n2 1 D 3 = I O (M 1) 2 (M DM 1)2 +. (15) 3

8 584 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011 TABLE I EXPERIMENTAL PARAMETERS Considering D nom to be 0.5, from (7) and Fig. 15, the required transformer turn ratio n is determined as 4.2 accordingly. Assuming R O = 462, F S =85kHz, and L lkg =3uH, the damping factor Q in (6) is so small, merely around 0.001, that its damping effect on the output voltage would be negligible. With the selected n and D nom, from (6) and (7), V L and V So are designed to be about 50 V and 200 V, respectively. Thereby, the usage of a 100-V switch is allowed for the primary side and 300-V diodes for the secondary VDR. The design of the boost inductor and the transformer is the same as those of conventional ones. Considering a current ripple to be 25% of the input current 5.7 A, L B is designed as 120 uh. From the fabricated transformer, the transformer magnetizing inductance L m is obtained as 230 uh. In LED driver applications, because of its constant current load characteristic, the converter is usually operated in a fullload condition. With previously obtained parameter from (14), I QA (t 4 ) in a full-load condition would be 4.3 A. Provided IRF540 is used for switch, of which C OSS is about 100 pf at a 50-V drain-sours voltage, the required L lkg for ZVS of Q M should be larger than 2.6 uh from (13). B. Experimental Results To verify the proposed stacked converter, a prototype is implemented. The specification and design parameters obtained from the design guideline are presented in Table I. Figs. 16 and 17 show the experimental waveforms at a fullload condition with V O = 250 V and V O = 150 V, respectively. They well coincide with the theoretical analysis except for some voltage spikes across switches caused by parasitic inductance. In case of V O = 250 V, the operating duty cycle is slightly larger than 0.5. The voltage stresses on both switches are around 50 V, which allows utilizing 100-V switches, and the voltage stress on the secondary diode is well clamped to the upper output voltage 200 V allowing the use of 300-V diodes. As can be seen in the waveforms of I Q A and V Q A,theZVSofQ A is well achieved. Although, the turn-off current of I Q A is small, about 4 A, the ZVS of Q M is also achieved with 2.8 uh of L lkg which is designed in the Section IV-A. The ZVS of Q M is verified by the small negative current flowing through Q M. In case of V O = 150 V, because of a reduced step-up gain, the operating duty cycle is reduced to about 0.35 and the voltage stresses on most devices are decreased compared to those of V O = 250 V case. The voltage stress on switch is under 50 V and the voltage stress on secondary diode is also well clamped to about 110 V. However, the reduced duty cycle causes an imbalance of I lkg in return, which leads to an increase in the current stress of I Q M. The ZVS of both Q M and Q A are also achieved as verified by the negative current flowing ahead. In the experiment of a conventional boost converter, where alow-performance high-voltage switch is used inevitably, the output voltage could not be obtained over 180 V. That is, the switch becomes thermally unstable as the output voltage is increased with the same boost inductor, a switch FQP17N40 (R ds =0.21 Ω, V DSS = 400 V), and a diode STTH2003. For the comparison with the other high step-up converter, a prototype of the circuit presented in [7] is implemented as shown in Fig. 18(a) with the following design parameters; a switching frequency = 85 khz, a boost inductance L B =33uH(core: EER3435), a coupling turn ratio n =7, a leakage inductance L lkg =25uH, a switch Q: IRF540 (R ds =49 mω, V DSS = 100 V), a clamp diode D C : 16CTQ100 (V F =0.58 V, V RRM = 100 V), an output diode D O : ISL9K1560 G3 (V F =1.8 V, V RRM = 600 V), a snubber capacitor C sn =22nF, a snubber resistor R sn =20kΩ. Fig. 18(b) and (c) show the experimental waveforms at a full-load condition with V S = 250 V and V S = 150 V, respectively. The input current I in, which comprises the switch current I Q and the clamp diode current I D C as well, is discontinuous by the coupling effect of L B. The switchvoltage stress is about 50 V, allowing the usage of a 100-V switch. However, the voltage stress on the output diode, V D O, is over 400 V in spite of utilizing an resistor-capacitor-diode

9 PARK et al.: NONISOLATED HIGH STEP-UP STACKED CONVERTER BASED ON BOOST-INTEGRATED ISOLATED CONVERTER 585 Fig. 16. Experimental waveforms at V O = 250 V. Fig. 17. Experimental waveforms at V O = 150 V.

10 586 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011 Fig. 18. Experiment of high step-up circuit in [7]. (a) Circuit diagram. (b) Experimental waveforms at V O = 250 V. (c) Experimental waveforms at V O = 150 V. converter is higher over 1% at the full-load condition owing to the full ZVS operation and the usage of low-voltage highperformance devices. In addition, the proposed converter does not require an additional input filter because of its inherent continuous input current by the boost inductor. If the circuit in [7] adopts an additional input filter to smooth the input current, the efficiency would be slightly decreased further in return. Fig. 19. Measured efficiency. (RCD)-snubber. The use of a 600-V diode is inevitable and it causes a reverse recovery, which can be observed from I D O, and the reflected current to the primary side of the coupled-inductor is rather high as can be seen in I in. Fig. 19 presents the comparative efficiency curves for the proposed converter and the circuit in [7] with respect to V O = 250 V and V O = 150 V. The overall efficiency of the proposed converter with V O = 250 V is over 93%. Since the design for the proposed converter is focused on the V O = 250 V case, the efficiency of V O = 150 V gets lower due to the reduced duty cycle which causes an asymmetric in I lkg and increases a conduction loss. In case of the circuit in [7], the efficiency with V O = 250 V is below 92% at the full-load condition due to a large conduction loss, a snubber loss, and a reverse-recoveryrelated loss. Regarding the case of V O = 150 V, however, it shows a rather higher efficiency compared with the proposed converter for a reduced conduction loss. It is noted that, at the design point of V O = 250 V, the efficiency of the proposed V. CONCLUSION An alternative structure to obtain a high step-up gain for nonisolated applications is introduced in this paper. Based on the conventional VDRBHB converter, the secondary side is stacked in addition to the primary side to further increase the step-up gain and distribute the voltage stress to devices. Moreover, the derived stacked converter shows a continuous input current and a ZVS capability by inherent characteristics of VDRBHB converter. It is worth noting that the introduced stacked structure can be extended to other isolated-type converters and, particularly, a boost-integrated structure is expected to shows a good performance for high step-up applications. REFERENCES [1] R. W. Erickson and D. Masksimovic, Fundamentals of Power Electronics. 2nd Ed., Norwell, MA: Kluwer, pp [2] K. M. Smith and K. M. Smedley, Properties and synthesis of passive lossless soft-switching PWM converters, IEEE Trans. Power Electron., vol. 14, no. 5, pp , Sep [3] M. M. Jovanovic and Y. Jang, State-of-the-art, single-phase, active powerfactor-correction technique for high-power applications An overview, IEEE Trans. Power Electron., vol. 52, no. 3, pp , Jun [4] F. L. Luo and H. Ye, Positive output cascade boost converters, in Proc. Inst. Elect. Eng., (IEE) Electr. Power Appl., Sep. 2004, vol. 151, no. 5, pp [5] T.-F. Wu, Y.-S. Lai, J.-C. Hung, and Y.-M. Chen, Boost converter with coupled inductors and buck-boost type of active clamp, IEEE Trans. Ind. Electron., vol. 55, no. 1, pp , Jan

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Kim, High boost converter using voltage multiplier, in Proc. IEEE Ind, Electron. Conf. (IECON), 2005, pp Ki-Bum Park (S 07) was born in Korea, in He received the B. S., M. S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2003, 2005, and 2010, respectively. He is currently a Postdoctoral researcher at KAIST, Daejeon. His current research interests include dc dc converter and power-factor correction ac dc converter for server power systems and display power systems, and display driver circuit. Dr. Park received the Best Paper Award from the International Telecommunications Energy Conference in Gun-Woo Moon (S 92 M 01) received the M. S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1992 and 1996, respectively. He is currently a Professor at the Department of Electrical Engineering, KAIST, Daejeon. His research interests include modeling, design and control of power converters, soft-switching power converters, resonant inverters, distributed power systems, power-factor correction, electric drive systems, driver circuits of plasma display panels, and flexible ac transmission systems. Dr. Moon is a member of the Korean Institute of Power Electronics, Korean Institute of Electrical Engineers (KIEE), Korea Institute of Telematics and Electronics (KITE), Korea Institute of Illumination Electronics and Industrial Equipment, and Society for Information Display (SID). Myung-Joong Youn (S 74 M 78 SM 98) was born in Seoul, Korea, in He received the B. S. degree from Seoul National University, Seoul, Korea in 1970, and the M. S. and Ph.D. degrees in electrical engineering from the University of Missouri, Columbia, MO, in 1974 and 1978, respectively. In 1978, he joined the Air-Craft Equipment Division, General Electric Company, Erie, PA, where he was an individual contributor on Aerospace Electrical System Engineering. Since 1983, he has been a Professor at the Korea Advanced Institute of Science and Technology, Daejeon, Korea. His research activities are in the field of power electronics and control, which include the drive systems, rotating electrical machine design, and high-performance switching regulators. Dr. Youn is a member of the Institution of Electrical Engineers, U. K., Korean Institute of Power Electronics, Korean Institute of Electrical Engineers, and Korea Institute of Telematics and Electronics.