GENERATION of quadrature signals is essential for

Transcription

1 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 59, NO. 9, SEPTEMBER An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation Haitao Tong, Shanfeng Cheng, Yung-Chung Lo, Aydın İlker Karşılayan, Member, IEEE, and Jose Silva-Martinez, Fellow, IEEE Abstract A phase shift technique using capacitive source degeneration (CSD) is presented for LC quadrature voltage-controlled oscillators (QVCO), capacitively degenerated differential pairs are used to couple the LC tanks to implement a phase-shifted transconductance and negative input resistance to compensate resonator losses, and to minimize the flicker noise contributions. The CSD technique not only introduces excess phase shift to eliminate undesired bi-modal oscillation, but inherently provides a large coupling ratio to improve quadrature phase accuracy. Compared to existing phase-shift LC-QVCOs, the proposed CSD-QVCO presents excellent phase accuracy and power efficiency. A prototype of the QVCO was fabricated in TSMC m CMOS technology. The measured phase noise is 120 dbc/hz at 3-MHz offset from 5-GHz carrier, with a power consumption of 6.4 mw from a 1.2-V supply. Index Terms Bi-modal oscillation, phase noise, phase shift, quadrature VCO, voltage-controlled oscillator (VCO). I. INTRODUCTION GENERATION of quadrature signals is essential for the implementation of many modern communication systems. Quadrature signals, for example, are required for up/down-conversion in zero-if architectures [1], which is a suitable solution for full integration of wireless transceivers on a single chip. Another example is found in half-rate clock and data recovery (CDR) systems [2], quadrature signals slow down the operating speed of the most critical sampling blocks. Typical quadrature signal generation approaches include frequency divider [3], RC polyphase filter [4], quadrature voltage-controlled oscillator (QVCO) with RC load [5] or LC resonator [6] [18]. Among them, LC-QVCO is a popular choice due to its low phase noise and low power consumption. LC-QVCOs generally consist of two identical LC oscillators, being coupled through various ways. First, passive components are widely utilized for coupling the super-harmonic signals of oscillators without generating considerable noise [6] [8]. The Manuscript received June 01, 2011; revised October 11, 2011; accepted December 21, Date of publication February 14, 2012; date of current version August 24, This paper was recommended by Associate Editor Y. Sun. H. Tong is with Broadcom Corporation, Irvine, CA USA. S. Cheng was with NXP Semiconductor, Austin, TX USA. Y.-C. Lo, A. İ. Karşılayan and J. Silva-Martinez are with the Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX USA ( karsilay@ece.tamu.edu; jsilva@ece.tamu.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCSI Fig. 1. Conventional QVCO. coupling via passive components usually features a weak coupling strength due to signal amplitude attenuation at high frequency. In order to enhance the coupling, transformer-based [6] and LC resonator-based [7] coupling networks have been proposed, both of which, however, have significant area penalty. A second approach is to directly couple the VCO outputs through coupling transistors. A conventional implementation of such LC-QVCOs is shown in Fig.1.Aseriousissueoftheconventional LC-QVCO is the bi-modal oscillation, which means that the oscillator can have two stable oscillation frequencies for the same bias condition. The solution reported in [9] relies on the asymmetrical frequency response of the resonator to obtain a unique oscillation frequency. However, Li et al. [10] observed bi-modal oscillations during measurements, and proposedtoaddsomephase shift in the coupling pairs to solve the oscillation ambiguity. Other phase shift LC-QVCO structures have been reported in the existing literature [11] [14]. However, those solutions suffer from various problems, such as poor phase noise and limited voltage headroom. To address these issues, a capacitive source degeneration LC-QVCO (CSD-QVCO) is proposed in this work. The usage of capacitive source degeneration differential pairs not only delivers necessary phase shift to improve the phase noise, but also provides a phase-shifted coupling transconductance and negative input resistance to sustain the oscillation. The CSD-QVCO has better phase accuracy due to its inherent large transconductance coupling ratio. An additional benefit ofthe proposed architecture is that the low-frequency noise present at the gates of the transistors implementing the negative resistor (due to noisy LO-signals and transistors) is inherently rejected since the capacitive source degeneration presents a high-pass like noise transfer function. The paper is organized as follows. Section II reviews the bi-modal phenomenon. Section III discusses the advantages and drawbacks of the existing phase /$ IEEE

2 1872 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 59, NO. 9, SEPTEMBER 2012 Fig. 3. Phasor diagram of conventional QVCO. (a) Stage-I leads Stage-Q by 90.(b)Stage-I tags Stage-Q by 90. Fig. 2. Small signal model of QVCO. shift LC-QVCOs. Section IV presents the proposed phase shift LC-QVCO, explains the phase shift mechanism, and performs analysis of startup condition, oscillation frequency, phase noise and phase error. Measurement results are shown in Section V, while the conclusions are drawn in Section VI. II. BI-MODAL OSCILLATION Fig. 2 shows a single-ended linear model for a general QVCO, represents the transconductance of the coupling pair and represents the transconductance of the positive feedback pair. The output currents and are defined as follows: parallel network is the equivalent circuit for the resonator. Bi-modal oscillation can be explained through phasor diagrams as shown in Fig. 3. The currents flowing out of the node in Fig. 2 are indicated as,,,and.while is always in phase with, is always 180 away from. can have either or phase shift, depending on whether the oscillation frequency is smaller or larger than the tank s resonance frequency. For conventional QVCO, has either or phase shift, depending on the oscillation mode. Since the sum of those four currents has to be zero, has to be equal to, leading to.fig.3(a) shows that when Stage-I leads Stage-Q by 90, is. As a result, has to be, indicating that the oscillation frequency is higher than the resonance frequency. Fig. 3(b) shows the case when Stage-I lags Stage-Q by 90, is 90 and is 90, indicating the oscillation frequency is lower than the resonance frequency. Therefore, for the same conventional QVCO, two oscillation modes are possible. In [9], it is argued that in practice, a unique oscillation frequency is assured as the practical resonator has asymmetric magnitude response across its resonance frequency. It is also shown that for the same phase response of the resonator, the magnitude at one mode is 30% larger than the other. This asymmetry of the resonator magnitude response (1) (2) Fig. 4. Tank impedance of the implemented LC resonator with 45 phase shift across the whole tuning range. is large enough to overcome the bimodal oscillation under process-voltage-temperature (PVT) variations. However, we investigate the frequency characteristics of the resonator used in our implementation. Fig. 4 shows the simulation results. Notice that along the whole control voltage range, the tank impedance magnitude at the frequency with 45 phase shift is always larger than the one with 45 phase shift. However, the magnitude difference is marginal, which is no more than 6%. The small magnitude asymmetry could be attributed to the implementation of inductor using thick top metal layer currently available in many processes, which helps to increase inductor quality factor and self-resonance frequency. As a result, such a resonator in a conventional QVCO architecture may easily lead to the problem of bi-modal oscillation. In [9], the authors proposed adding some phase shift at cell,, so that the QVCO will favor only one mode. This approach is illustrated with the phasor diagram shown in Fig. 5. Assuming a positive within the range, Fig. 5(a) shows that if, the only chance for the sum of all currents to be zero is if Stage-I leads Stage-Q by 90, while the oscillation frequency is higher than the resonance frequency. Similarly, Fig. 5(b) shows that if,the only chance for the sum of all currents to be zero is if Stage-I lags Stage-Q by 90, while the oscillation frequency is lower than the resonance frequency. Though two possible oscillations seem to exist in the QVCO with phase shift according to the phasor diagram, in reality, the oscillation in Fig. 5(b) prevails over that in Fig. 5(a) because the oscillation in Fig. 5(b)

3 TONG et al.: LC QUADRATURE VCO USING CSD COUPLING TO ELIMINATE BI-MODAL OSCILLATION 1873 Fig. 5. Phasor diagram of QVCO with phase shift. (a) Stage-I leads Stage-Q by 90.(b)Stage-I tags Stage-Q by 90. Fig. 7. Phase-shift QVCO proposed in [14]. Fig. 6. Bi-modal suppression QVCO discussed in [10]. Fig. 8. Phase-shift QVCO reported in [11]. has larger tank impedance and loop gain [9], [12]. Therefore, many phase shift techniques have been reported to solve the bimodal oscillation of the QVCOs [10] [14]. The additional benefit of the phase shift approach is that the phase noise of the QVCO is reduced because decreases the required phase shift from the resonator to meet Barkhausen s phase criteria. With a smaller,the oscillation frequency is closer to the resonant frequency and the effective quality factor of the resonator is higher, so the tank has better noise filtering to improve the phase noise of the QVCO. When, can be approximated as [11] Fig. 9. Proposed CSD-QVCO. is the quality factor of the resonator. (3) Tang et al. [11] inserted phase-shifters between the oscillator stages, as shown in Fig. 8. However, similar to the approach in [14], of the transistor inside the phase-shifter degrades resonator. III. EXISTING PHASE SHIFT LC-VCOS In [10], it is suggested to replace the regular differential coupling pair with a cascode topology. In this way, additional phase shift is generated at the source node of the common-gate transistor, biased by in Fig. 6. The phase shift is normally limited and may not be sufficient to suppress the bi-modal oscillation, because this source node only provides a pole at high frequency. Also the usage of cascode configuration decreases voltage headroom, making the topology unsuitable for low-voltage applications. There are other journal publications discussing other phase shifting techniques. Although the main target is to improve the phase noise performance, it helps to suppress the bi-modal oscillation as well. For instance, Valla et al. [14] adds a resistor at the gate of each coupling transistor to realize an low-pass network with the gate capacitance, as shown in Fig. 7. However, the phase noise performance would be degraded because of the extra noise added by the resistor. IV. PROPOSED CSD-QVCO A. Structure of the Proposed CSD-QVCO A capacitive source degeneration QVCO (CSD-QVCO), shown in Fig. 9, is proposed to suppress bi-modal oscillation. The capacitive source degeneration provides the required amount of phase shift in the transconductance of the coupling pair, which can be derived as follows. At high frequencies, the overall transconductance,,of the capacitive degeneration differential pair is approximated as is twice the source degeneration capacitance between the two source nodes plus the AC-grounded parasitic capacitors at the source of, is the gate-to-source capacitance and is the transconductance of the input transistor. (4)

4 1874 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 59, NO. 9, SEPTEMBER 2012 Fig. 10. Phasor diagram of the proposed CSD-QVCO. Fig. 10 shows the phasor diagram of the proposed CSD-QVCO, is defined as the phase shift between the input voltage of and its output current, and can be calculated as Fig. 11. Small signal model of the proposed CSD-QVCO. is the input transistor s transition frequency. According to (5), the phase shift is between 0 and 90, and it is determined by the ratios and. Notice that the source degeneration capacitor is noiseless and does not contribute any phase noise. The placement of the source degeneration capacitance between the two source nodes instead of from each source node to ground is chosen for the following reasons: 1) in the latter case, each capacitance has to be doubled with area penalty, 2) the oscillator would be subject to common-mode oscillation [19]. The positive and smaller than 90 phase shift allows only one oscillation, Stage-I lags Stage-Q and the oscillation frequency is lower than the resonance frequency. Intuitively, the current provided by the complex coupling transconductance can be decomposed as the effective negative transconductance current,, and the effective coupling transconductance current,, which can be expressed as (5) (6) (7) According to (4), the effective negative transconductance,, and the effective coupling transconductance,, can be expressed as in (8) helps to compensate the loss of the tank. The input impedance seen at the gate of can be obtained by (8) (9) (10) (11) The input impedance can be regarded as the series combination of and. The quality factor of the input impedance is given by (12) With the series-parallel transformation around the oscillation frequency, the equivalent input resistance, which serves as for the preceding stage, is expressed as The equivalent parallel input capacitance (13) (14) is expressed as (15) The proposed CSD-QVCO architecture can be modeled as showninfig.11,,,and are the equivalent parallel resistance, capacitance, and inductance in the standalone tank, respectively. Using the CSD technique, the effective load resistance and capacitance, and the quality factor of the resonator can be expressed as (16) (17) (18) Note that is usually positive because it is very difficult to design to compensate the loss of tank by itself. Besides, is small compared to, so the CSD-QVCO presents a large frequency tuning range. The remarkable benefit present in the proposed architecture is that the commonly used positive feedback pairs are removed as the capacitive source degeneration differential pairs provide negative input impedance and phase shift for the coupling transconductance to compensate the energy loss in the tank.

5 TONG et al.: LC QUADRATURE VCO USING CSD COUPLING TO ELIMINATE BI-MODAL OSCILLATION 1875 B. Oscillation Frequency and Resonator Phase Shift The CSD-QVCO loop transfer function is given by C. Start-Up Condition The CSD-QVCO start-up condition is expressed as (28) (19) (20) is the minimum loop gain for the startup condition. Typically, is selected as 3 [20] to ensure worst case startup and overcome PVT variations. Using (20) and (25), the start-up condition can be written as According to the Barkausen s phase criteria, the circuit oscillates when the phase of is 0. To satisfy this condition, the following quantity should be pure imaginary: (21) (29) (30) which leads to (22) Assuming is close to, equation (29) can be simplified as (31) The oscillation frequency is approximated as (23) (24) (25) Equation (24) agrees with the phasor diagram in Fig. 10; with the phase shift from capacitive source degeneration, there is only one oscillation mode exhibiting that the oscillation frequency is lower than the resonance frequency and Stage-I lags Stage-Q. Since the phase shift in both I and Q stage has to be 90 to meet the Barkhausen s phase criteria, the phase shift from the coupling transconductance and the resonator are complementary. Hence, the resonator phase shift can be written as (26) Equation (26) shows that making closer to 90 reduces the resonator phase shift, so the oscillation frequency will be closer to the resonance frequency, and the effective quality factor of the tank will be larger, as long as the loop has enough gain to support the oscillation. The effective quality factor of the resonator can be approximated as (27) Equations (26) and (27) reveal that the effective quality factor of resonator is higher with approaching 90. Notice in equation (31) that the inherent negative input resistance helps to achieve this condition since,and the oscillation is mostly sustained by the coupling transconductance. D. Phase Noise The phase noise expression of the proposed CSD-QVCO is given as (32) is the total current noise and is the squared rms carrier current. Equation (32) shows that the less the phase shift from the resonator, the less the phase noise is produced. This is true in CSD-QVCO, as is decreased by increasing the phase shift. There are several ways to increase, which are compromised with other design considerations. According to (5), higher can be obtained by increasing through increase of either bias current or transistor size. However, current consumption is limited by power budget available for the oscillator, and transistor size is increased with the penalty of reduced oscillation frequency. can also be increased by decreasing ; however, is reduced using this approach. As a result, this approach is limited by the start-up requirement. A major advantage of the proposed QVCO is that it has low sensitivity to flicker noise present at the gate of transistors in Fig. 9. The capacitive degeneration makes the differential pair to inherently reject the low frequency signals; the noise is shaped by an intrinsic high-pass filtering. In [21] and [22], it is found that flicker noise in bias transistors could be a main source for close-in phase noise. To reduce this noise, is inserted as source degeneration resistor in Fig. 9 to each bias transistor. Therefore, the noise current at bias transistor output is reduced by a factor of.

6 1876 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 59, NO. 9, SEPTEMBER 2012 Although increasing bias transistor size helps to reduce flicker noise also, the drain capacitance is increased with the penalty of smaller and being more prone to common mode oscillation. TABLE I COMPARISON OF PHASE ACCURACY BETWEEN CONVENTIONAL QVCO AND CSD-QVCO E. Phase Error Mismatches between two stages leads to phase error in QVCOs. It has been demonstrated already that the quadrature phase error is reduced by increasing the coupling ratio defined as [12], [13], [18], [23] (33) is usually designed as large enough to compensate the loss of the resonator while is designed based on the requirements of phase noise, phase accuracy, and power consumption. A larger, or equivalently a larger coupling ratio, helps to improve the quadrature phase accuracy but sacrifices the phase noise and power consumption [23]. It has been proven that inserting a phase shift in the path of coupling transconductance to make can improve the phase noise as well as phase accuracy [13]. This phase-shifted coupling transconductance also helps compensating the loss of resonator so the power consumption can be further reduced. In the proposed CSD-QVCO, there is no negative cross-coupled transconductance but the coupling transconductance with capacitive source degeneration forms an active feedback to produce a negative transconductance asshowninfig.11.theeffect of the negative is equivalent to that of the negative cross-coupled transconductance. Therefore, according to [13] the phase errors from the mismatch of resonant frequency and the mismatch of coupling transconductance in the CSD-QVCO can be approximated as (34) (35) (36) Equation (36) shows that if a fixed magnitude of is given for comparison, the coupling ratio of CDS-QVCO is much larger than of conventional QVCOs because the magnitude of negative transconductance in CSD-QVCO is smaller than the required in conventional QVCOs. Therefore, the quadrature phase accuracy of CSD-QVCO is less sensitive to mismatches in both tanks and coupling transconductances. Table I shows the comparison of simulated phase errors between CSD-QVCO and the conventional QVCO with an ideal phase shifter with no signal attenuation, and a coupling ratio (strong coupling ratio). Quality factor of the LC tank in both topologies is 12, and the oscillation frequency is approximately 5 GHz. A 1% mismatch is given to the capacitance, coupling transconductance and negative cross-coupled transconductance between two oscillators. The simulation results show that CSD-QVCO has better Fig. 12. Simulated phase error versus varactor size mismatch. phase accuracy even though an optimized phase shift and strong coupling are used in the conventional QVCO. It reveals that while most QVCOs burn more power to have a larger coupling ratio to improve the phase accuracy, the inherent large coupling ratio of CSD-QVCO can achieve excellent phase accuracy without paying the penalty of power consumption. Hence, in terms of performing good phase accuracy, CSD-QVCO is a very power-efficient solution. The simulated phase errors of CSD-QVCO caused by mismatches in devices such as varactors, differential pairs and source degeneration capacitors are shown in Figs If the phase error, for example, is required to be below 1,the mismatch of the varactor and differential pair cannot surpass 4%, which can be easily achieved in this technology. The phase error resulting from the source degeneration capacitor mismatch is almost one order less than others. V. MEASUREMENT RESULTS Table II summarizes the sizes and values for the various components used in the two CSD-QVCOs in Fig. 9, the varactors are realized by NMOS transistors.thesimulated quality factor of the inductor is around 12 at 5 GHz. Fig. 15 shows the micro photograph of the 5-GHz CSD-QVCO with buffers, fabricated using TSMC 0.18 CMOS process. The CSD-QVCO is powered by a 1.2-V supply and consumes 5.2-mA current. The total chip area is m including the contact pads. The oscillator occupies m. The measurement was performed on a standard FR4 PC board. One of the four CSD-QVCO outputs was picked up by a SMA connector, with other outputs each terminated with a 50

7 TONG et al.: LC QUADRATURE VCO USING CSD COUPLING TO ELIMINATE BI-MODAL OSCILLATION 1877 TABLE II SIZES AND VALUES OF THE COMPONENTS IN THE IMPLEMENTED CSD-QVCO Fig. 13. Simulated phase error versus core transistor W/L mismatch. Fig GHz CSD-QVCO chip microphotograph. Fig. 14. Simulated phase error versus source degeneration capacitor mismatch. resistor. A voltage regulator was mounted to provide clean supply voltage. The output signal was measured through a spectrum analyzer. Fig. 16 shows the plots of the oscillation frequency versus varactor control voltage from both measurement and simulation results, the oscillation frequency is measured within the range of GHz. The measured oscillation frequency is a little less than the simulated one, suggesting underestimation of parasitic capacitance. Plot of the phase noise at the oscillation frequency of 5 GHz is shown in Fig. 17. As indicated in the plot, the slope of the phase noise after 20 khz is 20 db/dec, which is suggesting that the flicker noise is indeed not the major source of noise in the proposed QVCO. To compare the CSD-QVCO performance with other publication results, a generally used FoM expression is used: Fig. 16. Comparison of simulated and measured tuning curves. (37) Table III compares the CSD-QVCO performance with prior works using various phase shifting techniques. The proposed CSD-QVCO employs the least expensive technology and achieves a competitive FoM with the minimum power consumption. Fig. 17. Measured CSD-QVCO phase noise at 5 GHz.

8 1878 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 59, NO. 9, SEPTEMBER 2012 TABLE III CSD-QVCO PERFORMANCE COMPARISON WITH OTHER PHASE SHIFT QVCOS VI. CONCLUSION In this paper, a capacitive source degeneration QVCO has been described. It was shown that this oscillator is capable of eliminating undesired bi-modal oscillation. Fabricated in TSMC m CMOS technology, the CSD-QVCO presents a phase noise of 120 dbc/hz at 3-MHz offset from 5-GHz center frequency, with a power consumption of 6.4 mw from a 1.2-V supply. Compared to existing phase shift LC QVCOs, the CSD- QVCO presents excellent phase accuracy and power efficiency. It is an attractive solution for quadrature signal generation. REFERENCES [1] B. Razavi, RF Microelectronics. Englewood Cliffs, NJ: Prentice-Hall, [2] J. Li, J. Silva-Martinez, B. Brunn, S. Rokhsaz, and M. E. Robinson, A fully integrated CMOS clock data recovery IC for OC-192 Applications, IEEE Trans. Circuits Syst. I, vol. 55, no. 5, pp , Jun [3] A. Mirzaei, H. Darabi, J. C. Leete, and Y. Chang, Analysis and optimization of direct-conversion receivers with 25% duty-cycle currentdriven passive mixers, IEEE Trans. Circuits Syst. I,vol.57,no.9,pp , Sep [4] F. Behbahani, Y. Kishigami, J. Leete, and A. Abidi, CMOS mixers and polyphase filters for large image rejection, IEEE J. Solid-State Circuits, vol. 36, no. 6, pp , Jun [5] J. van der Tang, D. Kasperkovitz, and A. van Roermund, A GHz quadrature ring oscillator for optical receivers, IEEE J. Solid-State Circuits, vol. 37, no. 3, pp , Mar [6] S.Gierkink,S.Levantino,R.Frye,C.Samori,andV.Boccuzzi, A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp , Jul [7] C.-W. Yao and A. Willson, Jr., Energy-circulation quadrature LC-VCO, Proc. IEEE ISCAS, pp , May [8] D. Guermandi, P. Tortori, E. Franchi, and A. Gnudi, A GHz continuously tunable quadrature VCO, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp , Dec [9] A. Rofougaran, G. Chang, J. Rael, J.-C. Chang, M. Rofougaran, P. Chang, M. Djafari, M.-K. Ku, E. Roth, A. Abidi, and H. Samueli, A single-chip 900-MHz spread-spectrum wireless transceiver in 1-um CMOS. I. architecture and transmitter design, IEEE J. Solid-State Circuits, vol. 33, no. 4, pp , Apr [10] S. Li, I. Kipnis, and M. Ismail, A 10-GHz CMOS quadrature LC-VCO for multirate optical applications, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp , Oct [11] J. van der Tang, P. van de Ven, D. Kasperkovitz, and A. van Roermund, Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator, IEEE J. Solid-State Circuits, vol. 37, no. 5, pp , May [12] I. R. Chamas and S. Raman, A comprehensive analysis of quadrature signal synthesis in cross-coupled RF VCOs, IEEE Trans. Circuits Syst. I, vol. 54, no. 4, pp , Apr [13] A.Mirzaei,M.E.Heidari,R.Bagheri,S.Chehrazi,andA.A.Abidi, The quadrature LC oscillator: A complete portrait based on injection locking, IEEE J. Solid-State Circuits, vol. 42, no. 9, pp , Sep [14]M.Valla,G.Montagna,R.Castello,R.Tonietto,andI.Bietti, A 72-mW CMOS a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner, IEEE J. Solid-State Circuits, vol. 40, no. 4, pp , Apr [15] A. Mazzanti and F. Svelto, A 1.8-GHz injection-locked quadrature CMOS VCO with low phase noise and high phase accuracy, IEEE Trans. Circuits Syst. I, vol. 53, no. 3, pp , Mar [16] S. S. Rai and B. P. Otis, A 600 uw BAW-tuned quadrature VCO using source degenerate coupling, IEEE J. Solid-State Circuits, vol. 43, no. 1, pp , Jan [17] D. Huang, W. Li, J. Zhou, N. Li, and J. Chen, A frequency synthesizer with optimally coupled VCO and harmonic-rejection SSB mixer for multi-standard wireless receiver, IEEE J. Solid-State Circuits,vol.46, no. 6, pp , Jun [18] A. Mazzanti, F. Svelto, and P. Andreani, On the amplitude and phase errors of quadrature LC-tank CMOS oscillators, IEEE J. Solid-State Circuits, vol. 41, no. 6, pp , Jun [19] B. Jung and R. Harjani, High-frequency LC VCO design using capacitive degeneration, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp , Dec [20] D. Ham and A. Hajimiri, Concepts and methods in optimization of integrated LC VCOs, IEEE J. Solid-State Circuits, vol. 36, no. 6, pp , Jun [21] S. Levantino, C. Samori, A. Bonfanti, S. Gierkink, A. Lacaita, and V. Boccuzzi, Frequencydependenceonbiascurrentin5GHzCMOS VCOs: Impact on tuning range and flicker noise upconversion, IEEE J. Solid-State Circuits, vol. 37, no. 8, pp , Aug [22] A. Jerng and C. G. Sodini, The impact of device type and sizing on phase noise mechanisms, IEEE J. Solid-State Circuits, vol.40,no.2, pp , Feb [23] L. Romano, S. Levantino, C. Samori, and A. L. Lacaita, Multiphase LC oscillators, IEEE Trans. Circuits Syst. I, vol. 53, no. 7, pp , Jul Haitao Tong received the B.S. and M.S. degrees in electrical engineering from Southeast University, Nanjing, China, in 1998 and 2001, respectively, and the Ph.D. degree in electrical engineering from Texas A&M University, College Station, TX, in He is currently with Broadcom Corporation, Irvine, CA, as a Senior Staff Scientist working on high-speed transceivers. Shanfeng Cheng received the B.Sc. and M.Sc. degrees in electrical engineering from Fudan University, Shanghai, China, in 1994 and 1998, respectively, and the Ph.D. degree in electrical engineering from Texas A&M University, College Station, TX, in He worked on the design of single-chip cellular analog baseband circuit with Silicon Laboratories, NXP Semiconductors, ST-NXP Wireless and ST-Ericsson, Inc., from 2006 to His research interests include high-efficiency power management circuit, multi-gigahertz phase-locked loop and clock data recovery circuit, and audio amplifiers for cellular applications.

9 TONG et al.: LC QUADRATURE VCO USING CSD COUPLING TO ELIMINATE BI-MODAL OSCILLATION 1879 Yung-Chung Lo was born in Taipei, Taiwan. He received the B.S. degree in engineering and system science and the M.S. degree in electronic engineering from National Tsing-Hua University, Hsinchu, Taiwan, in 2000 and 2006, respectively. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Texas A&M University, College Station. He is currently a Research Assistant in the Department of Electrical Engineering, Texas A&M University. From 2002 to 2004, he worked for Macronix, Hsinchu. In summer 2008, he was with the Mobile Wireless Group, Intel Co., Hillsboro, OR, as an Intern Design Engineer, working on 40-nm wideband quadrature VCO. In Winter 2008, he was with RF Design Team, TSMC, Hsinchu, he worked on DCO design. His current research interests are low-noise frequency synthesizers and high-speed wideband continuous-time sigma-delta ADCs. Aydın İlker Karşılayan (M 99) received the B.S. and M.S. degrees in electrical engineering from Bilkent University, Ankara, Turkey, in 1993 and 1995, respectively, and the Ph.D. degree from Portland State University, Portland, OR, in In 2000, he joined the faculty of Texas A&M University, College Station, he is currently an Associate Professor of Electrical and Computer Engineering. His research interests are in the area of high-frequency analog filters, automatic tuning, mixed-mode integrated circuit design, RF communication circuits, and power harvesting. Dr. Karşılayan served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: Regular Papers from 2002 to 2004 and as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: Express Briefs from 2006 to Jose Silva-Martinez (SM 96 F 10) received the M.Sc. degree from the Instituto Nacional de Astrofisica Optica y Electronica (INAOE), Puebla, Mexico, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven, Belgium, in From 1981 to 1983, he was with the Electrical Engineering Department, INAOE, he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autonoma de Puebla, he remained until He pioneered the graduate program on opto-electronics in In 1993, he rejoined the Electronics Department, INAOE, and from May 1995 to December 1998, was the Head of the Electronics Department. He was a cofounder of the Ph.D. program on electronics in He is currently with the Department of Electrical and Computer Engineering, Texas A&M University, College Station, he currently holds the position of Texas Instruments I Professor in analog engineering. He has published over 90 journal and 140 conference papers, one book and ten book chapters. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical applications. Dr. Silva-Martinez served as IEEE CASS Vice President Region-9 ( ), and as Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II from 1997 to 1998 and 2002 to 2003, Associate Editor of IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I from 2004 to 2005 and 2007 to 2009, and currently serves on the board of editors of six other major journals. He was the recipient of the 2005 Outstanding Professor Award by the Electrical and Computer Engineering Department, Texas A&M University, coauthor of the paper that won the RF-IC 2005 Best Student Paper Award, co-advised in testing techniques the student who was the winner of the 2005 Best Doctoral Thesis Award, presented by the IEEE Test Technology Technical Council (TTTC) of the IEEE Computer Society, and he was the recipient of the 1990 European Solid-State Circuits Conference Best Paper Award.