V out. V in VRM. I Load

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1 Optimal Selection of Voltage Regulator Modules in a Power Delivery Network Behnam Amelifard Massoud Pedram Department of Electrical Engineering University of Southern California

2 Outline Introduction Voltage Regulator Modules (VRM s) Selection of VRM s in a PDN VRM Tree Optimization Algorithm Practical Issues Simulation Results Conclusions

3 Introduction Power delivery network (PDN) is a critical design component PDN design comprises of three steps: Establishing a PDN target impedance Designing a proper system-level decoupling network Needed to achieve target impedance over a broad frequency band Selecting the right voltage regulator modules (VRM s) VRM provides constant DC output voltage

4 Voltage Regulator Modules (VRM s) VRM tasks Voltage regulation Achieved by a feedback loop DC-DC conversion Step-down (Buck) Step-up (Boost) Buck-Boost Boost V in t VRM V out t I Load Power efficiency

5 Different Types of VRM s Inductor-based VRM s Inductors are energy storage Requires off-chip inductor Charge-pump VRM s Capacitors are energy storage Suitable for handheld devices V ref + PWM/ PFM VCO V in L C V in Charge pump V out I out Linear VRM s Require few or no reactive components More integrable compared to switching VRM s Efficiency limited by V out /V in Most efficient form: low- dropout regulator (LDO) V ref + C C V in V out V out I out I out

6 Voltage Regulator Module Tree Multiple voltage domains on SoC Different functional blocks (FB s) have different voltage and current demand A topology of VRM s needed to deliver power Typically a star topology of VRM is used A tree topology of VRM may be more power efficient P P VRM1 VRM2 VRM1 VRM3 VRM4 VRM2 VRM3 VRM4 CPU 200mA@1.5V DSP 100mA@1.2V Memory 100mA@1.8V Analog 90mA@2.5V CPU 200mA@1.5V DSP 100mA@1.2V Memory 100mA@1.8V Analog 90mA@2.5V

7 VRM Tree Optimization for Min Power Loss VRM Tree Optimization (RMTO) Problem: Given is: A library R of VRM s; r R: V out, min and max V in, max I out efficiency η =f (V I ) efficiency η r =f (V in, I out ) A set L loads; l L: (V l,i ) l A power source P, with the nominal voltage of V P Objective is Build a VRM tree b/w P and loads to minimize the power consumption n11 P Power Supply VRM FB n7 n8 n9 n10 n1 n2 n3 n4 n5 n6

8 RMTO Problem RMTO problem definition does not put any constraint on VRM tree depth In practice such a constraint is useful to manage cost Up to two level regulator in VRM tree To make a balanced-height VRM tree Insert ideal VRM s Assumption: Each VRM s produce a single V out n11 P n12 n13 Power Supply VRM Ideal VRM FB n7 n8 n9 n10 n1 n2 n3 n4 n5 n6

9 RMTO-FM Problem Monotone input current property (MICP) of a VRM I in is a monotone increasing function of I out independent of V in If tree topology is fixed and MICP holds, RMTO-FM is solved using dynamic programming Performing BFS starting from leaves n11 P n12 n13 Power Supply VRM Ideal VRM FB n7 n8 n9 n10 n1 n2 n3 n4 n5 n6

10 RMTO-FM Algorithm Candidate VRM s for n4: {R1, R2, R3, R4} U: Set of all output voltages of VRM s Vin Iin R1: V1 I1 R2: V2 I2 R3: V3 I3 I P I in P Vout Iin R1 * : V1 I1 * R2 * :V3 I2 n6 * Vin Iin R1 : V1 I1 n4 n5 R2 : V2 I2 n1 n2 n3 RMTO-FM Algorithm For each second level node n 2 v U Find VRM which minimizes I V1=V1 in (n 2 ) For each V3=V2 first level node n 1 v V m : m Fanout(n) Find VRM which minimizes I in (n 1 ) Return best VRM assignment V n : Set of all candidate V in for node n

11 RMTO-VM Algorithm If tree topology is varied and MICP holds, RMTO-VM is solved by enumerating all feasible trees RMTO-VM (R, L, V P ) Begin 1. For each T T 2 (n) 2. If T is feasible 3. RMTO-FM (R, L, T, T V P ) 4. End 5. End 6. Return best RMTO-FM (R, L, T, T V P ) End R: : set of VRM s L: : set of loads T 2 (n): All trees with exactly two internal nodes and n leaves

12 Tree Generation A VRM tree topology is feasible if Its depth is exactly four Leaf nodes under any second-level internal node have same voltage assignments. Number of feasible trees with n leaves is quite large In RMTO problem, many feasible trees are isomorphic P P R3 R3 R1 R2 R1 R2 FB1 FB2 FB3 FB1 FB2 FB3

13 Tree Generation (cont d) Two VRM trees are inter-isomorphicisomorphic if they become equal by a change of labeling li in intermediate t vertices P R3 P R3 Number of non-inter-isomorphic isomorphic trees R1 R2 with exactly n leaf nodes and two intermediate nodes: FB2 FB3 R1 R2 FB1 FB1 FB2 FB3 : Stirling number of second kind n T 2 (n) Set of non-inter inter-isomorphic isomorphic trees generated using restricted growth strings (RGS)

14 Practical Issue I: Effect of Non-Monotone Input Current MICP holds if VRM has a single mode 80 Some VRM s operate at 60 different modes depending on applied V 40 in 20 Non-monotone input current 0 vs. output current behavior Principle of dynamic programming g is broken RMTO-FN/VN require exhaustive search Change in RMTO-VM Lookup tables in level-2 nodes become 2-D Efficiency( (%) Vin(V) LDO 2/3X CP 1/2X CP 1/3X CP

15 Practical Issue II: Effect of Current Profile of Loads Current profiles play a key role in optimal VRM selection Motivational example: Curre ent VRM1 and VRM2 are candidate VRM s for FB1 200mA 0.9 R1 FB1 100mA 0.1 Prob Ef fficiency(%) VRM Iout(mA) Ef fficiency(%) VRM Iout(mA) VRM2 is more power efficient Current 200mA 100mA Prob VRM1 is more power efficient

16 Practical Issue II: Effect of Current Profile of Loads (cont d) Change in RMTO-FM algorithm to account for effect of current profile: Efficiency and I in of a candidate VRM become PWL function Assumption: profiles of different FB s are independent of one another Current Curren nt n3 Prob Prob n1 n2 Cur rrent Prob

17 Practical Issue III: Effect of Current Profile Correlations Correlation b/w load profiles could be used to design more efficient VRM tree Motivational example: Positively correlated FB s Parallel processor cores Negatively correlated FB s Activity migration Efficiency and I in of a candidate VRM become PWL function Current FB2 FB1 Current t 0 t 0 time FB2 FB1 time

18 Experimental Setup Proposed algorithms implemented in C++ A set of 30 commercial VRM s from Texas Instruments t and National Semiconductors used as library of VRM s. Results of RMTO-VM compared with results of optimal VRM assignment in astar topology (RMTO-SM) Benchmark Characteristics Circuit V P N I min I max V min V TB m 100m TB m TB m TB m TB m TB m TB m TB m V max 200m m m m m m m

19 Experimental Results Circuit VRM Tree Power Loss (mw) RMTO-SM RMTO-VM VRM Tree Power Dissipation Reduction (%) TB TB TB TB TB TB TB TB RMTO-VM reduces power dissipation in VRM tree by an average of 17.9%

20 Experimental Results (cont d) Optimal VRM Tree for TB1 P V P =2.5V VRM2 η=93% VRM4 η=95% LDO VRM1 η=83% VRM3 η=92% VRM5 η=78% LDO FB1 60mA@1.1V FB2 FB3 FB4 FB5 FB6 100mA@1.3V 100mA@1.8V 100mA@1.8V 50mA@1.5V 70mA@1.2V 21.9% power reduction in VRM tree

21 Conclusion Using a multi-level level VRM tree and optimally selecting VRM is beneficial for power reduction in PDN Modeled VRM tree optimization problem as a dynamic program and efficiently solved it On average about 18% power reduction in the VRM tree can be achieved by using a VRM tree topology

22 Thank You!