RFID Radio Circuit Design in CMOS. Minhong Mi, Ansoft Corp.

Transcription

1 1 RFID Radio Circuit Design in CMOS Minhong Mi, Ansoft Corp.

2 Outline 2 Overview of RFID Radios at System Level Power Generation/Management Circuit Recitifier, Charge-pump, Low-Drop Out (LDO) Voltage Regulator, Reset Circuit Demodulator Circuit Envelope Detector, Ring Oscillator, Comparator Modulator Circuit Bias Generator, Phase Modulator Overall Radio Simulation and Verification Input Impedance Simulation (under large signal condition) System/Nexxim Co-sim (with deep-modulated ASK input) Antenna Design

3 3 Overview of RFID Radio Circuits at System Level

4 Overview for RFID Radio 4πfd Loss[ db] = 20 log 10 log Gt 10 log c Antenna gain Gt=3dB Base station EIRP = 4W f=950mhz Distance d= 10m Loss ~ 47 db Tx Antenna Gain Rx Antenna Gain Frequency Distance Speed of Light Loss Tx Power Rx Power 3 db 1.64 db 950 MHz 10 meter 3.00E+08 m/s db dbm dbm Gr Antenna gain Gr=1.64 db Tag Receiving power ~ -1dBm 4

5 Overview for RFID Radio (2) 1 Tari = 6.25µ s 12.5µ s 25µ s 5 CW >= 8*RTcal ASK input Envelope Detector pivot = RTcal 2 RTcal = 0 length + 1 length Waveform shaper (A/D) Data Rate Register Counter To get TRCal to calibrate for link frequency (LF) when backscattering Digital Comparator LF = DR TRcal DR: Divide Ratio = 64/3 or 8 Sent from reader!! TRcal T pri = 1 = = Link Period LF DR Tag1: f osc1 Tag1: f osc2 Osc process, environment variations Tag1: f osc3

6 Overall Block Diagram for RFID Radio 6 To demodulator Env_detector Comparator Bandgap ref Bias Gen Ring Oscillator LDO Regulator Reset Rectifier Charge_pump Modulator

7 7 Power Generation & Management Circuit To demodulator Env_detector Comparator Bandgap ref Bias Gen Ring Oscillator Rectifier Charge_pump LDO Regulator Reset Modulator

8 Power Generation Circuit (Rectifier & Charge_Pump) 8 Large capacitor implemented with MosVar to make slow charge-pump

9 Power Management Circuit (LDO voltage regulator) from bandgap

10 Power Management Circuit (LDO Test) 10

11 Power Management Circuit (Reset) 11 1 : m

12 Power Management Circuit (Reset test) 12

13 13 Demodulator Circuit To demodulator Env_detector Comparator Bandgap ref Bias Gen Ring Oscillator Rectifier Charge_pump LDO Regulator Reset Modulator

14 Demodulator Circuit (top level) 14

15 Demodulator Circuit (Envelope detector) 15 Implemented with a two stage charge pump circuit

16 Demodulator Circuit (Comparator) 16 With hysteresis for better performance in a noisy environment.

17 Demodulated Signals us 1 Tari RTCal = 2.75*Tari Data-0 Data-1

18 Demodulator Circuit (Ring Oscillator) 18 Replica Feedback Differential Delay Block Comparator

19 Ring Oscillator Output 19 Ring Oscillator output Freq =4.0MHz

20 Demodulator Circuit (Bias and Control) 20 VT sensor Bipolar Core BandGap Ref Voltage BandGap Ref Voltage Constant Current Source

21 21 Modulator Circuit To demodulator Env_detector Comparator Bandgap ref Bias Gen Ring Oscillator Rectifier Charge_pump LDO Regulator Reset Modulator

22 Modulator Circuit for PSK 22

23 23 Tag s Overall Radio Simulation and Verification

24 Input Impedance Simulation for Tag s Radio 24 Under the condition of large signal input! Z total = Y tag Y Z 1 = Y tag tag = total 1 Z = Y total = 1 Z total tag 1 + Y src _ imp Yellow traces in the next slide red traces in the next slide

25 25 Input Impedance Simulation for Tag s ---- mod_in to AVDD ---- mod_in to AGND ~ 1.5V regulated supply generation

26 Continuous Wave (CW) Input (Transient) 26 Only transient solver can solve this region.. To save time and get more insightful information: Better use HB Engine

27 Continuous Wave (CW) Input (Harmonic Balanced: HB) 27 The results are from Nexxim s HB engine

28 28 System/Nexxim Co-simulation NSAMP=sample_num SAMPLE_RATE=sample_rat PERIOD=20/sample_rat A=1V DUTY=0.61 T1=0s T2=0s NSAMP=sample_num SAMPLE_RATE=sample_rat PERIOD=20/sample_rat A=1V DUTY=0.81 T1=0s T2=0s VTHRESHOLD=0.5V SP PWM_out PRBS NB=sample_num/10 BR=sample_rat/20 T=1V F=0V V0=0V TS=1/sample_rat TR=0s TF=0s SEED=0 AMMOD FC=fc P=-35dBm REF=-0.01 SAMPREP NOR=NOR SP AM_out SP env_p SP env_n SP avdd SP rst SP agnd antp env_p env_n agnd rst avdd mod_in U1 rfid_tag antp env_p env_n agnd rst avdd mod_in Env_Det inn inp opn opp antn antp rect_o rect_on rect_so rect_son rect_sso rect_sson agnd avdd r_avdd ref agnd avdd rst agnd antn antp avdd mod_in agnd avdd mr_bias vref E42 agnd rect_o agnd

29 System/Nexxim Co-simulation Worst case for supplied voltage generation duty cycle = 47.5% 29

30 System/Nexxim Co-simulation Worst case for supplied voltage generation duty cycle = 47.5% Generated Supplied Voltage --- Detected Evlelope --- Reset Signal

31 System/Nexxim Co-simulation Worst case for envelope detection: duty cycle = 13.25% 31

32 System/Nexxim Co-simulation Worst case for envelope detection: duty cycle = 13.25% Generated Supplied Voltage --- Detected Evlelope --- Reset Signal

33 System/Nexxim Co-simulation Typical case: RTcal = 2.75*Tari, PW = 0.4*Tari Average duty cycle = 71% 33

34 System/Nexxim Co-simulation Typical case: RTcal = 2.75*Tari, PW = 0.4*Tari Average duty cycle = 71% Generated Supplied Voltage --- Detected Evlelope --- Reset Signal

35 35 UHF RFID Antenna Design and Simulation

36 36 Design Method The method follows recently published work on RFID tag design. Reference: K.V. Rao, P.V. Nikitin, and S.F. Lam, Antenna design for UHF RFID tags: a review and a practical application, IEEE Trans. on Antennas Propagat. Dec

37 37 Design Goals Primary goal is to design an antenna that maximizes RFID read range Range is limited by tag response threshold (tag power absorption): range λ 4π PG t tgrτ P where λ = wavelength P t = Power of transmitter G t = Gain of transmit (reader) antenna G r = Gain of receive (tag) antenna P th = Tag response threshold power τ = mismatch factor (0 τ < 1) = th τ = Z 4R c Z = R + a c a Z = R + c + c jx R Z a jx a a c 2 Mismatch Factor Chip impedance Antenna impedance Goal: maximize power absorption by designing tag antenna impedance that resonates with chip impedance

38 38 Simulation and Optimization Note: This antenna was designed for Z a = 16 + j 350 Ω Dimensions Taken From Reference Paper Adjust parameters l, w, s, d, a, b to achieve desired antenna input impedance

39 Target Impedance From Circuit Simulation 39 Small signal chip impedance is Z c = 35 - j 155 Ω Re(Z in_tag ) Ω Capacitive Im(Z in_tag ) Rectifie r Envelope Detector Voltage Regulator Thin traces in the next slide 2V Modulator Thick traces in the next slide

40 40 Simulation in Ansoft Designer Loading Bar Reduces Resistance Provides inductive reactance Optimize to Match Target Impedance

41 41 Results Optimized Result Goal Small signal chip impedance is Z c = 35 - j 155 Ω Too low Z a = j 148 Ω l = 77.7 mm b = 7 mm s = 5 mm New Design Removed loading bar Reduced inductive meanders Z a = j 155 Ω l = 121 mm b = 2.85 mm Meets goal but larger in size

42 42 Swept Frequency Performance Real Part of Input Impedance Imaginary Part of Impedance Antenna design provides relatively flat response across UHF RFID band

43 43 Far-field Radiation Performance 1.95 db Gain Broad Omnidirectional Pattern

44 44 Conclusions UHF RFID tag RF/analog circuits have been designed and tested at circuit and system levels using Ansoft tools within the Cadence environment. Meandered (inductive) dipole antenna was designed for this specific tag. Ansoft team has comprehensive understanding of EPC Global Standard

45 Thank you! 45

46 Appendix: Entry for Nexxim/Cadence Integration 46 Netlist & Run