System Design Guide for Master

Transcription

1 System Design Guide for Master Motor Business Unit Appliances Company 2012/1/31 Rev. 2 Page 1

2 Revision History Revision Date Change Description /7/14 Initial Release /1/31 P1 Changed title from A Guide for Firmware Development. P3 Added introduction. P7 Added SH7216 example. P19 Added SH7145 example. P25 Added TMS320F28335 example. Deleted SH7065 example. Deleted TMS320VC example. P58 Added overview of profile position I/F. P72 Added internal-timer using system. Minor edits. 2012/1/31 Rev. 2 Page 2

3 Introduction To control transmit-timing, MNM1221 has two timer sources that are an external-timer and an internal-timer. This document describes examples of the external-timer using system in chapter 1, and the internal-timer using system in chapter 2. MNM1221 External Timer XTXTIM Internal Timer Sel Frame TX Timing Transmitter MII XSYNC Receiver Frame RX Completed Timing XINTRX 2012/1/31 Rev. 2 Page 3

4 Timing Signal Pins of MNM1221 For using the external-timer. If not using, tie to +3.3V. For using the internal-timer. If not using, leave unconnected. Input as a trigger to transmit (Falling edge) T = 0.5ms MNM1221 Output at transmitted (pulse width: 1.28us) XTXTIM XSYNC Pulse width: min 1us XINTRX Output at received (pulse width: 1.28us) Note: If not in RUNNING state, XTXTIM input is ignored. Init-A and Init-B frame in RING-CONFIG state are automatically transmitted with internal timer of MNM /1/31 Rev. 2 Page 4

5 Chapter 1 External-Timer Using System 2012/1/31 Rev. 2 Page 5

6 Goal of Timing Control The goal is to make the following timing: Offset to transmit after data exchange Command Update Period: 1ms Com. Period: 0.5ms Interrupt for NC calculation W R NC calculation W R NC calculation Com. Frame* TXD RXD Data exchange between CPU and MNM1221 #1 OK #2 Error #3 OK #4 OK RX interrupt M_RXMEM_HOLD register RX memory data of CPU-reading side in MNM1221 Bank switched Bank switched Bank switched #1 Data #3 Data #4 Data If a CRC error is detected in RX data, the RX bank is not switched in RX interrupt routine. In this case, previous RX data is read in the data exchange at the beginning of NC calculation. * One frame contains data of all slave nodes, and its length depends on the number of connected nodes. 2012/1/31 Rev. 2 Page 6

7 Example for SH7216 (Renesas) 2012/1/31 Rev. 2 Page 7

8 Timing Circuit 0.5ms CPU SH7216 To ensure level at reset. 3.3V ASIC MNM1221 PWM mode2 CLK: 50MHz (200MHz / 4) Timer MTU2 Ch1 TIOC1B TX timing XTXTIM Counter MTU2 Ch2 TCLKA CLK: Rising edge of TCLKA Counter clear and interrupt start at compare match of TGRA_2 Interrupt IRQ3 RX timing XINTRX - - MTU2-Ch1 MTU2-Ch1 generates generates TX TX timing timing signal. signal. For For 0.5ms, 0.5ms, TGRA_1 TGRA_1 = = 24999(0x61A7)@50MHz 24999(0x61A7)@50MHz - - MTU2-Ch2 MTU2-Ch2 divides divides this this signal, signal, and and generates generates the the start start signal signal for for NC NC calculating calculating interrupt. interrupt. For For 1ms, 1ms, TGRA_2 TGRA_2 = = IRQ3 IRQ3 by by XINTRX XINTRX of of MNM1221 MNM1221 causes causes RX RX interrupt. interrupt. 2012/1/31 Rev. 2 Page 8

9 Multiplex Interrupt Setting Source Trigger Priority Period Operation TGIA_2 Compare match of MTU2 Ch2-1ms - Communication data exchange - NC calculation /IRQ3 RX complete Higher than TGIA_2 0.5ms - Communication status check - RX memory bank switch 2012/1/31 Rev. 2 Page 9

10 Timing Chart 1 TGRA_1 = TGRA_1 Comm. period 0.5ms NC period 1ms TCNT_1 TGRB_1 TIOC1B TCLKA Adjust TGRB_1 (approx ms) TGRA_2 = 1 TGRA_2 TCNT_2 > Interrupt for NC calculation Data exchange W R NC calculation W R NC calculation 2012/1/31 Rev. 2 Page 10

11 Timing Chart 2 Adjust TGRB_2 to make After the data exchange, Low. The data exchange time must be measured by an oscilloscope. NC period: 1ms Com. Period: 0.5ms TIOC1B TCLKA TCNT_ Interrupt for NC calculation W R NC calculation W R NC calculation Com. Frame TXD RXD Data exchange Approx. RX interrupt These time are in proportion to the number of axes. 2012/1/31 Rev. 2 Page 11

12 Bus Connection ASIC MNM1221 Pullups must be installed on all CPU pins except WAIT to ensure level at reset. CPU SH7216 D31 D31 D0 D0 A10 A10 A2 A2 A1 A0 +3.3V MODE1 MODE0 BUSMODE XCS XRD XWR CSn RD WRL XWAIT WAIT 2012/1/31 Rev. 2 Page 12

13 Example for SH7206 (Renesas) 2012/1/31 Rev. 2 Page 13

14 Timing Circuit CPU SH ms ASIC MNM1221 PWM mode2 CLK: MHz ( MHz x 2) Timer MTU2 Ch2 TIOC2B TX timing XTXTIM Counter MTU2 Ch0 TCLKD CLK: Rising edge of TCLKD Counter clear and interrupt start at compare match of TGRA_0 Interrupt IRQ0 RX timing XINTRX - - MTU2-Ch2 MTU2-Ch2 generates generates TX TX timing timing signal. signal. For For 0.5ms, 0.5ms, TGRA_2 TGRA_2 = = 16666(0x411A)@ MHz 16666(0x411A)@ MHz - - MTU2-Ch0 MTU2-Ch0 divides divides this this signal, signal, and and generates generates the the start start signal signal for for NC NC calculating calculating interrupt. interrupt. For For 1ms, 1ms, TGRA_0 TGRA_0 = = IRQ2 IRQ2 by by XINTRX XINTRX of of MNM1221 MNM1221 causes causes RX RX interrupt. interrupt. 2012/1/31 Rev. 2 Page 14

15 Multiplex Interrupt Setting Source Trigger Priority Period Operation TGIA_0 Compare match of MTU2 Ch0-1ms - Communication data exchange - NC calculation /IRQ0 RX complete Higher than TGIA_0 0.5ms - Communication status check - RX memory bank switch 2012/1/31 Rev. 2 Page 15

16 Timing Chart 1 TGRA_2 = 1666 TGRA_2 Comm. period 0.5ms NC period 1ms TCNT_2 TGRB_2 TIOC2B TCLKD Adjust TGRB_2 (approx ms) TGRA_0 = 1 TGRA_0 TCNT_0 > Interrupt for NC calculation Data exchange W R NC calculation W R NC calculation 2012/1/31 Rev. 2 Page 16

17 Timing Chart 2 Adjust TGRB_2 to make After the data exchange, Low. The data exchange time must be measured by an oscilloscope. NC period: 1ms Com. Period: 0.5ms TIOC2B TCLKD TCNT_ Interrupt for NC calculation W R NC calculation W R NC calculation Data exchange Approx. TXD RXD RX interrupt These time are in proportion to the number of axes. 2012/1/31 Rev. 2 Page 17

18 Bus Connection ASIC MNM1221 CPU SH7206 D31 D31 D0 D0 A10 A10 A2 A2 A1 A0 +3.3V MODE1 MODE0 BUSMODE XCS XRD XWR CSn RD WE0 XWAIT WAIT Note: Because each pin of SH7206 has weak-keeper, it is not necessary to install external pullups on bus-interface pins. 2012/1/31 Rev. 2 Page 18

19 Example for SH7145 (Renesas) 2012/1/31 Rev. 2 Page 19

20 Timing Circuit 0.5ms PWM mode2 CLK: MHz (12.288MHz x 2) Timer CPU SH7145 To ensure level at reset. MTU Ch2 TIOC2B 3.3V TX timing ASIC MNM1221 XTXTIM Counter MTU Ch0 TCLKD CLK: Rising edge of TCLKD Counter clear and interrupt start at compare match of TGRA_0 Interrupt IRQ2 RX timing XINTRX - - MTU-Ch2 MTU-Ch2 generates generates TX TX timing timing signal. signal. For For 0.5ms, 0.5ms, TGRA_2 TGRA_2 = = 12287(0x2FFF)@24.576MHz 12287(0x2FFF)@24.576MHz - - MTU-Ch0 MTU-Ch0 divides divides this this signal, signal, and and generates generates the the start start signal signal for for NC NC calculating calculating interrupt. interrupt. For For 1ms, 1ms, TGRA_0 TGRA_0 = = IRQ2 IRQ2 by by XINTRX XINTRX of of MNM1221 MNM1221 causes causes RX RX interrupt. interrupt. 2012/1/31 Rev. 2 Page 20

21 Multiplex Interrupt Setting Source Trigger Priority Period Operation TGIA_0 Compare match of MTU Ch0-1ms - Communication data exchange - NC Calculation /IRQ2 RX complete Higher than TGIA_0 0.5ms - Communication status check - RX memory bank switch 2012/1/31 Rev. 2 Page 21

22 Timing Chart 1 TGRA_2 = TGRA_2 Comm. period 0.5ms NC period 1ms TCNT_2 TGRB_2 TIOC2B TCLKD Adjust TGRB_2 (approx ms) TGRA_0 = 1 TGRA_0 TCNT_0 > Interrupt for NC calculation Data exchange W R NC calculation W R NC calculation 2012/1/31 Rev. 2 Page 22

23 Timing Chart 2 Adjust TGRB_2 to make After the data exchange, Low. The data exchange time must be measured by an oscilloscope. NC period: 1ms Com. Period: 0.5ms TIOC2B TCLKD TCNT_ Interrupt for NC calculation W R NC calculation W R NC calculation Com. Frame TXD RXD Data exchange Approx. RX interrupt These time are in proportion to the number of axes. 2012/1/31 Rev. 2 Page 23

24 Bus Connection ASIC MNM1221 Pullups must be installed on all CPU pins except WAIT to ensure level at reset. CPU SH7145 D31 D31 D0 D0 A10 A10 A2 A2 A1 A0 +3.3V MODE1 MODE0 BUSMODE XCS XRD XWR CSn RD WRL XWAIT WAIT 2012/1/31 Rev. 2 Page 24

25 Example for TMS320F28335 (TI) 2012/1/31 Rev. 2 Page 25

26 Timing Circuit 0.5ms CPU TMS320F28335 To ensure level at reset. +3.3V ASIC MNM1221 TBCLK: e.g. 75MHz Timer epwm 1 EPWM1A TX timing XTXTIM Counter ecap 6 ECAP6 Select rising edge for capture event, and divide with event prescaler. Interrupt GPIO2 RX timing XINTRX - - epwm1 epwm1 generates generates TX TX timing timing signal. signal. For For 0.5ms, 0.5ms, TBPRD TBPRD = = 37499(0x927B)@TBCLK 37499(0x927B)@TBCLK 75MHz 75MHz - - ecap6 ecap6 divides divides this this signal, signal, and and generates generates the the start start signal signal for for NC NC calculating calculating interrupt. interrupt. For For 1ms, 1ms, PRESCALE PRESCALE = = External External interrupt interrupt by by XINTRX XINTRX through through GPIO2 GPIO2 causes causes RX RX interrupt. interrupt. 2012/1/31 Rev. 2 Page 26

27 Multiplex Interrupt Setting Source Trigger Priority Period Operation ECAP6 INT Capture event of ecap6-1ms - Communication data exchange - NC calculation XINT through GPIO2 RX complete Higher than ECAP6 0.5ms - Communication status check - RX memory bank switch 2012/1/31 Rev. 2 Page 27

28 Timing Chart 1 TBCLK TBPRD 75MHz (0x927B) NC period 1ms 37.5MHz 18.75MHz (0x493D) 9374 (0x249E) TBPRD Comm. period 0.5ms TBCTR CMPA Adjust CMPA (approx ms) EPWM1A ECAP6 Prescaler output > 0 PSout div 2 Interrupt for NC calculation Data exchange W R NC calculation W R NC calculation Interrupt by rising edge of event Enable Enable all all capture capture event event 1 1 to to 4 4 as as interrupt interrupt source, source, and set capture mode to continuous. and set capture mode to continuous. 2012/1/31 Rev. 2 Page 28

29 Timing Chart 2 Adjust CMPA to make After the data exchange, Low. The data exchange time must be measured by an oscilloscope. NC period: 1ms Com. Period: 0.5ms EPWM1A ECAP6 PSout div 2 Interrupt for NC calculation W R NC calculation W R NC calculation Com. Frame TXD RXD Data exchange Approx. RX interrupt These time are in proportion to the number of axes. 2012/1/31 Rev. 2 Page 29

30 Bus Connection ASIC MNM1221 D31 D0 XD31 XD0 CPU TMS320F28335 For data bus, internal pullups on each pin must be enabled with CPU configuration. A10 A2 A1 A0 XA9 XA1 XA0 / XWE1 +3.3V MODE1 MODE0 BUSMODE XCS XRD XWR XZCSn XRD XWE0 XWAIT XREADY Note: TMS320F28335 has 16bit-unit address bus. 2012/1/31 Rev. 2 Page 30

31 Important Notes for Address Although MNM1221 has 8bit-unit address bus, TMS320F28335 has 16bit-unit. Therefore each address connection must be shifted 1, such as A2(MNM1221) - XA1(TMS320F28335). Also in the example code, all address definitions must be modified as follows: mnm1221_m.h Change according to # of XZCS. XZCS0: 0x XZCS6: 0x XZCS7: 0x Delete this line. For each address definition, change like this: (ADDR_MNM (0x0000 >> 1)) 2012/1/31 Rev. 2 Page 31

32 Details of TMS320F28335 Configuration 2012/1/31 Rev. 2 Page 32

33 Period 0.5ms Setting for epwm Setting for 0.5ms: TBCLK 75MHz (150MHz / 2) 37.5MHz (150MHz / 4) 18.75MHz (150MHz / 8) TBPRD (0x927B) (0x493D) 9374 (0x249E) 2012/1/31 Rev. 2 Page 33

34 Interrupt by ecap Captured data is not used because of interrupt use only. Using area for interrupt 2012/1/31 Rev. 2 Page 34

35 Event Prescaler inside ecap 2012/1/31 Rev. 2 Page 35

36 ECCTL1 Register 2012/1/31 Rev. 2 Page 36

37 ECCTL2 Register 2012/1/31 Rev. 2 Page 37

38 ECEINT Register Disable Enable 2012/1/31 Rev. 2 Page 38

39 ECCLR Register At the beginning of interrupt routine, interrupt flags must be cleared to prepare the next interrupt /1/31 Rev. 2 Page 39

40 Capture Interrupt Sequence Interrupt occurring: CEVT1 CEVT2 CEVT3 CEVT4 CEVT1 2012/1/31 Rev. 2 Page 40

41 Example for CPU without Internal Timer 2012/1/31 Rev. 2 Page 41

42 Timing Circuit CPU IRQn T = 1ms ASIC MNM1221 Interrupt SN74LV4040A T = 0.5ms QL(Q12) QK(Q11) SN74LVC74A D Q TX timing XTXTIM 4.096MHz QJ(Q10) CLK Q Timing Shift Interrupt IRQm RX timing Counter XINTRX At system reset, CLR* = L and PRE* = H should be inputted to clear Q output. Priority: IRQm > IRQn At system reset, CLR = H should be inputted to clear all outputs. 2012/1/31 Rev. 2 Page 42

43 Timing Chart 1 Counter QJ (Q10) T = 250us 74LV4040 QK (Q11) T = 500us QL (Q12) T = 1ms Timing Shift 125us Q of 74LVC74 T = 500us 2012/1/31 Rev. 2 Page 43

44 Timing Chart 2 NC period: 1ms IRQn of CPU T = 1ms XTXTIM of MNM1221 T = 500us 125us Com. period: 500us It is assumed that the data exchange is done within 125us. NC Calculation Interrupt W R NC Calculation W R NC Calculation Data exchange Approx. TXD RXD IRQm of CPU T = 500us 2012/1/31 Rev. 2 Page 44

45 Location of Example Codes 2012/1/31 Rev. 2 Page 45

46 Location of Example Codes These functions have to be made by yourself. Example code Function ctrl_mnm1221_m() - Controlling MNM Exchanging communication data Reading response data from buffer rx_buf[] Generating motion profile Writing command data to buffer tx_buf[] NC calculation Interrupt T=1ms W R NC calculation Priority RX Interrupt T=0.5ms Interrupt Return Multiplex nested interrupt Higher Note: If there is timing conflict between data exchange and RX interrupt, the RX interrupt must be disabled during the data exchange. Example code Function int_rx_mnm1221() - Checking communication status - RX memory bank switch 2012/1/31 Rev. 2 Page 46

47 An Example of NC Calculation void int_nc_calc(void) { short phase; The next phase phase = ctrl_mnm1221_m(); COM LED control This function includes the data exchange between the buffer and MNM1221. The time for the exchange depends on the number of axes. if (phase!= PH_RUNNING) { } return; Reading response data from buffer rx_buf[] Generating motion profile Command operation If not in RUNNING, get away. At any timing, you can access the rx_buf[] and tx_buf[]. Also, you do not have to access at once. } Writing command data to buffer tx_buff[] 2012/1/31 Rev. 2 Page 47

48 COM-LED operation Phase of Firmware Firmware operation T = 1ms Timing Chart at Start-up TX Init frame 500us Confirm Ready State Error check of of Slave information Cyclic Start INIT WAITING PREPARE START RUNNING 1ms When error, set COM-LED to RED OFF Flashing GREEN (0.5s ON, 0.5s OFF) GREEN From here, Start NC calculation XTXTIM TX RX Init-A T = 2ms Init-B Invalid Data (NOP) Real-time Valid Data When Slave NOT established, MNM1221 repeats TX. XSYNC XINTRX State of MNM1221 INITIAL RING-CONFIG READY RUNNING 2012/1/31 Rev. 2 Page 48

49 Notes of Using Example Codes 2012/1/31 Rev. 2 Page 49

50 Data Structure (32bit) The following shows the structure of one element of tx_buf[] or rx_buf[] array when 32bit bus access. Bit 31 Bit 24 Bit 23 Bit 16 Bit 15 Bit 8 Bit 7 Bit 0 data[0] byte3 byte2 byte1 byte0 One element of tx_buf[] or rx_buf[] data[1] data[2] data[3] byte7 byte6 byte5 byte4 byteb bytea byte9 byte8 bytef bytee byted bytec byte0 to F is corresponding to contents of a data block consisting of 16bytes. 2012/1/31 Rev. 2 Page 50

51 Data Structure (16bit) The following shows the structure of one element of tx_buf[] or rx_buf[] array when 16bit bus access. One element of tx_buf[] or rx_buf[] data[0] data[1] data[2] data[3] data[4] data[5] data[6] data[7] Bit 15 byte1 byte3 byte5 byte7 byte9 byteb byted bytef Bit 8 Bit 7 byte0 byte2 byte4 byte6 byte8 bytea bytec bytee Bit 0 byte0 to F is corresponding to contents of a data block consisting of 16bytes. 2012/1/31 Rev. 2 Page 51

52 Status LEDs for Communication COM (green and red) 2 Output Port LINK (green) Input Port RJ45 RJ45 PHY MII ASIC MNM1221 CPU 25MHz 2012/1/31 Rev. 2 Page 52

53 COM LED Operation COM LED which has red and green lights should be operated as follows: Normally Return value of ctrl_mnm1221_m() PH_INIT PH_WAITING PH_PREPARE PH_START PH_RUNNING COM LED operation Disappearance Flashing Green (0.5s ON, 0.5s OFF) Solid Green Error detected Contents of error Timeout in RUNNING state Mismatch of slave information (e.g. duplicate MAC-ID) COM LED operation Flashing Red (0.5s ON, 0.5s OFF) Solid Red Notes: - Solid Red means that a system reset is necessary to release the error. - Either green or red must be lighted. 2012/1/31 Rev. 2 Page 53

54 Overview of Cyclic Position I/F 2012/1/31 Rev. 2 Page 54

55 Data Block Command (TX) Normally, set 0x20 (Position). Response (RX) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 byte0 0 (CMD) Update Counter MAC-ID byte0 1 (RSP) Update Counter Echo Actual MAC-ID byte1 0 Command Code byte1 CMD Error Command Code Echo byte2 Servo On 0 0 Gain SW TL SW HM Ctrl 0 0 byte2 Servo Act. Servo Ready Alarm Warn. TL HM Comp. In Prog. In Pos. byte3 Hard Stop SMT Stop Pause 0 SL SW 0 EX- OUT2 EX- OUT1 byte3 SI- MO5 SI- MO4 EXT 3 EXT 2 SI- MO1 Home POT NOT byte4 byte5 byte6 byte7 Command Position Low byte Low Middle byte High Middle byte High byte byte4 byte5 byte6 byte7 Actual Position Low byte Low Middle byte High Middle byte High byte byte8 byte9 bytea byteb Command Data 2 Low byte Low Middle byte High Middle byte High byte byte8 byte9 bytea byteb Response Data 2 Low byte Low Middle byte High Middle byte High byte bytec byted bytee bytef Command Data 3 Low byte Low Middle byte High Middle byte High byte bytec byted bytee bytef Response Data 3 Low byte Low Middle byte High Middle byte High byte Note: In cyclic position I/F, at least red portions must be supported. 2012/1/31 Rev. 2 Page 55

56 Command at Start-up Time MNM1221_M_CYCL_START (Register in MNM1221) Start MAC-ID Valid data Update Counter 0 1ms Command data block Command Code 0x00 (NOP) 0x20 (Position) Command Position 0 (free) Valid data Servo On Off On Note: This time chart shows an example of cyclic position I/F. During Servo Off, Command Position should be set with Actual Position value of Response. 2012/1/31 Rev. 2 Page 56

57 Cyclic Position I/F Velocity Time Command Position [pulse] Cmd. Update Period (NC calculation period) 1 /0.5/0.166ms (Select with parameter) Time Absolute (not incremental) value must be used. Default polarity: + CCW, - CW 2012/1/31 Rev. 2 Page 57

58 Overview of Profile Position I/F 2012/1/31 Rev. 2 Page 58

59 Command Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 C/R (0) TMG CNT Servo On Hard Stop Update Counter MAC-ID (0 to 31) 0 0 Smooth Stop Gain SW 17h (Command Code) TL SW Homing Ctrl Pause 0 SL SW 0 Target Position 0 0 EX- OUT2 EX- OUT1 Byte7 Byte8 Type Code Byte9 0 Byte10 0 Mode, Inc/Abs Byte11 Byte12 Byte13 Byte14 Monitor Sel Target Speed Byte /1/31 Rev. 2 Page 59

60 Response Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Byte0 C/R (1) Update Counter Echo Actual MAC-ID (0 to 31) Byte1 CMD Error 17h (Command Code Echo) Byte2 Servo Active Servo Ready Alarm Warning Torque Limited Homing Complete In Progress In Position Byte3 SI-MON5 /E-STOP SI-MON4 /EX-SON SI-MON3 /EXT3 SI-MON2 /EXT2 SI-MON1 /EXT1 Home POT /NOT NOT /POT Byte4 Byte5 Byte6 Actual Position Byte7 Byte8 Type Code Echo Byte9 ERR WNG 0 BUSY PSL /NSL NSL /PSL NEAR Latch Compl Byte10 0 Byte11 Byte12 Byte13 Byte14 Monitor Sel Echo Monitor Data Byte /1/31 Rev. 2 Page 60

61 Start When In Progress = 0, a change of Command Code 10h to 17h makes servo start motion. Acceleration and deceleration are preset with parameter. Abs/Inc is set with Type Code at start. Target Speed Speed s1 Acceleration Pr8.01 Deceleration Pr8.04 Time Target Position p1 Position Time Command Code 10h 17h Target Position, Speed p1, s1 In Progress (Response) 2012/1/31 Rev. 2 Page 61

62 Changing T Speed in Motion When In Progress = 1, target speed can be changed. Even if changing target speed to 0 or Pause to 1, In Progress keeps 1 during stop. Speed s1 s2 Time Command Code 10h 17h Target Speed s1 s2 In Progress (Response) 2012/1/31 Rev. 2 Page 62

63 Modifying the Example Code 2012/1/31 Rev. 2 Page 63

64 Definition for Bus Access mnm1221_m.h Modify this address value in order to suit to the located address of MNM bit bus: Delete this. 16bit bus: Leave this. 2012/1/31 Rev. 2 Page 64

65 Definition of Variables mnm1221_m.c For fast access, locate this communication buffers on the internal RAM of CPU if possible. 2012/1/31 Rev. 2 Page 65

66 Slave Information Table mnm1221_m.c When test, modify these values according to actual your system. In one-axis case, make these lines comment. And change this number to /1/31 Rev. 2 Page 66

67 Slave Information Table (Cont.) Structure of Slave Information data: Bit 15 Bit 14 Bit 13 Bit 12 Bit 8 Bit 7 Bit 6 Bit 5 Bit 0 ACT MODE MAC-ID 0 0 Number of Blocks Set node address Set 1 (generic slave) Set 1 Active: 1 (present) Inactive: 0 (absent) 2012/1/31 Rev. 2 Page 67

68 Style of Initializing Variables ctrl_mnm1221_m() in mnm1221_m.c To set variable phase to 0 after reset, select this value (0 or 1) according to your initializing process. 2012/1/31 Rev. 2 Page 68

69 Checking Slave Information ctrl_mnm1221_m() in mnm1221_m.c Add the routine when an error is detected in READY state. In actual application, the phase should not be changed to PH_RESET until releasing errors. 2012/1/31 Rev. 2 Page 69

70 Starting Cyclic Transmission ctrl_mnm1221_m() in mnm1221_m.c This process is to set a initial transmit data including MACID. Since this is for initial test, your proper process is needed. If you leave this as it is, clr_mnm1221_tx_mem() should be deleted to avoid duplicate initializing. The data exchange function is used provisionally. But the reading of the exchange is unnecessary. 2012/1/31 Rev. 2 Page 70

71 In Running State ctrl_mnm1221_m() in mnm1221_m.c After test, you have to remove. Add the routine when time-out error is detected. At that time, Servo-OFF must be commanded to all servos for safety. In actual application, the phase should not be changed to PH_RESET until releasing errors. 2012/1/31 Rev. 2 Page 71

72 Chapter 2 Internal-Timer Using System 2012/1/31 Rev. 2 Page 72

73 The Point of System Set both Command Update Period and Communication Period to the same time. Start NC calculation interrupt with MNM1221 XSYNC. If not using RX interrupt, detect timeout error by software using Update Counter Echo. 2012/1/31 Rev. 2 Page 73

74 Period Setting of A5N Drive Set both command update period and communication period to the same. Default setting must be changed. Update Period Com. Period Pr7.20 Setting Name Range Description Pr ms 1.000ms ms 0.500ms ms 0.500ms ms 0.166ms ms 0.083ms 0 2 Pr7.20 Communication Period 0 to 12 Pr7.21 Ratio of Command Update Period 1 to 2 0: 0.083ms 1: 0.166ms 3: 0.5ms 6: 1.0ms Else: Do not set. (Reserved) Command Update / Communication Period 1: 1 2: 2 (Com.=0.5ms case only) 2012/1/31 Rev. 2 Page 74

75 Goal of Timing Control The goal is to make the following timing: Command Update Period = Communication Period Interrupt for NC calculation R NC calculation W R NC calculation W R Com. Frame* TXD RXD Data exchange between CPU and MNM1221 #1 OK #2 Error #3 OK RX interrupt for WDT clear Deferred due to lower priority M_RXMEM_HOLD register RX memory data of CPU-reading side in MNM1221 Bank switched During reading, set to 1 #1 OK Data Bank switched Because of error, do not read. #2 Error Data Regardless of CRC error, the RX bank is switched at RX completed. In NC calculation routine, when RX data is OK, the M_RXMEM_HOLD is set to 1 and RX data is read. * One frame contains data of all slave nodes, and its length depends on the number of connected nodes. 2012/1/31 Rev. 2 Page 75

76 Example for an Embedded CPU 2012/1/31 Rev. 2 Page 76

77 Timing Circuit When not in RUNNING state, CPU interrupt should be disabled. CPU NC Calculation Start ASIC MNM1221 IRQn Interrupt TX start timing XSYNC IRQm Interrupt RX completed timing XINTRX If not using RX interrupt, a timeout should be detected with the echo back of Update Counter in the data block. 2012/1/31 Rev. 2 Page 77

78 Recommended Timing XSYNC Com. period IRQn of CPU NC period R: Reading RX data W: Writing TX data NC Calculation Interrupt R NC Calc. W R NC Calc. W R NC Calc. W R NC Calc. W Com. Frame Data exchange Tf TX data flow TXD RXD XINTRX Tf: approx. 11us@1-axis to 300us@32-axis 2012/1/31 Rev. 2 Page 78

79 NOT Recommended Timing XSYNC IRQn of CPU Com. period If TX data writing is done at the beginning of NC calculation, it causes longer delay. NC period TX data flow R: Reading RX data W: Writing TX data NC Calculation Interrupt W R NC Calc. W R NC Calc. W R NC Calc. W R NC Calc. Note Com. Frame TXD RXD Data exchange XINTRX Note: At XSYNC falling edge, a frame has already been in transmitting, and the memory-bank switching after writing TX-data is deferred. Therefore the transmit timing is delayed for one communication period. 2012/1/31 Rev. 2 Page 79

80 Timeout Detection Example for Not Using RX Interrupt 2012/1/31 Rev. 2 Page 80

81 Update Counter Command (TX) Response (RX) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 byte0 0 (CMD) Update Counter MAC-ID byte0 1 (RSP) Update Counter Echo Actual MAC-ID byte1 0 Command Code byte1 CMD Error Command Code Echo byte2 Servo On 0 0 Gain SW TL SW HM Ctrl 0 0 byte2 Servo Act. Servo Ready Alarm Warn. TL HM Comp. In Prog. In Pos. byte3 Hard Stop SMT Stop Pause 0 SL SW 0 EX- OUT2 EX- OUT1 byte3 SI- MO5 SI- MO4 EXT 3 EXT 2 SI- MO1 Home POT NOT byte4 byte5 byte6 byte7 Command Position Low byte Low Middle byte High Middle byte High byte byte4 byte5 byte6 byte7 Actual Position Low byte Low Middle byte High Middle byte High byte byte8 byte9 bytea byteb Command Data 2 Low byte Low Middle byte High Middle byte High byte byte8 byte9 bytea byteb Response Data 2 Low byte Low Middle byte High Middle byte High byte bytec byted bytee bytef Command Data 3 Low byte Low Middle byte High Middle byte High byte bytec byted bytee bytef Response Data 3 Low byte Low Middle byte High Middle byte High byte 2012/1/31 Rev. 2 Page 81

82 Timeout Detection If Update Counter Echo is not changed continuously for a certain time, timeout should be considered. Normal Command update period Error Detection Time Timeout Error If timeout is detected, servo-off must be commanded to all axes for safety. 2012/1/31 Rev. 2 Page 82

83 Modifying the Example Code See also corresponding clause in chapter 1. There are some abbreviations to prevent duplicate descriptions. 2012/1/31 Rev. 2 Page 83

84 COM-LED operation Phase of Firmware Firmware operation Timing at Start-up OFF Blinking GREEN (0.5s ON, 0.5s OFF) GREEN TX Init frame Confirm Ready State Error check of of Slave information Cyclic Start INIT WAITING PREPARE START RUNNING Main loop Note: In also RUNNING state, main loop operation is continued. When error, set COM-LED to RED Interrupt (NC calculation) IRQ Enable Interrupt Disable Enable Com. Frame TX RX Init-A T = 2ms Init-B Real-time During Slave NOT established, MNM1221 repeats Init-A TX. XSYNC XINTRX State of MNM1221 INITIAL RING-CONFIG READY RUNNING 2012/1/31 Rev. 2 Page 84

85 Task Assignment Task Trigger Priority Period Operation Main loop Controlling MNM1221 (including com-status check) - COM LED control XSYNC Interrupt TX start - e.g. 0.5ms - Communication data exchange - NC calculation - Timeout detection XINTRX Interrupt RX completed Lower than XSYNC Same as XSYNC - Watchdog timer clear Notes: - The interrupts must be disabled until RUNNING state. - If not using XINTRX interrupt, a timeout detection with Update Counter Echo is necessary. 2012/1/31 Rev. 2 Page 85

86 Location of Example Codes Transfer this function into main loop. Example code Function ctrl_mnm1221_m() - Controlling MNM Exchanging communication data For only data-exchanging xchg_com_data(), put it into NC calculation interrupt. Make these functions by yourself. Reading response data from buffer rx_buf[] Generating motion profile Writing command data to buffer tx_buf[] NC calculation interrupt (XSYNC interrupt) R NC calculation W Note XINTRX Deferred due to lower priority XINTRX interrupt Transfer into main loop and NC calculation interrupt. Example code Function int_rx_mnm1221() - Checking communication status - RX memory bank switch - Watchdog timer clear Note: If both RX completed and RX data reading are at the same time, it might cause a problem. When only a few axes are connected, there is this risk. To prevent it, the RX data reading should be put at the beginning of NC calculation. 2012/1/31 Rev. 2 Page 86

87 An Example of Location void int_nc_calc(void) { xchg_com_data(); Data exchanging between the buffer and MNM1221 Reading response data from buffer rx_buf[] Generating motion profile Command operation At any timing, you can access the rx_buf[] and tx_buf[]. Also, you do not have to access at once. Writing command data to buffer tx_buff[] } TX data writing Timeout detection This is transferred from xchg_com_data(). This is transferred from xchg_com_data(). 2012/1/31 Rev. 2 Page 87

88 MNM1221 initializing Replace this line. 0 MNM1221_M_TX_PERIOD = 0x30D4; /* T = 0.5ms */ MNM1221_M_TXTIM_SEL = 0; /* internal timer */ Communication Period 1ms 0.5ms 0.166ms MNM1221_M_ TX_PERIOD 0x61A8 0x30D4 0x /1/31 Rev. 2 Page 88

89 Reading State ctrl_mnm1221_m() in mnm1221_m.c Put this function into main loop. mnm1221.state = MNM1221_M_STATE; Insert this line. Here, insert an interrupt disable function provided by yourself. /* */ Delete this line. 2012/1/31 Rev. 2 Page 89

90 Starting Cyclic Transmission ctrl_mnm1221_m() in mnm1221_m.c This process is to set a initial transmit data including MACID. Since this is for initial test, your proper process is needed. If you leave this as it is, clr_mnm1221_tx_mem() should be deleted to avoid duplicate initializing. Here, insert an interrupt enable function provided by yourself. Replace with TX data writing extracted from xchg_com_data(). 2012/1/31 Rev. 2 Page 90

91 In Running State ctrl_mnm1221_m() in mnm1221_m.c Delete this. Add the routine when timeout detected in RUNNING state. At that time, Servo-OFF must be commanded to all servos for safety. In RUNNING state, since the data exchanging is transferred to the interrupt, there is nothing to be done in main loop. Transfer this timeout detection into NC calculation interrupt. 2012/1/31 Rev. 2 Page 91

92 Data Exchanging xchg_com_data() in mnm1221_m.c unsigned long ul_temp; Put this function to the beginning of NC calculation interrupt. Transfer this to the end of NC calculation interrupt. Note this is for 16-bit bus. TX data writing for 16-bit bus ul_temp = MNM1221_M_DCRC_ERR_H; ul_temp <<= 16; ul_temp = MNM1221_M_DCRC_ERR_L; mnm1221.data_crc_err = ul_temp; If (!mnm1221.data_crc_err) { MNM1221_M_RXMEM_HOLD = 1; RX data reading for 16-bit bus } MNM1221_M_RXMEM_HOLD = 0; 2012/1/31 Rev. 2 Page 92

93 Data Exchanging (Cont.) Transfer this to the end of NC calculation interrupt. Note this is for 32-bit bus. TX data writing for 32-bit bus mnm1221.data_crc_err = MNM1221_M_DCRC_ERR; If (!mnm1221.data_crc_err) { MNM1221_M_RXMEM_HOLD = 1; RX data reading for 32-bit bus } MNM1221_M_RXMEM_HOLD = 0; 2012/1/31 Rev. 2 Page 93

94 XINTRX Interrupt Delete this. 2012/1/31 Rev. 2 Page 94

95 XINTRX Interrupt (Cont.) Delete this. Leave watchdog timer clear only. 2012/1/31 Rev. 2 Page 95

96 Appendix System Consideration for 2 times communication one NC calculation This system is not recommended because of longer delay in TX data flow. 2012/1/31 Rev. 2 Page 96

97 Timing Chart XSYNC Divided by 2 Com. period Because TX data flow has longer delay of one com period than NC = com system, this system is not recommended. IRQn of CPU NC period TX data flow R: Reading RX data W: Writing TX data NC Calculation Interrupt W R NC calculation W R NC calculation Com. Frame Data exchange Approx. Note TXD RXD XINTRX Note: At XSYNC falling edge, a frame has already been in transmitting, and the memory-bank switching after writing TX-data is deferred. Therefore the transmit timing is delayed for one communication period. 2012/1/31 Rev. 2 Page 97

98 BAD Example XSYNC Divided by 2 Com. period IRQn of CPU NC period End timing is unstable! NC Calculation Interrupt R NC calculation W R NC calculation W R: Reading RX data W: Writing TX data Com. Frame Data exchange Right flow Wrong update period! Wrong flow (Earlier timing) TXD RXD XINTRX If TX data writing is done at the end of NC calculation, the transmit timing can be shorter delay. However the data update period cannot be constant because the end timing is unstable. 2012/1/31 Rev. 2 Page 98