Power-Aware Scheduling for Embedded Real-Time Systems

Transcription

1 Power-Aware Scheduling for Embedded Real-Time Systems STEFAN OLOFSSON Master of Science Thesis MMK 2009:100 MDA 372 KTH Industrial Engineering and Management Machine Design SE STOCKHOLM

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3 iii. Master of Science Thesis MMK 2009:100 MDA 372 Power-Aware Scheduling for Embedded Real-Time Systems Stefan Olofsson Approved: Examiner: Supervisor: Martin Törngren Magnus Persson Commissioner: Contact person: Enea AB Barbro Claesson. Detlef Scholle Abstract. The main problem to solve in this master thesis project is to develop, and implement a dynamic voltage and frequency scaling scheduling algorithm, in a real-time embedded system. The main purpose with this algorithm is to enable the system to select the right voltage and frequency settings to reduce energy consumption. When the processor utilization is low, the processor can save energy by slowing down the processes execution and reduce processor idle time. The algorithm is implemented on a real-time operating system. It has been written for two different cases. One case is written for a system that simulate the frequency scaling, and one is written for real frequency scaling. The scheduling design is developed as a Rate Monotonic algorithm with fixed priority assignments. The dynamic voltage and frequency mechanism in this system is divided in two different parts. One of the parts are based on a static frequency algorithm, which make initially computation based on defined processes periods, and execution times. After this static frequency settings, the second part of the algorithm tries to decrease the frequency even more for more efficient energy savings. The technique is to decrease the frequency one step at a time at every new period for the lowest prioritized process. If the scheduler detect a deadline overrun, the current frequency and time relation to the hyperperiod is saved as not allowed frequency for this time stamp relative the hyperperiod. After a deadline overrun detection, the scheduler increases the frequency to avoid a domino effect of deadline overruns. The scheduling algorithm works as expected, it reduces the CPU idle time and makes computations on-line for frequency settings. The scheduling algorithm enables the system to select the right voltage and frequency settings to reduce energy consumption.

4 iv. Examensarbete MMK 2009:100 MDA 372 Energimedveten Schemaläggare för ett Inbyggt Realtidssystem Stefan Olofsson Godkänt: Examinator: Handledare: Martin Törngren Magnus Persson Uppdragsgivare: Kontaktperson: Enea AB Barbro Claesson. Detlef Scholle Sammanfattning. Fokus i detta examensarbete ligger på att utveckla en DVFS algoritm för en schemaläggare. Denna algoritm ska sedan implementeras i ett inbyggt realtidssystem. Huvudsyftet för DVFS algoritmen är att möjliggöra för systemet att välja rätt spänning och frekvens för att kunna minska systemets energiförbrukning. Om processoranvändandet är lågt, kan systemet spara energi genom att bromsa ner processernas exekveringstid och öka processoranvändandet. Algoritmen är implementerad på ett realtids operativsystem. Schemalägningsalgoritmen har skrivits för två olika fall. Ett fall är skrivet för ett system som simulerar frekvensskalning och ett fall är skrivet för ett system som har support för riktig frekvensskalning. Schemaläggarens design är utvecklad som en Rate Monotonic algoritm med fixt prioritering. Den dynamiska volt- och frekvens-skalnings mekanismen är uppdelad i två olika delar. Den första delen av algoritmen är baserad på en statisk frekvenskalningsalgoritm, som utför en initial beräkning baserad på processernas period och exekveringstid. Efter den statiska frekvens beräkningen, tar den andra delen av algoritmen över och försöker sänka frekvensen ytterligare för en mer effektiv energibesparing. Tekniken är att sänka frekvensen ett steg i taget för varje ny periodtid för den lägst prioriterade processen. Om schemaläggaren upptäcker en överstigen deadline, sparas den rådande frekvensen och tiden i förhållande till hyperperioden undan som icke tillåten frekvens för denna tid i förhållande till hyperperioden. Efter att schemaläggaren har upptäckt en överstigen deadline, ökas frekvensen för att undvika en dominoeffekt av överstigna deadlines. Den implementerade algoritmen beter sig som väntat, den ökar processoranvändandet och utför beräkningar under körning för att kunna sätta nya frekvenser. Algoritmen möjliggör för systemet att välja rätt spänning och frekvens för att kunna minska systemets energiförbrukning.

5 Contents Contents List of Figures List of Tables v viii x 1 Introduction Problem Statement Study scheduling theory Study power-aware scheduling Study Quality of Service (QoS) Method Limitations GEODES Project Use Case System requirements Scheduling Theory Introduction Real-Time Embedded Systems Hard Real-Time Soft Real-Time Scheduling definitions Definition of scheduling problems Scheduling algorithms First In First Out (FIFO) Round Robin (RR) Rate Monotonic (RM) Earliest deadline first (EDF) Comparison Between RM and EDF Implementation Context Switches and Runtime Overhead Overload And Blocking v

6 vi CONTENTS 3.7 Summary Power-Aware Scheduling Saving energy by computing actual execution time On-line vs Off-line Scheduling Dynamic Voltage and Frequency Scaling (DVFS) RT-DVFS Algorithms Static Voltage Scaling (SDVS) Cycle-Conserving RT-DVS (CCDVS) Look-Ahead RT-DVS (LADVS) Feedback Scheduling Feedback RT-DVS (FRTDVS) Summary Quality of Service QoS Specification Power Management Power and Performance Trade-off Power-Aware System QoS Levels QoS Manager Summary OSE Real-Time Operating System Processes Process States Inter-Process Communication Signals Semaphores Fast Semaphores Mutexes Summary Design and Implementation System Design Scheduling Design and Implementation RM Scheduling Implementation DVFS Scheduling Summary Verification Measuring Power Consumption Test Cases Simulated DVFS Test Case

7 CONTENTS vii Results Test Case Test Case Results Tests Case Test Case Real DVFS Test Case Results Test Case Conclusion and Future work Conclusion Problem Statement Requirements Future Work Bibliography 51 A Requirements 53 B Test Cases 55

8 List of Figures 2.1 Illustration of the use for mobile embedded technology in rescue work [8] Use case illustration Illustration of a job from a real-time task Preemption under RM scheduling Preemption under EDF scheduling Overload under EDF scheduling causing Domino Effect Permanent overload under RM Elastic Scheduling Feedback DVFS framework Task Splitting Process states Signal structure System design Priority queues for RM scheduling Flowchart for the scheduling algorithm Schematic of the power measurement Amount of CPU idle time for test case 1, with different configurations Amount of CPU idle time for test case 2, with different configurations Amount of CPU idle time for test case 3, with different configurations Power consumption for test case 3, with different configurations B.1 Test case 1: Figure A, shows the system running with configuration A. Figure B, shows the system running on configuration B. Figure C, shows the system running on configuration C B.2 Test case 1: Shows the number of hyperperiods needed to find the best suited frequency for the system running on configuration C B.3 Test case 2: Figure A, shows the system running with configuration A. Figure B, shows the system running on configuration B. Figure C, shows the system running on configuration C viii

9 List of Figures ix B.4 Test case 2: Shows the number of hyperperiods needed to find the best suited frequency for the system running on configuration C B.5 Test case 3: Figure A, shows the system running with configuration D. Figure B, shows the system running on configuration E. Figure C, shows the system running on configuration G B.6 Test case 3: Shows the number of hyperperiods needed to find the best suited frequency for the system running on configuration G

10 List of Tables 2.1 Use cases for rescue mission devises Scheduling algorithms Scheduling algorithms for DVFS Test case settings Test case settings Test case settings Status of the requirements A.1 Descriptions of the requirements x

11 Chapter 1 Introduction This is a master thesis, written at Enea during fall Enea is a global software and services company focused on solutions for communication-driven products. Enea has many years of experience to manage master thesis projects. During one project called DySCAS 1, the middleware SHAPE 2 was developed. This thesis is a part of the ITEA 3 project GEODES 4 [8]. This master thesis is about scheduling algorithms for a power-aware system, Quality of Service and power management. 1.1 Problem Statement The problem statement for this master thesis is to study and analyze different scheduling algorithms, power-aware scheduling and Quality of Service. A scheduling algorithm will be designed and implemented in the RTOS OSE. The algorithm shall be designed for power-awareness and power management Study scheduling theory Task scheduling is the basis of multi-programmed operating system. The scheduler s purpose is to switch the CPU between tasks in an effective way to make the system more productive. The basic scheduling concept has been studied for many decades, and there is a lot of literature in this area. What is the difference between different scheduling algorithms? This master thesis will cover the basic theories and go deeper in the research of task scheduling for real-time systems. 1 DySCAS Dynamically Self-Configuration Automotive System 2 SHAPE Self-configuring High-Availability Policy-based system for Embedded system 3 ITEA Information Technology for European Advancement 4 GEODES Global Energy Optimization for Distributed Embedded Systems, project number: ITEA2 <07013> 1

12 2 CHAPTER 1. INTRODUCTION Which of these scheduling algorithms is most suitable for real-time systems? Study power-aware scheduling Power-aware scheduling and dynamic voltage and frequency scaling, for embedded real-time systems is the main topic in this master thesis. The scheduler should be aware of the power consumption and be designed for power savings. How should a scheduling algorithm be designed to make the CPU better suited for power-awareness? Study Quality of Service (QoS) QoS can have different meanings in different context; in this project QoS refers to the relationship between energy consumption and performance. This master thesis will study the QoS concept in power-aware systems. How can QoS be integrated in the system to make it aware of its power consumption? 1.2 Method This master thesis project is divided in three phases. The first phase is aimed for an in-depth study to obtain as much knowledge as possible in the topic; power management for embedded systems with focus on task scheduling and power-awareness. This academic literature study will consist of reading books, research articles, technical manuals and earlier master thesis project. The second phase is for designing the scheduling algorithm and the third phase is for implementation and verification of the results from phase one and two. 1.3 Limitations The time limit for this the master thesis project is 20 weeks, and the first 10 weeks is dedicated for a literature study. The study is limited to CPU scheduling for realtime systems, with focus on algorithms suited for dynamic voltage and frequency scaling. Quality of Service in the sense of power and performance trade-off is also included in this master thesis literature study. The implementation part for this master thesis is limited to the DVFS scheduling algorithm. The hardware specific implementation for supporting DVFS is an ongoing project at Enea AB.

13 Chapter 2 GEODES Project The GEODES project [8] started September 2008 and ends September The aim of the project is to provide design techniques, embedded software and tools needed to prolong battery lifetime on mobile embedded systems, which has a rising functionalities and whose use is rising significantly. Mobile embedded technology can be useful in rescue works, to be able to analyze and organize the rescue situation from a central base placed at another location, figure 2.1 illustrate this technology. GEODES intends to cover the following aspects: Power-aware protocols; Power-aware operating systems; Middleware developments - in terms of QoS; Low power compilation; System-level modeling; Figure 2.1. Illustration of the use for mobile embedded technology in rescue work [8]. 3

14 4 CHAPTER 2. GEODES PROJECT 2.1 Use Case This section puts this master thesis project in a context. Imagine a rescue team out on a rescue mission, and the leading staff for this mission is placed at another location. To make it easier for the leading staff at the central base to analyze the situation at the location where the rescue work are taking place, the rescue team will be equipped with special technical devices that obtain useful information of the environment and send it to the central base, where the information can be analyzed and evaluated for further decisions. This device will also measure the physical condition on the team members and inform the leading staff. Use cases for mobile embedded devises developed for rescue missions are described in table 2.1. ID UC1 UC2 UC3 UC4 UC5 UC6 Description Give the exact location of the user with help of a GPS receiver Give information of the environmental temperature Give information about the person s heart rate Give information about the person s body temperature Send data to the central base Receive data from central base Table 2.1. Use cases for rescue mission devises. Figure 2.2 illustrate a user equipped with this technical device, obtaining useful information of the environment and the users physically condition and sending data to the central base. Figure 2.2. Use case illustration.

15 2.2. SYSTEM REQUIREMENTS System requirements Today s mobile embedded devices support increased functionality and need to run multi-programs on the processor. A result of this increasing complexity, power consumption has become an even bigger problem and power optimization is an important part in developing new devices. The GEODES project approaches this problem by considering all system levels in the concept of power-awareness. Many of these applications running on today s complex devises need to update frequently, and have timing constraints. This device for rescue workers mentioned above has requirements on weight and size because it has to be suitable for a rescue worker in action, which means that the size of the battery is limited. Functionalities on devices like this needs to be totally reliable and deliver right information on requests. This is a real-time embedded device that might handle both hard and soft deadlines. REQ1: The scheduling algorithm shall be designed for a Real-time system. REQ2: The system shall be able to handle multi-programs.

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17 Chapter 3 Scheduling Theory 3.1 Introduction CPU scheduling makes it possible to run multi-programs on single-processor systems, by switching the CPU time between processes. In a single-processor system there is only one task at the time that can be processed, all other tasks have to wait for the CPU to be free. A scheduling algorithm in a real-time system ensures that critical timing constraints such as deadlines and response time are met. In many real-time operating systems, priorities are assigned to tasks, and the task with the highest priority will be executed. This chapter starts with some definitions of realtime systems and scheduling. Some basic scheduling algorithms are described. The purpose of this chapter is to summarize and compare different scheduling algorithms, and come up with a conclusion, when and where different algorithms are appropriated. 3.2 Real-Time Embedded Systems Real-time system means that the correctness of the system depends not only on the logical result of the calculation but also on the time at which the results are produced. An example of a real-time system could consist of a controlling system and a controlled system. The controlling system interacts with its environment based on the information available about the environment from sensors attached to it. An embedded system is a computer system that is part of a larger system and performs some of the requirements of that system [12] Hard Real-Time In a hard real-time system time constraints are critical, and missing a deadline can cause catastrophic consequences. A hard real-time task could be a controller of a safety critical system, and if a single deadline is missed, the system is considered to 7

18 8 CHAPTER 3. SCHEDULING THEORY have failed. An example of a hard real-time embedded system could be a medical device as heart pacemakers Soft Real-Time In a real-time system where meeting deadlines are desirable, but not critical, the deadlines are considered to be soft. By missing deadlines, the system s quality could be deteriorated, but not jeopardize the systems stability or cause catastrophic consequences. A desktop computer is a good example of a system with soft deadlines. While a user typing letters with the keyboard, the user perceives that the letters show instantly in the editor on the screen, this may not be the case because a human cannot see delays under a few milliseconds. 3.3 Scheduling definitions To be able to describe task scheduling, there are some basic terminologies that have to be clarified. Here is a list of some basic concepts and terminologies in task scheduling [2][9][10]. Release time r: The time when a task becomes ready for execution. Absolute deadline d: Is the time when a task should be completed. Relative deadline D: Deadline relative to the task s release time. Computation time C: Is the worst-case execution time of a task. Start time s: The time a task starts its execution. Finishing time f: The time a task finishes its execution. A job J: A job is an instance of a task. Lateness L: Represent the delay of a task completion with respect to its deadline. Period T: The period of a task. Synchronous periodic tasks: Synchronous periodic tasks are when all first job of a periodic task set are released at the same time. Asynchronous periodic tasks: Asynchronous periodic tasks are when all first job of a periodic task set are released at different time. Response time R: Difference between the finishing time and the request time. Slack time X: Is the amount of time left to a tasks deadline after execution.

19 3.4. DEFINITION OF SCHEDULING PROBLEMS 9 Utilization U: Utilization factor is the fraction of processor time spent in the execution of the task. If the utilization factor is 100% then the CPU load is 100%. The utilization factor is given by equation 3.1 U = n i=1 C i T i (3.1) Figure 3.1 illustrate an execution of a job from a real-time task. Figure 3.1. Illustration of a job from a real-time task. 3.4 Definition of scheduling problems According to Buttazzo [2], scheduling problems can be defined by three sets, number of tasks, number of processors and types of resources. Many embedded real-time systems handle both hard and soft deadlines, and may need to work with both periodic and aperiodic tasks. The scheduler s main purpose is to find a schedule for the tasks that fulfil the systems requirements. Here are some definitions commonly used in task scheduling [2][9][10]. Static: Static scheduling algorithms are based on fixed parameters. In static scheduling the algorithm has complete knowledge of a task s deadline, computation and future release time. Dynamic: Dynamic scheduling algorithms are based on dynamic parameters that can change during runtime, the scheduler need to compute absolute deadlines between each instance of a task, and knowledge of new release times are not known. Preemptive: With preemptive algorithms, a running task can be interrupted at any time by another task with higher priority.

20 10 CHAPTER 3. SCHEDULING THEORY Non-preemptive: With non-preemptive algorithms, a running task cannot be interrupted, it will be executed until completion. The CPU is allocated to a process until it releases the CPU. On-line: A scheduling algorithm is used on-line if decisions are taken during runtime. Off-line: A scheduling algorithm is used off-line if all scheduling calculations are made before runtime. Periodic And Aperiodic Task Handling: A real-time system can obtain both periodic tasks with hard deadlines and soft aperiodic activities, in this case the scheduler need to ensure all hard deadlines, and make sure that the soft activities get as much runtime as possible to ensure the systems quality. 3.5 Scheduling algorithms Developing algorithms for task scheduling is a popular topic among researchers; it is a versatile topic with mathematical challenges. Many of today s scheduling algorithms are based on a few basic algorithms. One of the best known dynamic priority assignment scheduler, is the Earliest Deadline First (EDF) [4] and for static priority it is Rate Monotonic (RM) [4]. Round Robin (RR) is often used for scheduling time-shared applications. Another popular algorithm is First In First Out (FIFO) First In First Out (FIFO) FIFO is a scheduling algorithm of non-preemptive type, and the process that requests the CPU first will allocate the CPU first. The process that is running will finish completely before moving on to the next. When a new process comes in, it will be added to the queue, when the running process is finished, dequeue the process from the ready queue and run it. One advantage with FIFO is that it is easy to implement, one problem is that one process can occupy all CPU time, because each task occupies the CPU until it is finished. FIFO can be combined with other algorithms, like RM Round Robin (RR) Round Robin is a time-sharing algorithm, where all processes are given a small unit of time to allocate the CPU. When all tasks have got their time slice, the first task gets back into the CPU for its next processing. Round robin is quite easy to implement and a commonly used algorithm in operating systems. One problem with RR is to decide the size of the time slice, if the time slice is too long it may cause long response time and the system will behave slow, too short time slice causes many context switches, which are expensive to execute for the CPU.

21 3.6. COMPARISON BETWEEN RM AND EDF Rate Monotonic (RM) Rate Monotonic scheduling algorithm was introduced in 1973 by Liu and Layland [4]. In Rate Monotonic scheduling, the task with the shortest period has the highest priority. With a fixed priority assignment, the priorities are assigned before execution. RM is a preemptive algorithm; a running task can be preempted of a new incoming task with a shorter period. Rate Monotonic is optimal (for the Liu & Layland model [4]) among all fixed-priority assignments, in the sense that no other fixed-period algorithms can schedule a task set that cannot be scheduled by Rate Monotonic [2]. A set of periodic tasks can be scheduled with RM if the total utilization is equal or less then the schedulable utilization of the algorithm, see equation 3.2 for the schedulable utilization. n i=1 C i T i n(2 1 n 1) (3.2) The schedulability condition for RM is a function of the number of tasks, the bound decreases when the number of tasks increases. Equation 3.3 shows the converging bound when the number of tasks goes towards infinity Earliest deadline first (EDF) lim n(2 1 n 1) = ln (3.3) n EDF is a dynamic algorithm, different from RM where priorities are fixed, scheduling is made at runtime. Scheduling with EDF focuses on the task s deadline, the task with the closest deadline will be executed first. Compared to fixed-priority scheduling like RM, EDF has a schedulable utilization equal to the CPU utilization factor see equation 3.4. Scheduling with EDF does not require periodic tasks, the only requirement is that all tasks are finished before its deadline. Theoretically, EDF scheduling is optimal, it can schedule tasks so all tasks meat their deadlines, and the CPU utilization can be 100%. n i=1 C i T i 1 (3.4) According to the optimal theorem of Dertouzos [15] The earliest deadline first algorithm is optimal in the sense that, if there exist any algorithm that can build a valid (feasible) schedule on a single processor, then the earliest deadline first algorithm also builds a valid (feasible) schedule. 3.6 Comparison Between RM and EDF Of the algorithms mentioned above, RM and EDF are most suitable for real-time systems, especially hard real-time system [18]. In hard real-time the scheduler need

22 12 CHAPTER 3. SCHEDULING THEORY to be preemptive to ensure all real-time tasks to finish before their deadline. Both RM and EDF are preemptive algorithms, the big different between them are that with RM task are assigned fixed priorities and with EDF dynamic priorities Implementation In real-time systems, RM is probably the most used algorithm. It seems to be easy to implement on top of an operating system kernel, RM can be implemented just by assigning a fixed priority inversely proportional to its period for each task. To implement a dynamic priority algorithm like EDF, demand more from the kernel. The scheduler must keep track of all absolute deadlines and perform a dynamic mapping between absolute deadlines and priorities. It is easier to implement EDF on a kernel that support time and deadline management. With an EDF scheduler implemented on the kernel, it would improve the systems performance by its dynamic behavior. According to Buttazzo[3] in the article Rate Monotonic vs. EDF: Judgment Day only a few research kernels support EDF as a native scheduling scheme Context Switches and Runtime Overhead With EDF scheduling the absolute deadline needs to be updated for each job of a task, for RM the priority is based on the tasks period and does not need to be updated between one job to another. According to computation of absolute deadline during runtime, EDF causes more runtime overhead than RM. From another point of view taken context switches into account, RM need to preempt execution more frequently than EDF. Figure 3.2 and figure 3.3 illustrate two tasks scheduled with RM and EDF, in this example task T 1 has a period of 5 time units and an execution time of 2 time units, task T 2 has a period of 7 time units and an execution time of 4 time units. The figures show one hyper period for the two tasks. With RM T 1 need to preempt T 2 in every instance, with EDF T 2 is only preempted ones. Figure 3.2. Preemption under RM scheduling Overload And Blocking Overload condition in real-time scheduling is a critical situation and causes task to miss their deadlines. In a hard real-time system this may cause critical consequences. Overload condition can occur by some execution time exceeds its expected time or

23 3.6. COMPARISON BETWEEN RM AND EDF 13 Figure 3.3. Preemption under EDF scheduling. a new higher priority task arrives. Tasks with fixed periods scheduled by EDF occur to get their periods a multiple longer than their regular period. The new average period is given by T i = T i U, where U > 1 and the CPU utilization is given by equation 3.1. Figure 3.4 shows how a feasible schedule task set by EDF can be unscheduled and all tasks miss their deadlines if a new task arrives, this phenomenon is called domino effect [3][9]. Figure 3.4. Overload under EDF scheduling causing Domino Effect. Under fixed priority scheduling like RM, a task with low priority could be completely blocked by a higher priority. Permanent overload condition is when the CPU s utilization is over 100 %, figure 3.5 shows a periodic task set with a permanent overload condition scheduled by RM. It can be seen that T 3 which has the lowest priority, never gets any CPU time, this phenomenon is called starvation and is when one or more tasks totally allocate the CPU from another task to run.

24 14 CHAPTER 3. SCHEDULING THEORY Figure 3.5. Permanent overload under RM. 3.7 Summary Developing scheduling algorithms for computers and embedded real-time systems is a popular topic among researchers in computer engineering. There are many different aspects to consider when choosing an algorithm, or the way of developing a new algorithm. This chapter gives definition on real-time systems and CPU task scheduling, and explains some different algorithms and compares them with each other. This thesis is mostly about real-time systems, and because the two algorithms EDF and RM are best appropriated for real-time scheduling, there is a deeper comparison between these two algorithms. The comparison is about implementation complexity, runtime overhead and CPU overload. In table 3.1 there is a summarized conclusion about the compared algorithms. REQ3: The scheduling algorithm shall be of preemptive type. REQ4: The algorithm shall be implemented on an operating system with a preemptive kernel.

25 3.7. SUMMARY 15 Algorithm Characteristic Fulfilled REQ FIFO Non-preemptive Easy to implement Can be combined with RM RR Divides CPU time in time slices Easy to implement Starvation free Short time slice; many context switches Long time slice; slow system RM Preemptive REQ3 Static priority assignment Easy to implement Common for real-time systems REQ1 Can use FIFO queues, one for each priority Less runtime overhead than EDF EDF Preemptive REQ3 Dynamic priority assignment Hard to implement Suited for real-time systems REQ1 Optimal algorithm High utilization Table 3.1. Scheduling algorithms

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27 Chapter 4 Power-Aware Scheduling Power-aware scheduling is a significant part of real-time embedded systems, one big issue with battery powered embedded systems is power consumption. One way to reduce power consumption is to use a CPU that supports multiple voltage and frequency settings for Dynamic Voltage Frequencies Scaling (DVFS) technique. When CPU utilization is low, the CPU can save energy by slowing down the task execution. The purpose of DVFS scheduling is to enable the system to select the right voltage and frequency settings to reduce energy consumption. Today s technical devices include a lot of advanced functionality and it will always be a trade-off between power and performance when developing new devices. This chapter discusses task scheduling regarding power saving and power-awareness, some scheduling techniques and algorithms for DVFS are presented and evaluated based on the requirements given in Appendix A. The two must studied algorithms for real-time systems are RM and EDF, which both are preemptive, RM has a fixed priority assignment and EDF has a dynamic priority assignment. These algorithms are described and compared in chapter Saving energy by computing actual execution time WCET is the predicted, longest computation time for an instance of a real-time task. Statistically the actual execution time for a task is much shorter then its WCET, this result gives an underutilized CPU and this slack time can be used for energy savings. Either by slowing down the CPU frequency, if the system support dynamic adjustment of frequency, or let another task allocates the CPU for execution to guarantee deadlines. 4.2 On-line vs Off-line Scheduling The actual execution time cannot be predicted in advance, Off-line DVFS scheduling uses the WCET for computing suitable frequency for the CPU, which could be pessimistic for some real-time embedded systems. With on-line techniques the 17

28 18 CHAPTER 4. POWER-AWARE SCHEDULING scheduler are more flexible and frequency optimization can be efficiently made during runtime, and DVFS settings can be selected by using information of actual execution time, only available at runtime. 4.3 Dynamic Voltage and Frequency Scaling (DVFS) DVFS is a useful mechanism for embedded systems designed to provide high peak performance when needed, and reduce power consumption by dynamically reducing operating frequency for the CPU. By lowering the CPU frequency one can also lower the voltage supply, which reduces the power consumed by the CPU [1][6][5][14][17]. To dynamically change frequency on a processor, it needs to have support for dynamic frequency scaling. With this DVFS module one can use slack time to lower the frequency. By knowing how much slack time there is available in the system, the scheduler can stretch the execution time, and still meet all deadlines. Figure 4.1 shows two tasks running on different speed. At full speed, the execution time is as small as possible, but it gives a lot of slack in the system and the CPU utilization is quite low. When the two tasks are running on half the speed, the execution time of the tasks becomes longer, but the two tasks deadlines are still meet. Figure 4.1. Elastic Scheduling.

29 4.4. RT-DVFS ALGORITHMS RT-DVFS Algorithms Many articles and literature about DVFS scheduling [1][6][5][21][22][20][11][19], refer to one specific article by P. Pillai and Kang G. Shin [17]. In this article they presented three different online, dynamic techniques for scheduling real-time applications on a CPU supporting dynamic voltage and frequency scaling. These algorithms are more like modules to the traditional algorithms RM and EDF. The advantage with their online technique is that the actual execution time can be measured at runtime and used for selecting DVFS settings, as mentioned earlier the WCET is quite pessimistic. Their three techniques assume a real-time system with n periodic tasks with period T i, WCET C i, relative deadline D i assumed to be equal to its period and its absolute deadline is d i Static Voltage Scaling (SDVS) The static voltage scaling under EDF or RM sets the processor s frequency to the lowest possibly that still guarantee that all deadlines will be met. The clock frequency does not change during runtime; the amount of static slack available is given by the computed utilization based on the worst-case execution time. The necessary and sufficient schedulability test for EDF is given by equation 3.4. This test requires that total utilization for the task set is less then 1. To find the lowest CPU clock frequency f k that still meet all deadlines, the utilization is compared with a scale factor α see equation 4.1, α is given by f k f max f k {f 1,..., f max }. n i=1 C i T i α (4.1) The selected frequency is the lowest one that fulfills the schedulability test, the voltage is changed to match the operating frequency and reduce energy consumption as much as possible Cycle-Conserving RT-DVS (CCDVS) Real-time task sets are usually specified with WCET, but real time tasks use much less than worst case most times. This phenomenon gives an opportunity to reduce energy consumption by reducing operating frequency. In CCDVS the utilization is recomputed after every task in a task set by using the actual execution times of the computed task, and this is repeated for the whole task set. With this online technique, the actual execution time for the task that have completed can be compared with the worst case execution time for released tasks. If there is any unused time, the operating frequency can be reduced instead of idling the processor. With this algorithm the frequency can be changed during runtime, and can reduce frequency in each task completion. The main challenge in designing this algorithm is to ensure that deadline guarantees are not violated when the operating frequencies are

30 20 CHAPTER 4. POWER-AWARE SCHEDULING reduced [11]. The schedulability test for CCDVS can be implemented under both EDF and RM scheduling Look-Ahead RT-DVS (LADVS) Look-Ahead technique, as it sounds tries to predict the future and uses a look-ahead technique, to determine future computation need and set the frequency as low as possible. This may require a higher speed at a later time, to be able to finish all work in time. As mentioned earlier, tasks actual execution times is often much smaller than the WCET, the processor may not need to work at a higher speed to finish in time. This algorithm allows the system to operate at a low frequency while completing all tasks in time. The big difference from CCDVS is that LADVS doesn t assume the WCET initially and execute at a high frequency until some tasks completes. The look-ahead algorithm sets the operating frequency to meet the minimum work that has to be done now to ensure that all future deadlines are met. LADVS better estimates how much slack is available and results in lower power consumption than both CCDVS and SDVS, according to [17][6][5] 4.5 Feedback Scheduling Feedback scheduling is a technique to keep track of computation time, deadline and slack in the system [1][21][22]. In a dynamic system the scheduling algorithm does not have complete knowledge of the task set and its constraints. Feedback scheduling algorithms are designed based on feedback control theory, an aggressive technique to dynamically adjust operating frequency to reduce supply voltage. Traditional algorithms are usually based on offline analysis, with feedback scheduling the analysis is made during runtime. Figure 4.2 illustrates how a Feedback DVFS framework could look like. Figure 4.2. Feedback DVFS framework.

31 4.6. SUMMARY Feedback RT-DVS (FRTDVS) In Zhu and Mueller s article [21] they presented a power-aware feedback schemes for DVS algorithms based on EDF scheduling. Based on previous computations, this feedback algorithm gives information to the scheduler about actual execution time. With a DVS module for the CPU, the frequency can be scaled and work at a different speed. By dividing the task in two parts T A and T B and run them at different frequencies, energy consumption can be reduced for the system. The idea is to start with as low frequency as possible for T A and run T B with maximum frequency to ensure that the task is finished before its deadline. This calculation is based on the tasks WCET, why the execution of a task will probably be finished during subtask T A. This is illustrated in figure 4.3. The scaling factor α for the frequency, which T A runs on is given in equation 4.2. s k is the available slack to the task derived from its WCET. Figure 4.3. Task Splitting. α = C A C A + s k (4.2) This feedback scheduling algorithm keeps the CPU utilization under 100% even with scaled frequency, and ensure constraints for real time deadlines. 4.6 Summary This chapter has presented power-aware scheduling and dynamic voltage and frequency scaling for real-time embedded systems. Scheduling techniques that benefit the ability to dynamically adjust the execution time of a running task must run on a CPU designed with a mechanism that supports DVFS. Four different algorithms that modifie RM and EDF to run on real-time systems that support DVFS, have been presented in this chapter. The first algorithm SDVS different from the other three, compute the frequency statically and use WCET. The other three algorithms CCDVS, LADVS and Feedback RT-DVS EDF use the actual execution times that

32 22 CHAPTER 4. POWER-AWARE SCHEDULING are computed dynamically during runtime. conclusion about the presented algorithms. In table 4.1 there is a summarized REQ5: The algorithm shall be designed for on-line computation and keep track of deadline overruns. REQ6: The system shall be designed for power-awareness, with ability to change frequency during runtime. Algorithm Characteristic Fulfilled REQ SDVS Designed for DVFS REQ6 Use off-line technique Compute frequency based on WCET For both RM and EDF CCDVS Designed for DVFS REQ6 Use on-line technique REQ5 Compute frequency based on actual execution time For both RM and EDF LADVS Designed for DVFS REQ6 Use on-line technique REQ5 Compute frequency based on actual execution time More aggressive than CCDVS FRTDVS Designed for DVFS REQ6 Use on-line technique REQ5 Compute frequency based on actual execution time Table 4.1. Scheduling algorithms for DVFS

33 Chapter 5 Quality of Service Quality of service is a widely used concept and can have different meaning in different contexts, in computer networking it is about guarantee a certain level of performance for a system, and the possibility for a sent package to reach its destination. In this thesis, the term QoS will refer to the trade-off between power and performance. In battery-powered embedded systems, the energy consumption is a very important issue. The expectation of today s technical devices is very high, both in performance and battery lifetime, the aim of QoS is to lower the energy consumption and still fulfill the requirements on quality and performance. This chapter is about QoS and power management, there is a section that explains the tradeoff between power and performance in an embedded system. The study regarding power-aware system is presented in one section. 5.1 QoS Specification As mentioned above, the concept QoS is widely used and therefore its specification is different in different context. The design of a computer system can be represented as different layers, which goes from hardware to application. Application: Specified to: power-awareness in user level. Middleware: Specified to: modules that works as links between application and OS. Operation system: Specified to: power-aware scheduling, real-time support and resource management. Hardware platforms: Specified to: CPU supporting DPM and DVFS, memory/buffers and devices. 23

34 24 CHAPTER 5. QUALITY OF SERVICE 5.2 Power Management The method to manage power consumption in a system is called power management, for example when a cell phone or a laptop switches to sleep mode to save energy, when it has been inactive for a while. The purpose with power management is to prolong battery lifetime and reduce heat in a system. Power management can be performed either statically or dynamically. Static management is performed during the design phase of a system and optimization of power management is done offline. It is easier to guarantee the QoS constraints with static management, but the energy saving performance is rather limited. Dynamic power management can be performed during runtime and optimization can be done on-line, system components are put into different states, representing an energy consumption level, and ability to put components in power saving mode during runtime [16]. 5.3 Power and Performance Trade-off Power consumption in an embedded system has a direct affect on both performance and battery lifetime. To ensure long battery lifetime for a system, it has to operate at low power and low frequency, to obtain high performance it has to operate at a high frequency, which means higher power. Depending on application and purpose, the system can change between the two states, good performance or long battery lifetime. Power is proportional to the square of the supply voltage, se equation 5.1 where P is power, C is load capacitance, V is supply voltage and f is CPU clock frequency, therefore by reducing supply voltage a lot of power can be saved [13]. P = CV 2 f (5.1) Another issue is current leakage, which is affected of switching between different states in a CMOS circuit; by lowering the supply voltage the switching energy consumption decreases. The trade-off here is that delays in the system increases when supply voltage decreases, in other words the execution time for a software task increases and may affect system performance. One of the big challenges with task scheduling for power-aware system is to schedule all tasks with as low energy consumption as possible, and still guarantee a good performance and meet timing requirements. 5.4 Power-Aware System A power-aware system has to provide the right amount of power at the right place and at the right time. To reduce energy consumption in a system it should be designed in a way that make the system aware of its energy consumption. One way to reduce energy consumption is to use a CPU that supports dynamic frequency

35 5.4. POWER-AWARE SYSTEM 25 scaling, and let the CPU scheduler compute the best-suited frequency for saving energy and still guarantee a good performance in the system. The aim of a poweraware scheduler is to benefit the system,s power manageable resources and switches between different energy-saving modes. Or shutting down the CPU when it is idle, which is known as dynamic power management as mentioned above QoS Levels QoS can be related to the number of met deadlines of a task set in a real-time system, it can be a measurement of the systems robustness and quality. A control application that runs in a control system is a good example to illustrate this. If the control system requires a very robust and exact output, then the system can be considered to be a hard real-time system with a high QoS level. Scaling down the CPU frequency, to saving energy may not be the case, the schedulers assignment should be to find the best frequency to guarantee all deadlines. On the other hand, if the application has soft characteristics and allows a few missed deadlines, then the system allows a little less QoS in the sense of robustness and quality, and lets the scheduler find a lower frequency for the task set. Scheduling for soft real-time application can be divided in two techniques, best effort and guarantee techniques [11], which reflect earlier statements on power and performance trade-off. With best effort the scheduler s purpose is to minimize power consumption and maximize the QoS, but not guarantee either of them. If the scheduler s aim is to optimize energy consumption and guarantee QoS level, it uses the guarantee approches. Linwei Niu et al. [14] presented a model for task scheduling with QoS requirements, this model has a so called (m, k)-constraints, which require that at least m out of k jobs of a task meet their deadlines. With this model different tasks can be assigned different QoS levels QoS Manager A QoS manager can be implemented in a system as a mechanism that supplies modules with information about system parameters, such as deadline overrun, actual execution time or CPU clock frequency. Two of the most critical factors in a realtime system are energy consumption and QoS guarantees. If a computer platform is designed for power-awareness, it needs to have different modules implemented to manage and distribute system parameters. A QoS manager can work as a local manager in a module for the system or as a global manager to distribute information between modules.

36 26 CHAPTER 5. QUALITY OF SERVICE 5.5 Summary The widely used concept QoS is presented in this chapter in the context of power and performance trade-off. Energy consumption is a big issue for developing new technology with high performance and quality. One way to manage this problem is to design the computer platform with a power-aware concept, and implement QoS in the systems different layers. The task scheduler should be suited for powerawareness and modified with DVFS technique. QoS can be measured with different levels, in this chapter two techniques for handle QoS are presented, best effort and guarantee technique.

37 Chapter 6 OSE Real-Time Operating System OSE is an embedded real-time operating system developed at Enea AB. OSE is based on a microkernel architecture. All OSE implementations are fully preemptive, and interrupts are managed using interrupt processes. This chapter gives a brief description of the real-time operating system OSE, focused on functionalities relevant for this master thesis. The facts in this chapter are mainly obtained from the OSE user manual [7]. 6.1 Processes Processes are fundamental building block in OSE. A process in OSE is similar to tasks and threads in other operating system. OSE uses processes to allocate CPU time for different jobs. A process can be either static or dynamic. A static process is created at the system start be the kernel, or at the start of a load module. A dynamic process is created in run-time, and can be configured and killed in run-time. There are five different types of processes available in OSE [7]. Interrupt Processes Timer-Interrupt Processes Prioritized Processes Background Processes Phantom Processes Interrupt Processes: Interrupt processes executes without being blocked, interrupt processes are not allowed to use blocking system calls. Interrupt processes are the highest prioritized processes in an OSE system, interrupt processes can only be preempted by another interrupt process with higher priority. Interrupt processes are invoked by hardware interrupt or software event [7]. 27

38 28 CHAPTER 6. OSE REAL-TIME OPERATING SYSTEM Timer-Interrupt Processes: A timer-interrupt process act the same way as ordinary interrupt processes, but are called periodically by the system-timer process. A timer-interrupt process is created with a specified period, which is a multiple of the system-tick length. The system-tick length can be configured in different length [7]. Prioritized Processes: The most commonly used process types in OSE are prioritized processes [7]. Every prioritized processes created in OSE must be specified with a priority, the priority can be changed during run-time with a system call. Prioritized processes are written as infinite loops. Background Processes: Background processes runs in the background, in a strict time-sharing mode at the lowest priority level when no interrupt, timerinterrupt or prioritized processes are ready. Phantom Processes: Phantom processes have no program code, and need very little memory. Phantom processes are not real processes, phantom processes are used as place holders Process States OSE processes can be in three different states, and are always in one of them [7]. The three states are running, ready and waiting see figure 6.1. Only one process can be in the running state at the time, the running state is when the process is being executed in the CPU. A process in the ready state is ready to run, but a higher prioritized process is running. A process in waiting state is waiting for some event to happen or has been stooped by a system call. Ready stop preemption send start dispatch Waiting recesive Running send start Figure 6.1. Process states.

39 6.2. INTER-PROCESS COMMUNICATION Inter-Process Communication The recommended way for communication between processes is to use signals. There are three different communication mechanisms available under OSE; signals, semaphores, and fast semaphores Signals A signal is a message from one process to another, and the signal contains information to the destination process. The signal also contains attributes that are set by the operating system, these attributes keeps track of the sender and the receiver. A process has one signal queue that is created by the kernel and is administrated by the kernel [7]. Only the owner of the signal can modify the contents of the buffer, when the receiving process receives the signal, it becomes the owner of the signal. Before a signal can be sent, it must be allocated. All signals consist of three or four blocks; administration block, signal block, data field (optional) and an end mark se figure 6.2. Administration block Signal number Data Field (optional) End mark Figure 6.2. Signal structure Semaphores A semaphore is a mechanism that works as a flag to indicate different states. It is only possible for processes in the same memory domain to share a semaphore. The purpose with semaphores is to protect shared resources between processes, a process lock a semaphore with a wait call, and unlock with a signal call. OSE uses counting semaphores, each semaphore has a value [7]. If the value is less then zero, a waiting process is blocked until the semaphore is signaled by another process. When a semaphore is signaled, the resource will be given to the next process in its waiting queue Fast Semaphores Fast semaphores are just like ordinary semaphores, except that fast semaphores have an owner. In OSE all processes have a built-in fast semaphore. A fast semaphore can be signaled by a process outside the domain. An interrupt process sets its state to ready, by signaling the fast semaphore [7].

40 30 CHAPTER 6. OSE REAL-TIME OPERATING SYSTEM Mutexes Mutex (Mutual Exclusion) like semaphores, used to protect shared objects. A difference between mutexes and semaphore in OSE is that the mutexes can be used from user mode. Processes have to be in the same domain to share mutexes. 6.3 Summary All OSE implementations are fully preemptive, which fulfills REQ6 see chapter 2. This chapter gives a brief description of the real-time operating system OSE, focused on functionalities relevant for this master thesis. The system design, and system implementation for this master thesis is made for an OSE system.

41 Chapter 7 Design and Implementation This chapter will describe the design and implementation of the DVFS scheduling algorithm. The algorithm is implemented on Enea real-time operating system OSE5.4, and running on a Freescale i.mx31 ADS development board. The scheduling algorithm is implemented as a separate module on the OSE system, the OSE kernel has not been modified. This master thesis is limited to the DVFS scheduling algorithm, and the CPU specific drivers for DVFS is an ongoing, project at Enea. This scheduling algorithm has been written for two different cases. One case is written for simulating the frequency scaling, and one is written for real frequency scaling. The decision to implement a RM scheduling algorithm in the system was taken on the basis of the scheduling principle in OSE. The part of the algorithm that handles DVFS settings is based on the DVFS algorithms described in chapter 4. All on-line computation for execution time and frequency settings are an own developed algorithm. The initially schedulability test for frequency settings made in this system are taken from the algorithm (SDVS) developed by P. Pillai and Kang G. Shin [17], which is described in chapter 3. The SDVS algorithm was chosen because it s well suited for real-time systems, and quite easy to implement. SDVS is a good choose for initially computations, which make the system to start on the lowest possible frequency that guarantees all processes deadlines. 7.1 System Design The system developed in this master thesis project, is designed for an OSE system, and implemented as a module that can be loaded with the OSE kernel. This module is divided in five different parts. These parts are implemented in OSE as different processes, the first part is called the Timer process, which is a timer-interrupt process that will execute at every system-tick. The system-tick length is configured to one millisecond. At every system-tick the Timer process sends a signal to a high prioritized process called Scheduler, which is the scheduler for this system. The third part is called Procs, where the scheduled processes are implemented as prioritized processes with different priorities, all with lower priority than Scheduler. 31

42 32 CHAPTER 7. DESIGN AND IMPLEMENTATION The fourth part is called Printer, which also is a prioritized process with low priority. Printer gets signals from Scheduler and Procs with information about execution time, periods, deadline overruns and frequency. Printer handles this information and prints it on the screen. The printed data can be used in MATLAB for analysis purposes. The fifth part is implemented as a prioritized process called DVFS_slave. DVFS_slave is a process prepared to handle system calls for frequency scaling, this process is not in used for the system simulating frequency scaling. See figure 7.1 for the system design. Figure 7.1. System design 7.2 Scheduling Design and Implementation The scheduling design is built on a RM scheduling algorithm. The scheduler is written as an OSE prioritized process, with the highest priority, see chapter 6 about process types. And the processes that have to be scheduled are also written as prioritized processes. In this way the implemented scheduler uses existing OSE scheduling policies, which made the implementation much easier and more time could be dedicated to developing the DVFS scheduling algorithm and focus on the main topic in this master thesis; introducing power-awareness to the system.

43 7.2. SCHEDULING DESIGN AND IMPLEMENTATION RM Scheduling Implementation RM scheduling is described in chapter 3. OSE has fixed priority-based scheduling policies, which means that the process with the highest priority will always be running when it s ready. The RM scheduling is implemented by assigning the processes priority based on period, highest priority for the process with the shorts period and so on. OSE uses preemptive scheduling, which means that the operating system can preempt a currently running process at any time if another process with higher priority is ready. The principle for the implemented RM scheduler is illustrated in figure 7.2. Priority Ready Running Waiting Hihg Low Figure 7.2. Priority queues for RM scheduling The scheduler keeps track of system time, and sends signals to the different processes when each period starts. Signals in OSE can include information for the receiver, which are described in chapter 6. The signal sent from the scheduler includes information about the receiving process execution time. When a process gets the signal from the scheduler it registers the start time and starts to execute, when it is finished, it registers the stop time, and sends a signal back to the scheduler with its actual execution time DVFS Scheduling The DVFS scheduling mechanism are divided in two different parts. One of the implemented parts are based on a static voltage scaling algorithm SDVS introduced by P. Pillai and Kang G. Shin [17]. This algorithm is described in chapter 3. The purpose of this algorithm is to initially find the lowest frequency as possible that still guarantee all processes deadlines, which in this case are each process period. The schedulability test in this algorithm uses the processes periods and WCET to compute the frequency for the CPU. The algorithm is divided in two functions, see Algorithm 1.

44 34 CHAPTER 7. DESIGN AND IMPLEMENTATION Algorithm 1 Static Voltage Scaling 1: RM_test(α) 2: if T i ɛ{t 1,, T n P 1... P n } P i /P 1 C P i /P 1 C i α P i then 3: return TRUE 4: else 5: return FALSE 6: end if 7: selectfrequency: 8: use lowest frequency f i ɛ{f 1,..., f m f 1 <... < f m } 9: such that RM-test(f i /f m ) is true. After this initially frequency settings, the second part of the implemented algorithm tries to decrease the frequency even more for more efficient energy savings. The technique is to run the higher prioritized processes on the computed initial frequency, and decrease the frequency when the lowest prioritized process is running. The scheduler decreases the frequency one step at the time, at every new period for the lowest prioritized process. When the running process has finished its execution, it sends a signal back to the scheduler with its actual execution time. This makes it possible for the scheduler to keep track of deadline overruns. If the scheduler detects a deadline overrun, the current frequency, and time in relation to the hyperperiod is saved as not allowed frequency for this time stamp relative the hyperperiod. After deadline overrun detection, the scheduler increases the frequency to avoid a domino effect of deadline overruns see chapter 3. The scheduler keeps on with this technique to find the lowest possible frequency for each period sequence for the lowest prioritized process. In this way the system will find the best, suited frequencies for the process set, and after a few hyperperiods, all processes deadlines will be met, and the systems power consumption is reduced. Algorithm 2 describes the main functions of the algorithm. The implemented system with its different parts and main functionalities are illustrated in figure 7.3

45 7.2. SCHEDULING DESIGN AND IMPLEMENTATION 35 Algorithm 2 On-line frequency computations 1: procedure ComputeFrequency(P i,t imestamp,f requency) 2: if deadlineoverrun then 3: N otallowedf requency[i] F requency 4: AtT ime[i] T imestamp 5: SetN ewf requency(up) 6: else 7: SetN ewf requency(down) 8: end if 9: end procedure 10: procedure SetNewFrequency(P i,f requency, UpOrDown) 11: if F requency_1 then 12: if Up then 13: F requency F requency_2 14: end if 15: else if F requency_2 then 16: if Up then 17: F requency F requency_3 18: else 19: F requency F requency_1 20: end if 21: else if F requency_3 then 22: if Up then 23: F requency F requency_4 24: else 25: F requency F requency_2 26: end if 27: else if F requency_4 then 28: if Down then 29: F requency F requency_3 30: end if 31: end if 32: Return Frequency 33: end procedure

46 36 CHAPTER 7. DESIGN AND IMPLEMENTATION Timer Start signal Scheduler wait for start signal from time If first time Initial schedulability Test If counter = hyperperiod RESET counter Set Frequency P1 Start P1 If P1 Period Actual If deadline overrun Frequency execution time UPP P2 Start P2 If P2 Period Actual execution time If deadline overrun Frequency UPP DVFS P3 Start P3 If P3 Period Actaul execution time If deadline overrun Frequency UPP If NO deadline overrun Frequency DOWN counter ++ Figure 7.3. Flowchart for the scheduling algorithm.

47 7.3. SUMMARY Summary This chapter describes the design and implementation of the DVFS scheduling algorithm. The algorithm is implemented on Enea s real-time operating system OSE5.4, and running on a Freescale i.mx31 ADS development board. The algorithm is designed for a real-time system (REQ1), and is of preemptive type (REQ2). The algorithm is written for a system with multi-programs (REQ3). The scheduler makes on-line computations and keeps track of deadline overruns (REQ4). The algorithm is also developed for dynamical frequency scaling during runtime (REQ5).

48

49 Chapter 8 Verification Three test cases have been tested on the system to evaluate the implemented algorithm. The purpose of the test is to compare the system behavior with and without the implemented algorithm. Two test cases are done with the system that simulates the frequency scaling, and one test case is done for real frequency scaling. The two first test cases, with simulating frequency scaling have been running with three different configurations. The third test case that uses real frequency scaling has been running with four different configurations. The algorithm is implemented on an OSE system, and running on a Freescale i.mx31 ADS development board. 8.1 Measuring Power Consumption Power consumption has been estimated for test case 3, see figure 8.5 for result. Since test cases 1 and 2 simulate frequency scaling, there is no need for estimating the power consumption, it will be the same for all configurations. By measuring the supply voltage V DD and the voltage drop V R over a shunt resistor R in series with the CPU on the imx31ads board (see figure 8.1), the power consumption can be estimated from equation 8.1. VDD R IDD VR VCPU Figure 8.1. Schematic of the power measurement P = V CP U I DD = (V DD V R ) I DD = (V DD V R ) VR R (8.1) 39

50 40 CHAPTER 8. VERIFICATION 8.2 Test Cases Simulated DVFS For these configurations the system is simulating frequency scaling. When the Scheduler computes a new frequency it sends a new execution time to the waiting process instead of sending a signal to DVFS_slave with the new frequency. For example, if the frequency is decreasing from 532 MHz to 266 MHz, the frequency is halved. This will result in a new execution time that is doubled, see equation 8.2. α = max_f req = 532MHz new_f req = 266MHz new_f req max_f req = = 1 2 new_exectime = exectime α = 2 exectime (8.2) Configuration A: The system is running on max frequency, which on the imx31 target is 532 MHz. Configuration B: The system is now using the implemented algorithm for initial frequency settings. The algorithm for the initial frequency, computes the lowest possible frequency that still guarantees all processes deadlines. The system is then running on this simulated frequency until it s finished. Configuration C: This configuration uses the whole systems functionality. The system starts at the computed initial frequency, then the second part of the DVFS algorithm tries to reduce the frequency for the lowest prioritized process, and increase the frequency if the system detects any deadline overrun. After a few hyperperiods the system will find the best suited frequencies for the process set. 8.3 Test Case 1 Description: This test runs the system with three different configurations, the configurations are described in section 8.2. System settings for test case 1 are described in table 8.1. Process ID P i WCET C i Period T i P 1 C 1 = 1 ms T 1 = 6 ms P 2 C 2 = 1 ms T 2 = 8 ms P 3 C 3 = 1 ms T 3 = 12 ms Table 8.1. Test case settings.

51 8.3. TEST CASE Results Test Case 1 Hyperperiod 24 ms Available frequencies Frequency 1: 532 MHz Frequency 2: 266 MHz Frequency 3: 133 MHz Frequency 4: 66 MHz Configuration A: The results for test 1 with configuration A, is shown in figure B.1 A. The figure shows one hyperperiod of the processes set, which is µs. All processes are running on max frequency 532 MHz, which result in a lot of processor idle time. This means that there is a lot of slack time available for frequency scaling. As the figure shows, the running processes have a great margin for their deadlines. Configuration B: Figure B.1 B, shows the result of the system running on configuration B. The scheduler has made a shedulability test and computed the initial frequency to 266 MHz. All processes are now running on 266 MHz. Compared to configuration A, there is now a great difference in processor idle time. Configuration C: In configuration C, the whole systems functionality is used. The result is illustrated in figure B.1 C. The processor idle time has decreased even more, compared to configuration A and B. The system is now running the higher prioritized processes P 1, and P 2, on frequency 266 MHz, and decreases the frequency to 133 MHz when process P 3 is running. Different from B.1 A and B, the time axis starts at µs for B.1 C. The reason for that is, the scheduler needed five hyperperiods to find the best suited frequency. Figure B.2 shows all six hyperperiods for test case 1 with configuration C. Figure 8.2 shows how much, the CPU idle time can be reduced by using DVFS scheduling.

52 42 CHAPTER 8. VERIFICATION Figure 8.2. Amount of CPU idle time for test case 1, with different configurations 8.4 Test Case 2 Description: This test runs the system with three different configurations, the configurations are described in section 8.2. system settings for test case 1 are described in table 8.1. Process ID P i WCET C i Period T i P 1 C 1 = 1 ms T 1 = 8 ms P 2 C 2 = 1 ms T 2 = 12 ms Table 8.2. Test case settings Results Tests Case 2 Hyperperiod 24 ms Available frequencies Frequency 1: 532 MHz Frequency 2: 266 MHz Frequency 3: 133 MHz Frequency 4: 66 MHz Configuration A: The results for test 2 with configuration A, is shown in figure B.3 A. The figure shows one hyperperiod of the processes set, which is µs. Both processes are running on max frequency 532 MHz, which result

53 8.5. TEST CASE REAL DVFS 43 in a lot of processor idle time. This means that there is a lot of slack time available for frequency scaling. As the figure shows, the running processes have a great margin for there deadlines. Configuration B: Figure B.3 B, shows the results of the system running on configuration B. The scheduler has made a shedulability test and computed the initial frequency to 133 MHz. Both processes are now running on 133 MHz. Compared to configuration 1, there is now a great difference in processor idle time. In this case there is almost no slack time in the system, except for the last µs of the hyperperiod. Configuration C: In configuration 3, the whole systems functionality is used. The results are illustrated in figure B.3 C. The slack time for the last µs of the hyperperiod, is almost gone. The system is now running the highest prioritized process P 1, on frequency 133 MHz. The frequency for the lower prioritized process P 2, alternates between 133 MHz and 66 MHz. It took the scheduler two hyperperiods to find the best suited frequency for this processes set, see figure B.4. Figure 8.3 shows how much, the CPU idle time can be reduced by using DVFS scheduling. Figure 8.3. Amount of CPU idle time for test case 2, with different configurations 8.5 Test Case Real DVFS Configuration D: The system is running on max frequency, which on the imx31 target is 532 MHz, and voltage 1.6 V. In this test case, all implemented pro-

54 44 CHAPTER 8. VERIFICATION cesses are running on max frequency and the OSE system idle state is also running on max frequency. Configuration E: The system is now using the implemented algorithm for initially frequency settings. The algorithm for the initial frequency computes the lowest possible frequency that still guarantee all processes deadlines. The system is then running on this frequency until it s finished. If the computed frequency is less than 399 MHz, the target board can decrease the voltage to 1.2 V. The OSE system idle state is also running on the computed initial frequency. Configuration F: This configuration uses the same settings used in configuration E, except that the OSE system idle state is now running on frequency 99 MHz. Configuration G: This configuration uses the whole systems functionality. The system starts at the computed initial frequency, then the second part of the DVFS algorithm tries to reduce the frequency for the lowest prioritized process, and increase the frequency if the system detects any deadline overrun. After a few hyperperiods the system will find the best suited frequencies for the process set. 8.6 Test Case 3 Description: This test runs the system with four different configurations, the configurations are described in section 8.5. system settings for test case 3 are described in table 8.1. Process ID P i WCET C i Period T i P 1 C 1 = 1 ms T 1 = 4 ms P 2 C 2 = 1 ms T 2 = 6 ms P 3 C 3 = 1 ms T 3 = 8 ms Table 8.3. Test case settings. Hyperperiod 24 ms Available frequencies Frequency 1: 532 MHz Frequency 2: 399 MHz Frequency 3: 199 MHz Frequency 4: 99 MHz

55 8.6. TEST CASE Results Test Case 3 Configuration 1: The results for test 3 with configuration 1, is shown in figure B.5 A. The figure shows one hyperperiod of the processes set, which is µs. All processes are running on max frequency 532 MHz, which result in a lot of processor idle time. The voltage over the CPU is 1.6 V, and even when the CPU is idle it runs on frequency 532 MHz with voltage 1.6 V. Power consumption for this test case is shown in figure 8.5. Configuration 2: Figure B.1 B, shows the results of the system running on configuration 2. The scheduler has made a shedulability test and computed the initial frequency to 399 MHz. All processes and CPU idle time are now running on 399 MHz with voltage 1.2 V. Configuration 3: With this configuration, the illustrated results are exactly the same as in configuration 2. The difference is that the CPU is running on a lower frequency for idle time, idle frequency is now 99 MHz with voltage 1.2 V. This result in a less power consumption, which can be seen in figure 8.5. Configuration 4: In configuration 4, the whole systems functionality is used. The result is illustrated in figure B.5 C. The CPU idle time has decreased even more, compared to configuration 1 and 2. The system is now running the higher prioritized processes P 1, and P 2, on frequency 399 MHz with voltage 1.2 V, and alternate the frequency between 99 MHz and 199 MHz for process P 3, with voltage 1.2 V. For power consumption see figure 8.5. Figure 8.4 shows how much, the CPU idle time can be reduced by using DVFS scheduling.

56 46 CHAPTER 8. VERIFICATION Figure 8.4. Amount of CPU idle time for test case 3, with different configurations Figure 8.5. Power consumption for test case 3, with different configurations.