Solder Dip Option: T = Standard S = Solder Dip (*) Package: (See page 3) Z = Z output

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1 DUAL INLINE PACKAGES 5.2 to 4.5Vdc &. to 5Vdc 0.0Hz to 200MHz Description Qech s Dual Inline (DIP) crystal oscillats consist of a source clock square wave generat, logic output buffers and/ logic divider stages, and a round A highprecision quartz crystal built in a metal throughhole package in DIP DIP configurations. Features Made in the USA ECCN: EAR99 DFARS Compliant: Electronic Component Exemption USML Registration # M7677 Wide frequency range from 0.0Hz to 200MHz Available as QPL MILPRF5530/, /, /, /5, /6, /7, /, /25, and /26 Wide operating temperature range Choice of output logic options Supply voltages from.vdc to 5Vdc Lower higher supply voltages available All metal hermetically sealed package ight custom symmetry available Fast rise and fall times Fast startup time Capacitive load drive capability (Z output) Multiple outputs available Fundamental and third overtone designs High operating temperature up to 225ºC Custom design available tails to meet customer s needs Qech does not use pure lead pure tin in its products RoHS compliant Applications Designed to meet today s requirements f all voltage applications Wide military clock applications Smart munitions Navigation Industrial controls Microcontroller driver Downhole applications up to 225ºC Ordering Infmation Solder Dip Option: = Standard S = Solder Dip (*) Package: (See page 3) Sample part number Q6HCD9M20.000MHz Q6HC D9M MHz Logic & Supply Voltage: C = CMOS 5.0V to 5.0V(**) AC = ACMOS 5.0V HC = HCMOS 5.0V = L 5.0V Frequency vs. emperature Code: L = LVHCMOS 3.3V = ± 00ppm at 0ºC to 70ºC N = LVHCMOS 2.5V 3(***) = ± 5ppm at 0ºC to 50ºC R = LVHCMOS.V 4 = ± 50ppm at 0ºC to 70ºC E = 0K ECL 5.2V 5 = ± 25ppm at 20ºC to 70ºC EH = 0KH ECL 5.2V 6 = ± 50ppm at 55ºC to 05ºC EF = 00K/300K ECL 4.5V 9 = ± 50ppm at 55ºC to 25ºC PE = PECL 5.0V 0 = ± 00ppm at 55ºC to 25ºC LP = PECL 3.3V = ± 50ppm at 40ºC to 5ºC Z = Z output 2 = ± 00ppm at 40ºC to 5ºC ristate Option: Blank = No ristate D = ristate (*) Hot Solder Dip Sn60/Pb40 per MILPRF 5530 is optional f an additional cost (**) Please specify supply voltage when dering CMOS (***) Requires an external capacit Frequency stability vs. temperature codes may not be available in all frequencies. Qech will assign a custom part number f custom specifications and all high temperature applications with typical frequency stability at ± 250ppm up to 200ºC. F NonStandard requirements, contact Qech Cpation at Sales@Qech.com Packaging Options Standard packaging in black foam Optional antistatic plastic tube Output Frequency Screening Option: Blank = No Screening M = Per MILPRF5530, Level B Other Options Available F An Additional Charge Lead fming available on all packages. Please contact f details. P. I. N. D. test (MILSD 3, Method 2020) Lead trimming All DIP packages are available in surface mount fm. Specifications subject to change without pri notice. Cpation 050 W. Jefferson Boulevard, Culver City el: Fax: Dual Inline Packages (Revision G, August 20 ) (ECO# 0297)

2 Electrical Characteristics Output freq. range (Fo) Supply voltage (Vdd) DUAL INLINE PACKAGES 5.2 to 4.5Vdc &. to 5Vdc 0.0Hz to 200MHz Parameters C AC HC L (*) ECL / PECL (**) DIP : Q6,, 4, 42, Hz 5MHz 0.0Hz 60MHz 0.0Hz 60MHz 0.0Hz 60MHz 0.0Hz 60MHz MHz 200MHz DIP : Q50, 5, Hz 5MHz 0.0Hz 5MHz 0.0Hz 5MHz 0Hz 5MHz 0.0Hz 00MHz MHz 0MHz 5V ~ 5Vdc ± 0% 5.0Vdc ± 0% 3.3Vdc ± 0% Maximum Applied Voltage (Vdd max.) 0.5 to Vdc 0.5 to 7.0Vdc 0.5 to 5.0Vdc Freq. stability ( F/ ) See Option codes Operating temp. (opr) See Option codes Stage temp. (sto) 62ºC to 25ºC Operating supply current (Idd) (No Load) F and Vdd dependent 3 ma max. at 5V up to 5MHz 25 ma max. at 5V up to 5MHz 20 ma max. 0.0Hz ~ < 6MHz 25 ma max. 6MHz ~ < 40MHz 35 ma max. 40MHz ~ < 60MHz 45 ma max. 60MHz ~ < 5MHz 55 ma max. 5MHz ~ < 0MHz 65 ma max. 0MHz ~ < 25MHz 75 ma max. 25MHz ~ 60MHz 3 ma max. 0.0Hz ~ < 500kHz 6 ma max. 500kHz ~ < 6MHz 0 ma max. 6MHz ~ < 32MHz 20 ma max. 32MHz ~ < 60MHz 30 ma max. 60MHz ~ < 00MHz 40 ma max. 00MHz ~ < 30MHz 50 ma max. 30MHz ~ 60MHz 5.2Vdc ± 5% (0K / 0KHECL) 5.0Vdc ± 5% (PECL) 3.3Vdc ± 5% (LVPECL) 0 to.0vdc (0K / 0KHECL) 0 to.0vdc (PECL) 0 to 5.0Vdc (LVPECL) 45 ma max. MHz ~ < 25MHz 75 ma max. 25MHz ~ 200MHz Symmetry (50% of ouput wavefm.4vdc f L) 45/55% max. Fo < 4MHz 40/60% max. Fo 4MHz 45/55% max. Fo < 2MHz 40/60% max. Fo 2MHz 45/55% max. Fo < 2MHz 40/60% max. Fo 2MHz Rise and Fall times (r/f) (with typical load) Output Load Startup time (stup) Output voltage (Voh/Vol) Output Current (Ioh/Iol) Enable/Disable ristate function Pin Jitter RMS σ (at 25ºC) Aging (at 70ºC) 30ns max. (Measured from 0% to 90%) ± ma typ. at 5V ± 6.mA typ. at 5V Call f details 5pF // 0kΩ (*) Available in 2.5Vdc (N).Vdc (R) (**) Please contact Qech f details on 00KECL logic (EF) Z Output logic can drive up to 200 pf load with typical 6ns rise & fall times (tr, tf) 5ns max. Fo < 5kHz 6ns max. Fo 5kHz ~ MHz 3ns max. Fo 40MHz ~ 60MHz (Measured from 0% to 90% CMOS from 0.V to 2.0V L) 0L Fo < 20MHz 6L Fo 20MHz 0ms max. 5pF // 0kΩ 3.5ns max. Fo < 25MHz 3ns max. Fo 25MHz ~ 200MHz (Measured from 20% to 0%) 50Ω to 2V (0K / 0KH) 50Ω to Vcc 2V (P & LP) 0.9 x Vdd min.; 0. x Vdd max. 2.4V min.; 0.4V max. 0.9 x Vdd min.; 0. x Vdd max..5v min;.54v max. (E) 4V min.; 3.37V max. (PE) 2.27V min.;.6v max. (LP) ± 24mA ± ma.6ma / L 40μA / L VIH 2.2V Oscillation; VIL 0.V High Impedance ps typ. < 40MHz 5ps typ. 40MHz ± 5ppm max. first year / ± 2ppm typ. per year thereafter ± 4mA. 50mA VIH 0.7 x Vdd Oscillation; VIL 0.3 x Vdd High Impedance 5ps typ. < 40MHz ps typ. 40MHz Call f details Integrated phase jitter 2kHz 20MHz ps typ. Cpation 050 W. Jefferson Boulevard, Culver City el: Fax: Dual Inline Packages (Revision G, August 20 ) (ECO# 0297) 2

3 Package Outline and Pin Connections Dimensions are in inches (mm) A Q6, Q4 B Q DIP C Q4 DUAL INLINE PACKAGES 5.2 to 4.5Vdc &. to 5Vdc 0.0Hz to 200MHz D Q42 E Q47 (5.0) (5.0) (5.0) (5.0) (5.0).290 (7.36) MIN. (5.0) (5.0) MIN. (5.0) MIN. (5.0) MIN. (.50).0 (.279).00 ±.00 (2.032±.254) (.50).0 (22.35).00 (20.32).00 (20.32).00 (20.32).00 (20.32) 7 7 (2.3) 7 (2.3) 7 (2.3) (2.3) 7 (2.3).00 (2.54).00 (2.54) ø.00 (ø 2.03).024 (.609) MAX F Q50 DIP G Q5 H Q55 Q # Conf Vcc Case Output (*) E/D N/C Ext. Cap Equivalent MILPRF5530 Configuration Q4 A & / = Q4 Q6 A & /6 = Q6 /7 = Q6 (**) / = Q6C /26A = Q6HC (5.0).250 MIN. (6.35) (.50).0 (.279).00 ±.00 (2.032±.254) (5.00).290 (7.366) (.50) (5.0).250 MIN. (6.35) Q0 A 2 N/A 0 & /0 = Q0 / = Q0C /5 = Q0C Q2 A & N/A 4 SQ. (2.3) SQ. 4 SQ. (2.3) SQ. 4 SQ. (2.3) SQ. Q B & N/A Q4 C 7 7 N/A /26B = Q4HC 5 ø.060 (ø.52) (.609) Package Infmation Package material (header and leads): Kovar Lead finish: Gold Plated 50µ ~ 0µ inches Nickel Underplate 00µ ~ 250µ inches Package to lid attachment: Resistance weld Cover: (DIP): Pure Nickel Grade A (DIP): Stainless Steel Weight: (DIP): 3.4g typ.,.2g max. (DIP): 2.0g typ.,.2g max. 5 Q42 D 7 7 N/A N/A Q47 E 7 7 N/A N/A Q4 A 7 N/A N/A /25 Q4E (***) Q50 F N/A N/A Q5 G N/A N/A Q55 H N/A N/A (*) ECL / PECL complimentary output available on pin 9 (F Q6 and Q only) with a Qech custom part number (**) Gated Output, gate control pin 9 (***) 5.2V Vcc (Pin 7) Cpation 050 W. Jefferson Boulevard, Culver City el: Fax: Dual Inline Packages (Revision G, August 20 ) (ECO# 0297) 3

4 Output Wavefm (ypical) H SYMMERY = x 00% DUAL INLINE PACKAGES 5.2 to 4.5Vdc &. to 5Vdc 0.0Hz to 200MHz Startup ime YPICAL SEUP FOR SARUP IME VOH r f Vdd 0.9xVdd Oscilloscope 5466B Agilent Variable Ramp DU 0.5xVdd VOL 0.xVdd Startup box s H est Circuit YPICAL ES CIRCUI FOR Q63 (6L) ypical test circuit f ECL logic. 0.0uF OUPU 5VDC POWER SUPPLY ma Vdc 0.µF 0.0µF OU OU Vcc 2Vdc 50Ω 4.5V 5.2V Q63 0 Cext 7 D 0k 2pF(*) DD4: N4 equivalent 430 D2 D3 D4 (*) CL includes scope probe capacitance ypical test circuit f CMOS logic ypical test circuit f L logic. Vdd RL Power supply ma Vdc Vdd 0.µF E/D 0.0µF Out 5pF (*) 0k Output Ground POWER SUPPLY ma Vdc 0.µF 0.0µF Vdd OU OU E/D C L Rs ristate Function (*) CL includes probe and jig capacitance he ristate function on pin has a builtin pullup resist typical 50kΩ, so it can be left floating tied to Vdd without deteriating the electrical perfmance. LOAD CL(*) RL RS 6 L 2pF 430Ω 0kΩ 0 L 20pF 270Ω 6kΩ (*) CL inclides the loading effect of the oscilloscope probe. Frequency vs. emperature Curve Frequency Stability (PPM) FREQUENCY VERSUS EMPERAURE Q6L9M64.5MHz emperature ( C) _5 2_5 3_5 Cpation 050 W. Jefferson Boulevard, Culver City el: Fax: Dual Inline Packages (Revision G, August 20 ) (ECO# 0297) 4

5 DUAL INLINE PACKAGES 5.2 to 4.5Vdc &. to 5Vdc 0.0Hz to 200MHz hermal Characteristics he heat transfer model in a hybrid package is described in figure (Based on single ASIC design). D/A epoxy Die Heat spreading occurs when heat flows into a material layer of increased crosssectional area. It is adequate to assume that spreading occurs at a 45 angle. D/A epoxy 45º 45º Heat Hybrid Case Substrate he total thermal resistance is calculated by summing the thermal resistances of each material in the thermal path between the device and hybrid case. R = R R2 R3 R4 R5 he total thermal resistance R (see figure 2) between the heat source (die) to the hybrid case is the heta Junction to Case (heta JC) in C/W. heta junction to case (heta JC) f this product is 24 C/W. heta case to ambient (heta CA) f this part is 05 C/W. heta Junction to ambient (heta JA) is 30 C/W. Maximum power dissipation PD f this package at 25 C is: PD(max) = (J (max) A)/heta JA With J = 75 C (Maximum junction temperature of die) PD(max) = (75 25)/30 =.5W R Die R2 R3 R4 R5 D/A epoxy Substrate D/A epoxy Hybrid Case (Figure ) A CA C JC J Die JA JC CA (Figure 2) Environmental Specifications Qech Standard Screening/QCI (MILPRF5530) is available f all of our DIP packages. Qech can also customize screening and test procedures to meet your specific requirements. he DIP packages are designed and processed to exceed the following test conditions: Environmental est est Conditions emperature cycling MILSD3, Method 00, Cond. B Constant acceleration MILSD3, Method 200, Cond. A, Y Seal: Fine and Gross Leak MILSD3, Method 0, Cond. A and C Burnin 60 hours, 25 C with load Aging 30 days, 70 C, ± 0.7ppm max Vibration sinusoidal MILSD202, Method 204, Cond. D Shock, non operating MILSD202, Method 23, Cond. I hermal shock, non operating MILSD202, Method 07, Cond. B Ambient pressure, non operating MILSD202, 05, Cond. C, 5 minutes dwell time minimum Resistance to solder heat MILSD202, Method 20, Cond. C Moisture resistance MILSD202, Method 06 erminal strength MILSD202, Method 2, Cond. C Resistance to solvents MILSD202, Method 25 Solderability MILSD202, Method 20 ESD Classification MILSD3, Method 305, Class HBM 0 to,999v Moisture Sensitivity Level JSD020, MSL= Please contact Qech f higher shock requirements Cpation 050 W. Jefferson Boulevard, Culver City el: Fax: Dual Inline Packages (Revision G, August 20 ) (ECO# 0297) 5

6 DUAL INLINE PACKAGES 5.2 to 4.5Vdc &. to 5Vdc 0.0Hz to 200MHz Period Jitter As data rates increase, effects of jitter become critical with its budgets tighter. Jitter is the deviation of a timing event of a signal from its ideal position. Jitter is complex and is composed of both random and deterministic jitter components. Random jitter (RJ) is theetically unbounded and Gaussian in distribution. Deterministic jitter (DJ) is bounded and does not follow any predictable distribution. DJ is also referred to as systematic jitter. A technique to measure period jitter (RMS) one standard deviation (σ) and peaktopeak jitter in time domain is to use a high sampling rate (>G samples/s) digitizing oscilloscope. Figure shows an example of peaktopeak jitter and RMS jitter (σ) of a Q6AC 24MHz, at 5.0Vdc. Phase Noise and Phase Jitter Integration RMS jitter (σ): 5.6ps Peaktopeak jitter: 52.4ps Phase noise is measured in the frequency domain, and is expressed as a ratio of signal power to noise power measured in a Hz bandwidth at an offset frequency from the carrier, e.g. 0Hz, 00Hz, khz, 0kHz, 00kHz, etc. Phase noise measurement is made with an Agilent E5052A Signal Source Analyzer (SSA) with builtin outstanding lownoise DC power supply source. he DC source is floated from the ground and isolated from external noise to ensure accuracy and repeatability. In der to determine the total noise power over a certain frequency range (bandwidth), the time domain must be analyzed in the frequency domain, and then reconstructed in the time domain into an rms value with the unwanted frequencies excluded. his may be done by converting L(f) back to Sφ(f) over the bandwidth of interest, integrating and perfming some calculations. L(f) Symbol Definition Integrated single side band phase noise (dbc) Sφ (f)=(0/π)x 2 L(f)df RMS jitter = Sφ (f)/(fosc.360 ) Spectral density of phase modulation, also known as RMS phase err (in degrees) Jitter(in seconds) due to phase noise. Note Sφ (f) in degrees. he value of RMS jitter over the bandwidth of interest, e.g. 0kHz to 20MHz, 0Hz to 20MHz, represents standard deviation of phase jitter contributed by the noise in that defined bandwidth. Figure below shows a typical Phase Noise/Phase jitter of a Q6AC, 5.0Vdc, 24MHz and a Q50, 5.0Vdc, 60 MHz clock at offset frequencies 0Hz to 5MHz, and phase jitter integrated over the bandwidth of 2kHz to MHz. Q6AC, 5.0Vdc, 24MHz Q50, 5.0Vdc, 60 MHz Cpation 050 W. Jefferson Boulevard, Culver City el: Fax: Dual Inline Packages (Revision G, August 20 ) (ECO# 0297) 6