Small cost. Low power. Big Performance

Transcription

1 Small cost. Low power. Big Performance Introducing the MC56F86/2 DSC Family

2 Agenda BLDC Motor Brushed DC motor Brushless DC motor (BLDC) BLDC motor control Sensorless BLDC control Reference Design Freescale Solution Aditional Resourses

3 Brushed DC motor Freescale Semiconductor Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 28.

4 Brushed DC Rotor Motor Anatomy Commutator Stator The first electric motor was the Brushed DC Motor Basic idea is to repel rotor from stator

5 Motor Fundamentals N S

6 Motor Fundamentals N N S + _ + _ S V

7 Motor Fundamentals N N S + _ + _ S V

8 Motor Fundamentals S N N S _ + _ + V

9 Motor Fundamentals N S N S + _ + _ V

10 DC Motor Commutation The stator of a Permanent Magnet DC Motor is composed of two or more permanent magnet pole pieces. The rotor is composed of windings which are connected to a mechanical commutator. In this case the rotor has three pole pairs.

11 Brushless DC motor Freescale Semiconductor Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 28.

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15 BLDC Motor Control Freescale Semiconductor Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 28.

16 Six Step BLDC Motor Control Voltage applied on two phases only It creates 6 flux vectors Phases are power based on rotor position The process is called commutation Phases voltage Power Stage

17 Control of a Brushless D.C. Motor Controller B C A t s r 2 zones in 36 degrees of mechanical rotation 5 6 Source: Eastern Air Devices, Inc. Brushless DC Motor Brochure 2 hall spacing is preferred over 6 spacing since unpowered or unconnected sensors produce or codes, which can be used for fault detection.

18 Sensor Example: Hall Effect Sensor Hall effect sensor is a transducer that varies its output voltage in response to changes in magnetic field Hall sensors are used for proximity switching, positioning, speed detection and current sensing applications In this case, hall sensors are used in On/Off mode Hall Sensor Everytime a magnetic field is sensed, a change in voltage can be detected Permanent Magnet

19 BLDC Commutation Rotor Electrical Position (Degrees) Hall r Hall s Hall t PWM PWM 3 PWM 5 PWM 2 PWM 4 PWM 6 State shown In previous slide

20 Control of 3-Phase Inverter Determined on the Hall Sensor Position B A N S C A B C BLDC Motor C A B H H2 H3 Phase A Phase B Phase C +V DCB -V DCB NC +V DCB NC -V DCB NC +V DCB -V DCB -V DCB +V DCB NC -V DCB NC +V DCB NC -V DCB +V DCB

21 Control of 3-Phase Inverter Determined on the Hall Sensor Position B C N S A A B C A B C BLDC Motor H H2 H3 Phase A +V DCB +V DCB NC -V DCB -V DCB NC Phase B -V DCB NC +V DCB +V DCB NC -V DCB Phase C NC -V DCB -V DCB NC +V DCB +V DCB

22 Control of 3-Phase Inverter Determined on the Hall Sensor Position B C A N S A B C A B C BLDC Motor H H2 H3 Phase A +V DCB +V DCB NC -V DCB -V DCB NC Phase B -V DCB NC +V DCB +V DCB NC -V DCB Phase C NC -V DCB -V DCB NC +V DCB +V DCB

23 Control of 3-Phase Inverter Determined on the Hall Sensor Position B C A N S A B C A B C BLDC Motor H H2 H3 Phase A +V DCB +V DCB NC -V DCB -V DCB NC Phase B -V DCB NC +V DCB +V DCB NC -V DCB Phase C NC -V DCB -V DCB NC +V DCB +V DCB

24 Control of 3-Phase Inverter Determined on the Hall Sensor Position B C N S A A B C A B C BLDC Motor H H2 H3 Phase A +V DCB +V DCB NC -V DCB -V DCB NC Phase B -V DCB NC +V DCB +V DCB NC -V DCB Phase C NC -V DCB -V DCB NC +V DCB +V DCB

25 Control of 3-Phase Inverter Determined on the Hall Sensor Position B C A N S A B C A B C BLDC Motor H H2 H3 Phase A +V DCB +V DCB NC -V DCB -V DCB NC Phase B -V DCB NC +V DCB +V DCB NC -V DCB Phase C NC -V DCB -V DCB NC +V DCB +V DCB

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27 Sensorless BLDC Freescale Semiconductor Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 28.

28 Sensorless BLDC Control Conditioning Controller X Source: Eastern Air Devices, Inc. Brushless DC Motor Brochure

29 Back EMF in a Single Loop of Wire

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31 Sensorless Commutation Rotor Electrical Position (Degrees) Phase R Phase S Phase T Zero crossings PWM PWM 3 PWM 5 PWM 2 PWM 4 PWM 6

32 Back-EMF Zero Crossing - detail

33 Sensorless BLDC Motor Control using MC56F86 Reference Design: DRM8 Freescale Semiconductor Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 28.

34 Sensorless BLDC Motor Control using MC56F86 RUN/STOP Power supply UP/DOWN SPEED USB 3-phase BLDC 24V DC connector

35 Sensorless BLDC Motor Control using MC56F86 Application Features Sensorless Back-EMF zero crossing algorithm implemented Controlled by MC56F86 Back-EMF sensing by ADC Full 4-quadrant operation Speed Closed loop with PI Controller and automatic current limitation Speed range: 5 4 rpm (motor dependent) Manual Interface FreeMaster Interface

36 Sensorless BLDC Motor Control using MC56F86 Application Diagram

37 Sensorless BLDC Motor Control using MC56F86 MC56F86 Peripheral Utilization PWM module modulation for BLDC motor (complementary unipolar) Dual Timer Channel : ADC run, stop, zero crossing evaluation Channel : commutation PIT Timer PI controllers, check manual interface, Ramp generation A/D Converter DC Bus voltage, DC Bus current, Phase voltages Software Structure 2x periodical interrupts (5ms, 6us) x event interrupt (x Commutation) Background loop Written in C language Fast interrupt routines written in assembler

38 Sensorless BLDC Motor Control using MC56F86 Motor Start Up Alignment The rotor is aligned to known position. Start up Six forced commutation with predefined timing. Then transition to sensorless mode. Run Motor is running sensorless in closed loop Rotor alignment

39 Sensorless BLDC Motor Control using MC56F86 Software Structure Main (background) loop Timer Ch Compare ISR Timer Ch Compare ISR Initialize - Peripheral initialization - Application initialization - Select and start ADC - Store ADC results - Back-EMF averaging - Zerro cross evaluation - Commutation time calculation - Commutation PIT Period ISR Application State Machine - Init state - Stop state - Alignment state - Start state - Run state - Error state - Average speed and current - Speed calculation - PI controllers - Ramp generation - Setup number of samples - Check manual interface

40 Sensorless BLDC Motor Control using MC56F86 Application State Machine CPU RESET INIT STOP run == run == run == ERROR Alignment driver fault Code Length FLASH memory: 68 bytes RAM memory: 254 bytes (include stack 28 bytes) run == Start RUN timer overflow driver fault alignmentflag == timer overflow driver fault

41 Freescale DSC Family Freescale Semiconductor Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 28.

42 56F8/56F83/56F84 2K - 6KB Program Flash 4kB Program/ Data RAM 568E Core 32MHz JTAG/EOnCE 56F8/56F83/56F84 System Integration Module (SIM) Interrupt Controller PLL Relaxation OSC Voltage Regulator COP Power-On-Reset Power Supervisor Package: 32LQFP Up to 26 GPIOs x SCI x SPI x IIC 3-4ch 2bit ADC 3-4ch 2bit ADC Synch 4Ch 6bit Timer 6-ch PWM Output 32 MIPS Performance 2K -6 K Bytes Program FLASH 4 K Bytes Program/Data RAM Tunable Internal Relaxation Oscillator Software Programmable Phase Locked Loop Up to 96 MHz Peripherals Timers and PWMs Up to 6-Output PWM Module with up to 4 Programmable Fault Inputs Selectable PWM frequency for each complementary PWM signal pair Two 2-bit ADCs with up to 8 Inputs,.25us conversion rate Synchronization between PWM and ADC Four 6-bit General Purpose Programmable Timers Computer Operating Properly Timer Serial Ports: SCI, SPI, I2C Up to 26 GPIOs Versatile pin usage Low Power Consumption 59mA Max and.26ma Min JTAG/EOnCE Debug Port Industrial & Automotive temp

43 56F823/56F825/56F836/56F837 Features 56F823/56F825/56F836/56F837 32KB - 64KB Program Flash 4kB-8KB Program/ Data RAM 568E Core 32MHz JTAG/EOnCE System Integration Module (SIM) Interrupt Controller PLL Relaxation OSC Crystal OSC Voltage Regulator COP Power-On-Reset Power Supervisor 2 x 2 bit DAC Up to 53 GPIOs 2 x QSCI 2 x QSPI xiic x MSCAN 3xPIT 8ch 2bit ADC 8ch 2bit ADC Synch 8Ch 6bit Timer 6-ch PWM Output 2 x Comparators Package 32 LQFP, 44LQFP, 48LQFP, 64LQFP 32 MHz/32 MIPS 568E Core V Operation 32K-64K Bytes Program FLASH 4K-8K Bytes Program/Data RAM Flash security Tunable Internal Relaxation Oscillator Software Programmable Phase Locked Loop Up to 96 MHz Peripherals Timers and PWMs 6 Output PWM Module with 4 Programmable Fault Inputs Selectable PWM frequency for each complementary PWM signal pair Two 2-bit ADCs with up to 6 Inputs,.25us conversion rate Up to Two 2-bit Digital to Analog Converters Two Analog Comparators Synchronization between PWM and ADC 4 or 8 6-bit General Purpose Programmable Timers or 3 Programmable Interval Timers (PIT) Computer Operating Properly Timer 2-Queued Serial Communications Interface 2-Queued Serial Peripheral Interface Optional MSCAN I 2 C Communications Interface Up to 53 GPIOs Versatile pin usage JTAG/EOnCE Debug Port

44 56F8 Series Feature Summary 56F8 56F83 56F84 56F823 56F825 56F836 56F837 Performance 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs Temperature Range (V) -4C to 5C -4C to 5C -4C to 5C -4C to 5C -4C to 5C -4C to 5C -4C to 5C Voltage Range 3.V - 3.6V 3.V - 3.6V 3.V - 3.6V 3.V - 3.6V 3.V - 3.6V 3.V - 3.6V 3.V - 3.6V Voltage Regulator On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip Program/Data Flash 2KB 6KB 6KB 32KB 32KB 64KB 64KB Program/Data RAM 2KB 4KB 4KB 4KB 4KB 8KB 8KB Program Security Yes Yes Yes Yes Yes Yes Yes On Chip Relaxation Osc. Yes Yes Yes Yes Yes Yes Yes PLL Yes Yes Yes Yes Yes Yes Yes COP Yes Yes Yes Yes Yes Yes Yes PWM x 6ch x 6ch x 5ch x 6ch x 6ch x 6ch x 6ch PWM Fault Inputs bit ADCs 2 x 3ch 2 x 3ch 2 x 4ch 2 x 3ch 2 x 4ch 2 x 5ch 2 x 8ch 2-bit DACs No No No (Pinned out) Analog Comparator No No No bit Timers Prog. Interval Timers No No No GPIO (max) IIC SCI (UART) / LIN Slave - SCI - SCI - SCI - QSCI - QSCI - QSCI 2 - QSCI SPI (Synchronous) - SPI - SPI - SPI - QSPI - QSPI - QSPI 2 - QSPI CAN MSCAN MSCAN JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE Package (V) - Industrial 32LQFP (.8p) 32LQFP (.8p) 32LQFP (.8p) 32LQFP (.8p) 44LQFP (.8p) 48LQFP (.5p) 64LQFP (.5p) 44

45 Core 32 MHz/32MIPS 56F8E core.8v to 3.6V operating range Memory Up to 6KB flash with Flash security, 2KB SRAM Features Low power stop modes Up to 96 MHz peripherals timers, PWM & SCI 6 output PWM module with up to 4 programmable fault inputs Two wideband clocked programmable gain amplifiers /2-bit conversion done in SysClk (8-bit conversion done in SysClk ) Up to three analog comparators Custom timer for precise control of ADC/PGA sample times relative to PWM reload cycles 2 multiple function programmable timers One Periodic Interval Timer (PIT) Computer Operating Properly timer Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) I 2 C communications interface Up to 4 GPIOs Versatile pin usage JTAG/EOnCE debug port About the MC56F86/2 Family 2KB SRAM 6K Bytes Flash 2KB SRAM 2K Bytes Flash Memory Options 3 Analog Comparators 2 2X-6X Wideband PGAs Flash/RAM Voltage Regulators Interrupt Controller System Integration Module (SIM) 568E Core/32MIPS Power SuperVisor COP High Speed SCI SPI IIC 2 6-bit Timers 6-bit Periodic Interval Timer 2 2-bit ADCs Programmable Delay Block (PDB) 6 Output PWM System Clock Control (PLL, SIM, Osc) JTAG/EOnCE Part Number Package Sugg Resale K - 25K MC56F86VLF 48LQFP $.7 MC56F86VLC 32LQFP $.6 MC56F86VWL 28SOIC $.55 MC56F82VWL 28SOIC $.5 To order, visit: MC56F86 Buy Direct 45

46 Internal Peripherals

47 Introducing the MC56F86/2 DSC Family The entry-level MC56F86/2 Digital Signal Controller provides the most cost-optimized solution for mathematically-intensive, power-sensitive real-time control applications. High-performance, DSP core and integrated control peripherals The family explanation includes that an makes ideal this mix messaging of high-performance point true. analog What makes (PGA, ADC) this important? and digital How (PWM) are we accomplishing peripherals which this have point? been What intelligently does this designed do for our for customers? real-time industrial applications such as energy-efficient motor control, digital power supplies, and solar inverters. Market leading ultra-low-power DSC The 56F86/2 family has been architected from the transistor level up with ultra-low-power in mind -- standby currents are less than ua, and run currents less than 5mA are typical. A dual 2-bit SAR ADC is included that is optimized for very fast, low power data conversions. An ultralow-power crystal oscillator module is also integrated lowering overall system power consumption. Big performance, low cost Designed to achieve exceptional performance and price, our on-chip features reduce the need for external components and lower your overall BOM cost. 47

48 MC56F86/2 Target Markets and Applications Energy Motor Control 3 phase BLDC motor control Entry-level field -oriented control PMSM control Large & small home appliances Advanced Power Conversion Board mounted & industrial power supplies Switched-mode power supply & power management Arc fault protection Advance lighting control Power-Sensitive Applications Medical portable diagnostic and Therapeutic devices Handheld power tools Instrumentation 9

49 MCF5686/2: Break New Ground in Your Designs Performance Motor Control 96 MHz for key peripherals (timers, SCI and PWM) twice the module maximum operating frequency compared to competitive DSCs. Dual Harvard Architecture + MAC and high operating frequency enable outstanding performance in single-cycle Peripheral set 2 x high speed 2bit x 24 channel ADC module with integrated temperature sensor more resolution and channels than the competition. Programmable gain amplifier increases the ADC input dynamic range. Shielded inputs in ADC reduce noise in conversion. Three analog comparators more than any competitive offering. Power consumption Advanced Power Conversion Power-Sensitive Applications Lowest power stop modes of any DSC in the market.

50 Exceptional Out-of-the-Box Development Experience Rich enablement and development tools to speed your time-to market MC56F86DEMO boards kits MC56F86DEMO $49 MSRP MC56F86DEMO-T (USB Tap included) $99 MSRP Includes seven progressive labs that progress from blinking the LEDs to spinning a motor (with inexpensive accessory available now) in just one day Developers learn how to use the USB serial port, explore the capabilities of the programmable gain amplifier, design an FIR, perform an FFT on audio data, and perform real-time control and graphing. Easy configuration of all device pins with an expert system to generate system configuration and control code - all from an easy-to-use GUI interface built into the IDE The kits include CodeWarrior Development Studio for 568/E Digital Signal Controllers - Free Special Edition with up to 32 KB code size [CWX-568-SE] Highly optimized C compiler to ensure smallest code size and fastest execution time Industrial-strength Project Manager eliminates complicated build scripts Integrated source code navigation provides quick and easy access to functions and files Graphical source-level debugging solves complex problems quickly and easily Advanced instruction set simulation enables hardware/software co-design To order the MC56F86DEMO board, visit MC56F86DEMO To order CodeWarrior Suites and CW Special Edition, visit CodeWarrior for 56F8/E DSC 5

51 Get to Market Faster with Processor Expert Speed time to market Accelerate design cycles Do more with one engineer Improve software quality by using optimized libraries and expert system code generation Freescale s solution Processor Expert Shrink board bring-up from weeks to a day using this rapid application development tool to create initialization code and drivers Use Processor Expert s graphical user interface to select functionality for each application Processor Expert s built-in knowledge base Only presents silicon resources that can perform the selected functionality. Avoids resource conflicts and incorrect settings, to avoid issues in the design phase and get to market first with best quality Processor Expert automatically generates tested, optimized C code tuned to application needs and the selected Freescale DSC with its plethora of signal processing library code Extensive application-specific libraries Embedded Beans unlock libraries targeted for motor control, audio, speech, control systems, including Transcendental functions, speech codec, V22bis modem data pump PID controllers, noise filters, tone detectors, DF generators and detectors Clark and Park transform and inverse transforms Algorithmic support for space vector modulation, and more.. Embedded Bean Store is now available at 5

52 Aditional Resources Freescale Semiconductor Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 28.

53 Enables you to: Freescale MicroSelector Finding the right Freescale MCU for your design Find the best fit - filter by features in our wide variety of controller solutions: 8-bit products (RS8, HC8 and HCS8 families) 6-bit products (DSC and S2X families) 32-bit products (ColdFire, i.mx and Power) Find package and temperature range offerings. Documentation - read collateral for each family. Visit the Product Page Using MicroSelector: ) Download Freescale MicroSelector Installer. 2) Unzip and execute the file. 3) Open Freescale MicroSelector. 4) Choose Product Type: Microcontroller / Digital Signal Controller / Microprocessor 5) Navigate to find information 53

54 More Resources MCF56F86 Website _summary.jsp?code=mc56f8x Access Now for: Quick Product information Data Sheet Reference Manual Order Samples Application Notes Reference Designs Fact Sheets Development Board Downloads Video Tutorials

55 DC motor DC Motor with Speed and Current Closed Loops, driven by etpu on MPC5554 Power Drill Control Software for MC68HC98QY4. Universal motor Open Loop PWM Control of Universal Motor for Vacuum Cleaner using MC68HC98QT4 Stepper Motor LIN-bus HID Lamp Levelling Stepper Motor Control Using MC98E625 BLDC 3 phase Brushless DC Motor Sensorless Control using MC56F83 3 phase Brushless DC Motor Sensorless Control, Demonstrating very high speed motor operation using MC56F83 3-Phase BLDC Motor Sensorless Control using MPC565 3-phase BLDC Motor Control using MC9S8GT6 and MC Phase BLDC Motor Sensorless Control using MC9S8AW6 Washer Three-Phase AC Induction Motor Drive Based on MC56F83 3-phase BLDC Drive using DC/DC Inverter on MC56F83 3 phase Brushless DC Motor Sensorless Control, Demonstrating very high speed motor operation using MC56F83 3 phase Brushless DC Motor Sensorless Control using MC56F83 Low Power BLDC Drive for Fan using the MC68HC98QY4 MCU BLDC Motor Control with Quadrature Encoder using DSP56F the Processor Expert solution ACIM Washing Machine Three-Phase AC Induction Motor Drive Based on MC56F83 PWM Control of the Single-Phase A.C. Induction Motor Using the MC68HC98QT4 MCU (Nitron) 3-Phase ACIM V/Hz Control using Hybrid Controller 56F the Processor Expert solution 3-Phase AC Induction Motor Vector Control Using DSP56F8x AC Induction Motor Vector Control Using MPC555 3-Phase ACIM Control with Dead Time Distortion Correction using MC68HC98MR32 3-Phase AC Induction Motor Volt Per Hertz Control System Based on DSP56F8x Analogue support High Voltage BLDC Drive for Domestic Appliances using MC68HC98MR8 MCU Small Electric Vehicle with Analog DC Motor Driver (DMD) 3-phase Power Stage with DC/DC Inverter Lite using MC phase Micro Power Stage 3-Phase 2-Volt BLDC Power Stage with Driver Small Electric Vehicle with Analog DC Motor Driver (DMD) Freescale Motor Control Reference Designs PMSM Permanent Magnet Synchronous Motor Vector Control, driven by etpu on MCF523x 3-Phase PMSM Vector Control using MC56F ph. PMSM Torque Vector Control with Encoder and Resolver based on MC56F8x and MC56F83xx (EPS Demo) Synchronous PM Motor Control with Quadrature Encoder using DSP56F85 3-ph PM Synchronous Motor Torque Vector Control on DSP56F8x 3-Phase PM Synchronous Motor Vector Control using DSP56F8x 3-Phase PMSM Vector Control using MC56F8346 SR 3-Phase SR Motor Control with Hall Sensors Using DSP56F8x 3-Phase SR Sensorless Motor Control using DSP56F8x Advanced 3-Phase Switched Reluctance Motor Control with Encoder Using DSP56F8x TPU and etpu controlling motors Four BLDC Motors Driven by One etpu BLDC Motor with Speed Closed Loop and DC-Bus Break Controller, driven by etpu on MPC5554 DC Motor with Speed and Current Closed Loops, driven by etpu on MPC5554 AC Induction Motor V/Hz Control, driven by etpu on MCF523x BLDC Motor with Quadrature Encoder and Speed Closed Loop, driven by etpu on MPC Phase BLDC Motor with Hall Sensors and Speed Closed Loop, driven by etpu on MPC554 3 BLDC Motor Control with Hall Sensors driven by etpu on MCF5235 Permanent Magnet Synchronous Motor Vector Control, driven by etpu on MCF523x TPU Library Routines for MPC555 AC Induction Motor V/Hz Control, driven by etpu on MCF523x BLDC Motor with Quadrature Encoder and Speed Closed Loop, driven by etpu on MPC5554 Project Page: 3 BLDC Motor Control with Hall Sensors driven by etpu on MCF Phase BLDC Motor with Hall Sensors and Speed Closed Loop, driven by etpu on MPC554

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66 568/E Family Combining Signal Processing and Controller Functionality Traditional Microcontroller Design for Controller Code Traditional Software Stack Easy to Program Exceptional Code Density Traditional DSP Engine Designed for DSP Processing Fast Matrix Operations Single-cycle multiply-accumulate Modulo Addressing Barrel Shifter Multiple bus Harvard Architecture Instructions Optimized for Controller Code, DSP, Matrix Operations Compact Assembly and C Compiled Code Size Easy to Program Additional MIPS Headroom and extended addressing space

67 MCF56F86 has 2 ADCs ADC Features of the ADC module include: Input voltage values may range from VSSA to VDDA. Up to 28 analog inputs. Output formatted in 2-, - or 8-bit rightjustified format. Single or continuous conversion (automatic return to idle after single conversion). Configurable sample time and conversion speed/power. Conversion complete flag and interrupt. Input clock selectable from up to four sources. Operation in wait or stop modes for lower noise operation. Asynchronous clock source for lower noise operation. Support of simultaneous and software triggering conversions. Temperature sensors that are routed to ANA26 and ANB26. Can be configured to take two samples (with no software reconfiguration required) based on hardware triggers during ping-pong mode.

68 PGA Features: Sampled PGA architecture Common mode noise and offset are automatically cancelled out (2 4 consecutive samples required for noise/offset cancellation) Sample is able to be synchronized with PWM operation using the PWM sync output and programmable delay block Sampling time can be precisely controlled (to less than. µs) Several programmable gains (, 2, 4, 8, 6, and 32 ) Selectable tradeoff for slower/low power versus faster/more power Rail-to-rail input voltage range Single-ended output routed directly to on-chip ADCs ANA5 and ANB5 Software and hardware triggers are available Includes additional calibration features: Offset calibration eliminates any errors in the internal reference used to generate the VDDA/2 output center point Gain calibration can be used to verify the gain of the overall datapath Both features require software correction of the ADC result

69 Comparator output may be: Sampled. Windowed (ideal for certain PWM zero-crossing-detection applications). Digitally Filtered. Filter can be bypassed. May be clocked via external SAMPLE signal or scaled peripheral clock. HSCMP The HSCMP has the following features: Less than 4 mv of input offset. Less than 5 mv of hysteresis. Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. 4-to- muxes in inputs. Two software selectable performance levels: Shorter propagation delay at the expense of higher power. Low power, with longer propagation delay.

70 568E Core Architecture PC LA LA LA2 HWS FIRA FISR SR OMR LC LC LC2 PROGRAM CONTROLLER INSTRUCTION DECODER INTERRUPT UNIT LOOPING UNIT AGU A L U A L U 2 M N 3 R R R 2 R 3 R 4 R 5 N S P XAB XAB2 PAB PDB CDBW CDBR XDB2 Program Memory Data Memory IP-Bus Interface Instruction Fetch: PAB PDB - 2 bits - 6 bits st Data Access: XAB - 24 bits CDBR - 32 bits CDBW - 32 bits 2nd Data Access: XAB2 XDB2-24 bits - 6 bits Operations Performed: BIT MANIPULATION UNIT A B C D Y Y X DATA ALU External Bus Interface st - PAB / PDB 2nd - XAB / CDBR- CDBW EOnCE/JTAG TAP MAC and ALU Multi-bit Shifter 3rd - XAB2 / XDB2

71 56F8 Feature Highlights Pulse Width Modulator JTAG/EOnCE Voltage Regulators Interrupt Controller Power Supervisor COP MSCAN 3-PIT Flash RAM 568E Core 32 MIPS 32 MHz Pulse Width Modulator System Integration Module (SIM) 6 Output PWM 8 6bit Timers Up to 6 Input 2-bit ADCs 2-QSCI 2-QSPI I 2 C 2-2bit DACs 2-Analog Comparators System Clock Control (PLL, SIM, Osc) Up to 96Mhz PWM operation clock Three complementary signal pairs or six independent signals or combinations Complementary channel operation Separate Deadtime insertion for rising and falling edge Separate top and bottom polarity control Edge-aligned or center-aligned signals 5-bits of resolution Half-cycle reload capability Asymmetric mode of operation (for phase shifting) Programmable integral reload rates (half to 6) Individually software-controlled PWM outputs ADC synchronization Up to 4 Programmable fault inputs PWM compare output polarity control 8 or 4 ma current source/sink Output Polarity Control Write protected registers Double-buffered PWM register Wait/Debug mode operation Selectable PWM supply source for each complementary PWM signal pair (F8family only) PWM Generator External GPIO Internal timer channel ADC conversion result, taking into account values setting ADC high and low limit register

72 PWM Fault Decode and Automatic Clearing DISMAP3 DISMAP2 DISMAP DISMAP Fault Digital Filter AND Fault Fault 2 Fault 3 Digital Filter Digital Filter Digital Filter AND AND AND OR Disable PWM PWM Value PWM Modulo PWM Output Fault Input PWM Enable PWM Disable PWM Enable PWM Disable PWM Enable *When Fault logic returns to logic, the PWM restart at beginning of the next half cycle.

73 FlexTimer functionality TPM Ch TPM Ch F ch Capt/comp Combine Start value Finish value TPM Ch2 TPM Ch3 F ch Capt/comp Combine 6 bit counter Channel,2,4,6 compare capture Triggers ADC Filter (ch only) I/O pin Ch # TPM Ch4 TPM Ch5 F ch Capt/comp Combine Channel,3,5,7 compare Combine Dead time insertion, FAULT control, output mask I/O pin Ch# TPM Ch6 TPM Ch7 F ch Capt/comp Combine capture Filter (ch only) Filter Fault input

74 Center Aligned Example Modulus ($) PWM off PWM3 off ($) PWM3 on PWM on Preload ($FF) PWM PWM3 When the Init value is the signed negative of the Modulus value, the PWM module works in signed mode. Center-aligned operation is achieved when the turn-on and turn-off values are the same number, but just different signs. Ackowledgement: Dave Wilson for waveform diagram

75 Edge Aligned Signed Mode Example Modulus ($) PWM off ($) PWM off Preload ($FF) PWM on = PWM on = $FF PWM PWM All six PWM signals (PWM PWM5) have this capability All PWM-on values are set to the init value, and never changed again. Positive PWM-off values generate pulse widths above 5% duty cycle. Negative PWM-off values generate pulse widths below 5% duty cycle. This works well for bipolar waveform generation. Ackowledgement: Dave Wilson for waveform diagram

76 Phase Shifted PWMs Modulus ($) PWM3 off PWM off ($) PWM3 on PWM on Preload ($FF) PWM PWM3 In this example, both PWMs have the same duty-cycle. However, the edges are shifted relative to each other by simply biasing the compare values of one waveform relative to the other. This is useful for reconstructing phase currents from a DC bus shunt when the amplitudes of the modulated signals are near zero. Ackowledgement: Dave Wilson for waveform diagram

77 Phase Shifted PWM Example V+ Top Left Bottom Left FlexTimer Top Right Bottom Right Left Side Right Side Can be used with transformer circuits since H-bridge load sees no DC. Transistors always see 5% duty-cycle (no narrow pulses). Transformer Transformer RMS voltage is controlled by phase difference between left side and right side PWMs.

78 56F8 Feature Highlights - Quad Timers JTAG/EOnCE Voltage Regulators Interrupt Controller Power Supervisor COP MSCAN 3-PIT Flash RAM 568E Core 32 MIPS 32 MHz 6-Bit Timers System Integration Module (SIM) 6 Output PWM 8 6bit Timers Up to 6 Input 2-bit ADCs 2-QSCI 2-QSPI I 2 C 2-2bit DACs 2-Analog Comparators System Clock Control (PLL, SIM, Osc) Up to 96 MHz operation Four 6-bit general purpose up/down timers Individually programmable Input capture trigger Output compare capture Selectable input clock source Quadrature Decode Pulse Generation Input pins are shareable within a timer module Each timer has separate prescalar Counters are preloadable Counters in module can be daisy-chained to yield longer counter lengths, up to 64-bits Up to 2 operating modes Timer outputs can generate PWM complementary pair output signals

79 Quad Timer: Simple Operating Modes Stop Mode - Counter is inert. No counting will occur Count Mode Counts rising or falling edges (generating periodic interrupts, timing purposes) Edge Count Mode Counts rising and falling edges (counting of simple encoder wheel) Gated Count Mode - Counts primary input if secondary input is high (signal width measurement) Signed Count Mode Counts primary input up or down based on polarity of secondary input Cascaded Count Mode - Input is connected to the output of another (Great for large counts up to 2 64 ) Primary Secondary Count 2 2 Timer Timer Timer2 Timer3

80 Quad Timer: Triggered Modes Triggered Count Mode Start/Stop count of Primary input on rising edge of Secondary input. One-Shot Mode - Provides timing delays (ADC acquisition of new samples until a specified period of time has passed since the PWM sync signal occurred)

81 Quad Timer: Other Modes Fixed Frequency PWM - Fixed frequency, variable duty cycle (driving PWM amplifiers) Variable Frequency PWM - Variable frequency and duty cycle (driving PWM amplifiers) Pulse Output Mode - Supports stepper motor systems and provides change of signal frequency and number of pulses Count Mode Timer is Off Timer is in Count Mode Quadrature Count Mode Counter will decode the primary and secondary external inputs as quadrature encoded signals Compare interrupts will signal commutation Primary Count Output Timer Stopped due to Compare (COMP = 4)

82 56F8 Feature Highlights Analog to Digital Converters JTAG/EOnCE Voltage Regulators Interrupt Controller Power Supervisor COP MSCAN 3-PIT Flash Analog to Digital Converter System Integration Module (SIM) RAM 568E Core 32 MIPS 32 MHz Note: 56F83xx conversion time: Sequential: First.7us Subsequent.2 us Simultaneous: 8 conversions in 5.3us 6 Output PWM 8 6bit Timers Up to 6 Input 2-bit ADCs 2-QSCI 2-QSPI I 2 C 2-2bit DACs 2-Analog Comparators System Clock Control (PLL, SIM, Osc) 2-bit resolution Two ADCs per module 6 to 8 Analog Inputs per module Independent sampling frequency per ADC Sampling rate up to.667 million samples per second Sequential: First.59us subsequent.25us Simultaneous: 8 conversions in 4.48us Can be internally synchronized to a PWM reload event Simultaneous or sequential sampling Optional sample correction by subtracting a preprogrammed offset value 4 Interrupt types: End of a scan, zero crossing, High/Low limit High/Low Limits can control PWM outputs Signed or unsigned result Single-ended or differential inputs for all input pins with support for an arbitrary mix of input types Power savings modes Explicit power down of all/part of ADC Intelligent power savings mode: Auto wake-up Internal or External Voltage Reference

83 ADC Digital Comparators OFF Limit and Threshold Detection Programmable Upper limit Programmable Threshold limit Programmable Lower limit Over-voltage shut-down level Optional ADC Interrupt (can be selected) ISR ISR ISR ISR ISR ISR The ADC can perform limit checking and zero crossing detection with NO CPU intervention. Each channel has its own upper, lower, and threshold comparators.

84 56F8 ADC Channel Scan Modes Once The ADC starts to sample just one time whether you use the START bit or by a sync pulse. This mode must be re-armed by writing to the ADCR register again if you want to go capture another scan Triggered Sampling begins with every recognized START command or sync pulse Loop The ADC continuously take samples as long as power is on and the STOP bit has not been set Sequential Mode Sequential will sample SampleN one after another. Channel ANAx are sampled by ADCA and Channel ANBx are sampled by ADCB Parallel Mode Simultaneous: Parallel can sample SampleN from Group and SampleN from Group 2 at the same time. Independent:: ADCA and ADCB can operate independently. At end of scan of each ADC, they generate separate interrupt request. ANA ANA ANA2 ANA3 ANB ANB ANB2 ANB3 SYNCx Sequential Mode MUX Simultaneous ANA ANA ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 SYNCA VREFHI VREFLO Sample/ Hold Controller Controller Voltage Reference Circuit Scaling and Cyclic Converter A Scaling and Cyclic Converter B 2 2 Result Reg Result Reg Result Reg 2 Result Reg 3 Result Reg 4 Result Reg 5 Result Reg 6 Result Reg 7 VRETH VREFP Voltage VREFM Reference Result Reg Mode ID Circuit VREFN Result Reg VREFLO MUX Sample/ Hold Scaling and Cyclic Converter A Scaling and Cyclic Converter A 2 2 Result Reg 2 Result Reg 3 Result Reg 4 Result Reg 5 Result Reg 6 Result Reg 7

85 56F8 Digital to Analog Converters JTAG/EOnCE Voltage Regulators Interrupt Controller Power Supervisor COP MSCAN 3-PIT Flash Digital to Analog Converters System Integration Module (SIM) RAM 568E Core 32 MIPS 32 MHz 6 Output PWM 8 6bit Timers Up to 6 Input 2-bit ADCs 2-QSCI 2-QSPI I 2 C 2-2bit DACs 2-Analog Comparators System Clock Control (PLL, SIM, Osc) 2 bit Resolution Up to Two independent voltage mode DACs 2us settling time settling time when output swing from rail to rail at 3KΩ/4pf load Output glitch filter to eliminate switching glitches Two output update modes Asynchronous Update On-demand Synchronous Update based on PIT or Timer Overflow, or PWM synch signal Automatic waveform generation generates square, triangle and saw-tooth waveforms with programmable period, update rate, and range Software controlled power down mode

86 56F8 Analog Comparators JTAG/EOnCE Voltage Regulators Interrupt Controller Power Supervisor COP MSCAN 3-PIT Flash RAM 568E Core 32 MIPS 32 MHz Analog Comparators System Integration Module (SIM) 6 Output PWM 8 6bit Timers Up to 6 Input 2-bit ADCs 2-QSCI 2-QSPI I 2 C 2-2bit DACs 2-Analog Comparators System Clock Control (PLL, SIM, Osc) Up to Two continuous-time differential-input analog comparator modules Internal switching matrix supports independent connection of the analog inputs to the positive or negative input of the analog comparator and to the comparator s export output for another Comparator module. 5 selectable Input sources: Three GPIO Pins. One DAC output, One import input from another comparator module Programmable comparator output polarity Comparator output edge indicator Interrupt can be generated by comparator output rising edge, or falling edge, or both edges Comparator output can be fed to timer input, PWM fault input, PWM source, external pin. Software controlled power down mode

87 Analog Comparator Interconnection Positive input Source Select PSEL [,2] CIN_A CIN_A CIN_A2 DAC_A Export Source Select M U X Negative input Source Select ESEL [,] NSEL [,2] Power Down PDN + - CMP_A INV Programmable Glitch Filter Falling Edge Interrupt Request Rising Edge Interrupt Request COUT To Timer A To PWM Export to CMP_B M U X M U X To GPIO To PWM Fault Import From CMP_B

88 DAC and Comparator Application - Fault signal detection for Motor Control, UPS and SMPS Inside DSP DC Bus Current DAC-A - + COMP_B PWM Fault_ Inside DSP DC Bus Voltage DAC-B - + COMP_A PWM Fault_2

89 DAC and Comparator Application - timer And/Or ADC Triggering Inside DSP Analog input DAC-A - + COMP_B Timer_ ADC_B Inside DSP Analog Input 2 DAC-B - + COMP_A Timer_2 ADC_A